ETC T108

T108 Release
Copyright by Terawins, Inc.
Release
Version 1.0
May 27, 2007
T108 Video Display Controller
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T108 Release
Copyright by Terawins, Inc.
Contents
1
Introduction .................................................................................................................... 3
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
Features ................................................................................................................................................. 3
General Description ............................................................................................................................... 4
Applications............................................................................................................................................ 4
System Architecture............................................................................................................................... 5
System Configurations........................................................................................................................... 6
Pinout Diagram ...................................................................................................................................... 7
Pin Description ....................................................................................................................................... 8
Theory of Operations ................................................................................................... 11
2.1
2.2
2.3
2.4
2.5
2.6
3
I²C Command Protocol ........................................................................................................................ 11
Analog Front End ................................................................................................................................. 13
Black-Level Extension (BLE) ............................................................................................................... 14
Color Space Converter ........................................................................................................................ 14
Gamma Correction............................................................................................................................... 15
OSD1 ................................................................................................................................................... 16
Register Description .................................................................................................... 37
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
4
ADC Register Set................................................................................................................................. 37
Input Timing Register Set .................................................................................................................... 45
Picture Enhancement Register Set...................................................................................................... 51
Scaling Register Set ............................................................................................................................ 54
Gamma and Pattern Gen. Register Set............................................................................................... 58
OSD1 Register Set .............................................................................................................................. 60
LCD Output Control Register Set......................................................................................................... 60
Global Control Register Set ................................................................................................................. 67
TCON Register Set .............................................................................................................................. 73
Infra-Red Register Set ......................................................................................................................... 75
ITU - 656 Decoder Register Set........................................................................................................... 76
Y/C Separation and Chroma Decoder Register Set ............................................................................ 79
Electrical Characteristics............................................................................................. 84
4.1
4.2
4.3
4.4
4.5
Digital I/O Pad Operation Condition..................................................................................................... 84
DC Characteristics ............................................................................................................................... 85
AC Characteristics ............................................................................................................................... 86
Analog Processing and A/D Converters .............................................................................................. 86
I²C Host Interface Timing ..................................................................................................................... 87
5
Package Dimensions ................................................................................................... 88
6
Ordering Information.................................................................................................... 88
7
Revisions Note ............................................................................................................. 89
8
General Disclaimer ....................................................................................................... 89
9
Contact Information ..................................................................................................... 89
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T108 Release
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1 Introduction
1.1 Features

Cost Effective Highly Integrated Triple ADC +
ITU656/601 Decoder + Digital RGB + 2D Video
Decoder + OSD + Scaler + TCON + DAC + DCto-DC + LED/CCFL controls
- Integrates 10-bit Triple Analog to Digital
Converters (ADC) & Phase Locked Loop
(PLL), for supporting CVBS, S-Video, YPbPr
and RGB inputs
- Scaler supports 2-D adaptive intra-field deinterlacer and non-linear 16:9 aspect ration.
- Requires no external Frame Buffer Memory
for de-interlace.
- ITU656/601_8/L601_16 Decoder with digital
input ports for standard ITU656/601 input
data.
- Support digital RGB565 inputs
- Advanced On Screen Display (OSD) function
- Programmable Timing Controller (Tcon) for
Car TV applications
- Multi-standard color decoder with 2D
adaptive comb filter
- Innovative and flexible design to reduce total
system cost
-
-
Triple 10-bits ADCs
- 80MSPS Conversion Rate ADC
- Built-in Pre-amp, mid-level & ground clamp
- Automatic Clamp Control for CVBS, Y and C
- Programmable Static Gain Control or
Automatic Gain Control for CVBS or Y/C
- Max Input configuration up to 9xCVBS, 3xSvideo+3xCVBS, 3YPbPr
- Build-in Line-Lock PLL for RGB and YPbPr
- Phases Tracking and Boundary for adjusting
input quality.
Digital Video Enhancement
- Separate Luminance and Chroma Enhancer
- Y Supports Luminance Black Level
Extension., Contrast and Brightness
adjustment
- C Supports DCTI, Saturation and Hue
adjustment.
FIR Based Advanced Scaling Engine
- Coefficient based sharpness filters
- Independent vertical and horizontal scaling
ratio
- 16:9 Non-linear Aspect ratio
Provides 256-entry TBL Gamma correction
for panel compensation
Supports image pan functions
Programmable Timing Controller
Built-in software adjustable VCOM voltage
RGB Triple DAC output
Integrated high efficiency DC-DC power
conversion unit for gate and source drivers
reduces energy consumption
Integrated TFT-LCD backlight inverter drive
unit supports CCFL/LED typed backlight
Software adjustable lamp dimming

Built-in On Screen Display Engine
- 8K-word OSD1 memory
- Supports text or bitmap modes
- Supports character blinking and overlay
functions
- Fully programmable character mapping
- Supports alpha blending & Zoom-in/Zoomout function
- Built-in 114+ fonts (18x12, 24x16 each)
- Optional fonts stored in off-chip serial ROM
- Optional Pattern-Filled background

Crystal Oscillator Circuit
- Direct interface to a (27.0MHz or other
frequency) Crystal
- Also provide a buffered clock output for
external Micro-controller

Digital Test Pattern Generator
- Programmable standard & special panel
burn-in test patterns
- Support special border frame blocking mode

Independent Display Phase Lock Loop
- Generates pixel clock output to panel
- Supports free run OSD mode

Serial Bus Interface
2
- Supports 2-wire I C (Slave/Master)

Pulse Width Modulation Outputs

Design For Testability
- Scan chain insertion
- Separated analog & digital test modes

Power Supply: +1.8V, +3.3V and +5V

Package: 100 pin LQFP
LCD Interface
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1.2 General Description
The T108 is a highly integrated All-in-one
Visual Processor that provides major cost saving
solution for the portable applications. T108 has builtin high performance Triple ADCs, TCON, triple DACs.
Scaling Machine with sophisticated upscaling and
downscaling algorithms. The Innovative integrated
“Frame-Buffer-Less” De-interlacer can significantly
reduce system cost. The T108 also integrates
enhanced two layer OSD engines. The device can
interface to an external micro-controller through 2wire serial bus interface.
1.3 Applications
1. Small to medium sized displayer, In-car TV
2. Progressive CRT TV
3. GPS mobile display application
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1.4 System Architecture
T108 Block Diagram
CVBS,
S-Video,
YPbPr,
RGB
ADC
Analog
Front End
Control
ADC
ADC
Input
Sample Rate
Converter
Y/C
Separation
U/V
Demodulation
Line Buffers
ADC
Format
Detection
PLL
2D-Adaptive
Comb Filter
VBI
Decoder
FIFO
HIS, VSI,
SOYIN
Video Decoder
Slicer /
Sync_Sep
ITUR656
Decoder
Y
CC/TTX
Mixer
Zoom
CbCr
RGB565
Image Capture & Enhancer
VIP
Color Processor
Ext_OSD
Mixer
YUV_To_
RGB
2D DeInterlacer
Gamma
Dither
+
DCTi /
Hue /
Saturation
Line Buffers
LCD Control
Analog Output
Serial
RGB
VCOM
TCON
PT_GEN
I2C
Slave
RSTB
SDA, SCL
IR Decoder,
PWM
OSD1
RAMs / ROMs
IR1, PWM1
VCOM
DC
Converter
Swap
DAC
DAC
DAC
Timing
Gen
Display PLL
CCFL/LED
R/ G/ B
Misc.
CPH[3:1], TCON/sRGB
XCLK2MC
L601_8/16
RGB_To_YUV
422_to_444
XCLKO
Input
MUX /
Capture
Scaler
Black Level
Expansion /
Peaking /
DLTi /
Contrast /
Brightness
XCLKI
VCLK, LODD,
LHREF, DHDEI,
LVC[7:0],
LVY[7:0]
CC_BOX,
CC_Color[3:0],
CC_CKO,
CC_VSO,
CC_HSO
YCbCr
Post-filtering
Figure 1-1 System Architecture
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1.5 System Configurations
CVBS
Y
S-VIDEO
C
CCFL/LED
TV Tuner
T108
Y
Pb
Component
Pr
R
G
B
HSYNC
VSYNC
RGB
Video
Display
Controller
TCON Signals
TFT-LCD
I2C
Video
Decoder
V656/L601
GPS
RGB565/666/888
8051
MCU
Figure 1-2 System Configurations
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1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
1
1
1
1
1
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
VD5A
LVY7/DRI7
LVY6/DRI6
LVY5/DRI5
LVY4/DRI4
LVY3/DRI3
LVY2/DGI7
LVY1/DGI6
GND
VDD18
LVY0/DGI5
STV2/sD7
STV1/sD6
GOE/OEV/sD5
GCLK/CKV/sD4
VDD33
LP/OEH/VCOM_I/sD3
Q1H/sD2
GND
CPH3/LLCK3/sD1
CPH2/LLCK2/sD0
CPH1/LLCK1/CLKO
DEO/STH2
VSO/STH1
HSO/POL/VCOM
1.6 Pinout Diagram
2
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
1
1
1
1
1
1
LHREF/DHSI
LODD/DVSI
LVCLK
VDD18
LVC7/DGI4
LVC6/DGI3
LVC5/DGI2
LVC4/DBI7
LVC3/DBI6
LVC2/DBI5
LVC1/DBI4
LVC0/DBI3
GND
VDD33
PWM1
IR1
XCLKO
XCLKI
CPUINT/GPOB3 (Strap: I2C_A3)
XCLK2MC/GPIO3
SCL
SDA
RSTB
HSI
VSI
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1 1
1
13
3
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
1
1
1
1
1
1
OLR (SOYIN)
SOYIN(SAR1)
AVDDB
ACB2
ACB1
ACB0
AGNDB
AVDDG
AY2
AY1
AY0
AGNDG
AVDDR
ACR2
ACR1
ACR0
AGNDR
GNDP
PVS33
VPLL
FILT
AVDDP
PVD33
GND
VDD18
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
VS5A
IOB
IOG
IOR
RSET
VBGF
VCOMAMP
VCOMDC
VD33DAC
VEA
CSS
VFB
CEXT
VPWM
VD33PWM (VISen)
VS33PWM (VD33PWM)
VEAI (VS33PWM)
VFBI (VEAL)
VPWMP (VFBL)
VPWMN (VPWML)
VCKP (NC)
VCKN (NC)
CSSI (CSSL)
CEXT1 (CEXT1L)
OLP (VISenL)
Figure 1-3 Pinout Diagram
Pin 90-100, 1, 2: CCFL (LED) Backlight Pin Definitaion
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1.7 Pin Description
Table 1-1 Pin Description
Symbol
Pin #
Type
25, 47, 66
37, 60
3
8
13
75
84
90 or 91(LED)
22
23
24, 38, 57, 67
7
12
17
76
91 or 92(LED)
18
19
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
GND
GND
Description
Power Supplies
VDD18
VDD33
AVDDB
AVDDG
AVDDR
VD5A
VD33DAC
VD33PWM
AVDDP
PVD33
GND
AGNDB
AGNDG
AGNDR
VS5A
VS33PWM
GNDP
PVS33
+1.8V digital core power supply
+3.3V digital output power supply
+3.3V analog power supply for ADC channel 2
+3.3V analog power supply for ADC channel 1
+3.3V analog power supply for ADC channel 0
+5.0V analog power supply for DAC
+3.3V analog power supply for DAC
+3.3V analog power supply for DC Converter
+1.8V analog power supply for PLL
+3.3V analog power supply for PLL
Digital ground
Analog ground for ADC channel 2
Analog ground for ADC channel 1
Analog ground for ADC channel 0
Analog ground for DAC
Analog ground for DC Converter
Analog ground for PLL
Analog ground for PLL
Output Interface Signals
IOR
IOG
IOB
VCOMAMP
VCOMDC
VCOM_i
LLCk1
LLCk2
LLCk3
79
78
77
82
83
59
54
55
56
AO
AO
AO
AO
AO
DI, P/D
DO, P/D
DO, P/D
DO, P/D
Channel R current output
Channel G current output
Channel B current output
VCOM output
VCOM output
VCOM input
Output Data Clock
Output Data Clock
Output Data Clock
Timing Controller Interface Signals
POL/VCOM
STH1
STH2
Q1H
LP/OEH
GCLK/CKV
GOE/OEV
STV1
STV2
51
52
53
58
59
61
62
63
64
DO, P/D
DO, P/D
DO, P/D
DO, P/D
DO, P/D
DO, P/D
DO, P/D
DO, P/D
DO, P/D
Horizontal Polarity Output Signal. Share w/ HSO
Horizontal Start Pulse 1 Signal. Share w/ VSO
Horizontal Start Pulse 2 Signal. Share w/ DEO
Panel polarity control
Latch pulse for column driver
Gate driver clock
Gate driver output enable
Gate driver start pulse
Gate driver start pulse
Power Management Signals
VEA
CSS
VFB
85
86
87
AO
AO
AI
Error Amplifier output
Soft Start
Feedback of Lamp current
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Symbol
Pin #
Type
CEXT
VPWM
VISen
VEAI/VEAL
VFBI/VFBL
VPWMP/VPWML
VPWMN
VCKP/NC
VCKN/NC
CSSI/CSSL
CEXT1/CEXT1L
OLP/VISenL
OLR
88
89
90(LED)
92/93
93/94
94/95
95(CCFL)
96
97
98
99
100
1(CCFL)
AO
AO
AI
AO
AI
AO
AO
AO
AO
AO
AO
AI
AI
Description
Switching frequency of DC-DC converter
PWM output, connect o external N-channel power MOSFET
Feedback of DC-DC current
Error Amplifier output
Feedback of Lamp current
PWM output, drive PMOSFET switch
PWM output, drive NMOSFET switch
Clock output, drive PMOSFET switch
Clock output, drive NMOSFET switch
Soft Start
Switching frequency of Inverter
Open Lamp Protection/Current Limit
Open Lamp Regulation
Serial Panel Interface Signals
VSO
HSO
52
51
DO, P/D
DO, P/D
DEO
CLKO
sD0~sD7
53
54
55~56, 58~59,
61~64
DO, P/D
DO, P/D
DO, P/D
Vertical Synchronization Output Control Signal. Share w/ STH1
Horizontal Synchronization Output Control Signal. Share w/
POL/VCOM
Horizontal Output Data Enable Signal. Share w/ STH2
sPanel clock
sPanel data, share w/ TCON signals
Configuration Interface Signals
RSTB
SDA
SCL (SCANB)
28
29
30
XCLK2MC
CPUINT (A3)
31
32
DI, P/U Whole chip reset.
DIO, P/U 2-wire serial bus data. Power down does not affect SDA.
DIO, P/U 2-wire serial bus clock. Power down does not affect SCL. This pin
should be high when RSTB asserted for avoid entering Scan test
mode.
DO
Buffered XCLKI for external microprocessor.
DIO, P/U Internal Interrupt.
This pin is a reset strap pin for I2C device address. When RSTB
2
goes high, if this pin is high, then default I C device address is 50h,
else 40h.
ADC, PLL, Slicer Interface
ACB2
ACB1
ACB0
AY2
AY1
AY0
ACR2
ACR1
ACR0
VSI
HSI
SOYIN
SAR1
VPLL
FILT
4
AI
5
AI
6
AI
9
AI
10
AI
11
AI
14
AI
15
AI
16
AI
26
DI, P/D
27
DI, P/U
2(CCFL), 1(LED)
AI
2(LED)
AI
20
AI
21
AI
Analog input 2 of channel 2
Analog input 1 of channel 2
Analog input 0 of channel 2
Analog input 2 of channel 1
Analog input 1 of channel 1
Analog input 0 of channel 1
Analog input 2 of channel 0
Analog input 1 of channel 0
Analog input 0 of channel 0
RGB Vertical Synchronous input
RGB Horizontal Synchronous input
Sync on Y (of component) input
SARADC for keypads sense
PLL Reference
PLL filter
Video-In Interface: ITUR656
LVC0~7
39~46
DI, P/D
Video data port of the 2nd ITU-656
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Symbol
Pin #
Type
LVCLK
48
DI, P/D
Description
Video clock of the 2nd ITU-656 (2x pixel rate)
Video-In Interface: L601_8bit
LVC0~7
LVCLK
LODD/LVSYNC
LHREF/LHSYNC
39~46
48
49
50
DI, P/D
DI, P/D
DIO, P/D
DIO, P/D
Video data port of 8-bit 601 or Chroma
Video clock (2x pixel rate)
ITU-601 Odd or VSync input
ITU-601 HREF(HDE) or HSync input
Video-In Interface: L601_16bit
LVC0~7
LVY0~7
LVCLK
LODD/LVSYNC
LHREF/LHSYNC
39~46
65, 68~74
48
49
50
DI, P/D
DI, P/D
DI, P/D
DIO, P/D
DIO, P/D
Video chroma data port of 16-bit 601
Video Luma data port of 16-bit 601
Video clock (1x pixel rate)
ITU-601 Odd or VSync input
ITU-601 HREF(HDE) or HSync input
Video-In Interface: RGB565
DRI3~7
DGI2~7
DBI3~7
LVCLK
DVSI
DHSI
70~74
44~46, 65,
68~69
39~43
48
49
50
DI, P/D
DI, P/D
Digital RGB input: 5 MSB bits of Color R
Digital RGB input: 6 MSB bits of Color G
DI, P/D
DI, P/D
DIO, P/D
DIO, P/D
Digital RGB input: 5 MSB bits of Color B
Video clock (1x pixel rate)
Digital RGB VSync input
Digital RGB HSync input
33
34
35
36
80
81
DI
DO
DI, P/U
DIO, P/D
AI
AI
Output PLL reference clock input and I2C, timer operating clock
Output PLL reference clock output
IR input
Pulse Width Modulation 1 for backlight control / Volume / …
DAC reference current adjust
DAC voltage reference output
Misc. Signals
XCLKI
XCLKO
IR1
PWM1
RSET
VBGF
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2 Theory of Operations
2.1 I²C Command Protocol
Before your tester writes I²C commands to T108, slave address must be set at 50h. The timing
sequence can be shown as below. After 4 cycles, the tester can get started IIC commands. CPUINT(A3)
can affect slave address. Set it low for 40h, and high for 50h.
2 Cycles 2 Cycles
XTALI
RSTB
Don　care
SDA
SCL
Don　care
Figure 2-1 Power-Up Initialization
When tester issues commands to the T108, the only way the user can program the T108 is
using the 2-wire serial bus protocol. This section describes the 2-wire serial bus protocol. Data transfers
on the 2-wire serial bus are initiated with a START condition and are terminated with a STOP condition.
Normal data on the SDA line must be stable during the high period of the SCL. The transition on the
SDA is only allowed while SCL is low. The START condition is unique case and is defined by a high-tolow transition on the SDA while the SCL is high. The STOP condition is a unique case and is defined by
a low-to-high transition on the SDA while the SCL is high. Each data packet on the 2-wire serial bus
consists of 8 bits of data followed by an ACK bit. Data is transferred with MSB first. The transmitter
releases the SDA line during the ACK bit and the receiver of data transfer must drive the SDA line low
during the ACK bit to acknowledge receipt of the data. The frequency of SCL can be from 50 KHz up to
2 MHz (~=XCLK/12).
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SDA
B it7
B it6
1
2
SCL
S
3
7
9
P
ACK
S to p
C o n d it io n
8
S ta rt
C o n d it io n
Figure 2-2 Basic I2C Bus Protocol
The timing below shows a typical T108 I2C single byte write command,
Slave Address
SDA
A7
Write CMD
A6
A1
2
7
SCL
S
1
8
Register Address
9
R7
R6
1
2
Data being written to Register
R1
R0
7
8
9
ACK
Start
Condition
D7
D6
1
2
D1
D0
7
8
9
P
ACK
Stop
Condition
Figure 2-3 T108 I2C Single Byte Write Command
The timing below shows a typical T108 I2C single byte read command,
Slave Address
Write CMD
Slave Address
Restart
Register Address
Read CMD
Data being Read
Not Ack
SDA
A7
A6
A1
2
7
SCL
S
Start
Condition
1
8
9
ACK
R7
R6
1
2
R1
R0
7
8
A7
9
1
A6
A1
2
7
8
9
ACK
ACK
D7
D6
1
2
D1
D0
7
8
9
P
Stop
Condition
Figure 2-4 T108 I2C Single Byte Write Command
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2.2 Analog Front End
T108 contains 3 ADCs in Analog Front End. Each channel of ADCs can digitalize SDTV signals from
analog to digital. The figure shown below can describe how to select a SDTV signal from 3 inputs prior to
ADC.
Figure 2-5 Analog Front End MUX
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2.3 Black-Level Extension (BLE)
Black Level Expansion (BLE) can enhance image contrast that makes dark regions of image darker,
while bright regions remain unchanged. The figure shown below is BLE transfer function.
Y out
Without BLE
With BLE
Y in
BLE_threshold
Figure 2-6 Black Level Expansion
Yout = Yin − (Yoffset − Yin) * BLE _ Gain / 16
Where Yoffset and BLE _ Gain can be programmed by register P0_96h.
2.4 Color Space Converter
A pixel in YCbCr color space can be converted to RGB color space by using following equations,
R = YCoef _ R * (Y − 16) + / − CbCoef _ R * (Cb − 128) + CrCoef _ R * (Cr − 128)
G = YCoef _ G * (Y − 16) − CbCoef _ G * (Cb − 128) − CrCoef _ G * (Cr − 128)
B = YCoef _ B * (Y − 16) + CbCoef _ B * (Cb − 128) + / − CrCoef _ B * (Cr − 128)
The equations shown as below correspond to a typical YCbCR-to-RGB converter.
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2.5 Gamma Correction
The relation between input video signal and LCD panel may exist non-linear transfer function
such as figure shown below,
R /G /B o u t
G am m a 255
G am m a 248
G am m a 2
G am m a 1
R /G /B in
255
248
16
8
0
G am m a 0
Id e a l T ra n s fe r F u n c tio n
T 1 0 8 G a m m a C o rre c tio n
Figure 2-7 Gamma LUT
T108 uses 33-point piece-wise linear interpolation instead of RAM-based LUTs. Each point can be
programmed via register at P0_93h and P0_94h.
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2.6 OSD1
The OSD1 in T108 is improved in rendering and efficient memory usage. The legacy OSD is either one thread
Menu or one graphic (BMP) mode. T108 OSD1 supports two threads menus and 1 graphic rendering
simultaneously. So it will be easier to have menu control and Closed Caption.
2.6.1
OSD1 RAM Partition
The OSD1 Font/Menus/BMP memory share the same built-in 8Kx16 SRAM.
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OSD1 Register Map
I/O Port
Groups
Global
Setting
Menu-1
Setting
A0h – OSD1_Index
A1h – OSD1_Data
ROM
Font
Menu-2
Setting
BMP
Setting
Index
Description
00h
OSD1 Enable/Blinking Register
01h
Font Size
02h
Char2BP Font Index Base
03h
Char4BP Font Index Base
04h
Char2BP Font Memory Base Address, LSB
05h
Char2BP Font Memory Base Address, MSB
06h
Char4BP Font Memory Base Address, LSB
07h
Char4BP Font Memory Base Address, MSB
08h
OSD1 Color LUT Address port
09h
OSD1 Color LUT Data Port
0Ah
OSD1 Window Shadow
0Bh
Global Alpha Blending Control
0Ch
Char1BP color high bits offset
0Dh
ROM Font Index Base
0Fh
Revision ID
10h
Menu-1 Enable
11h
Menu-1 Start Address, LSB
12h
Menu-1 Start Address, MSB
13h
Menu-1 End Address, LSB
14h
Menu-1 End Address, MSB
16h
ROM Font Memory Base Address, LSB
17h
ROM Font Memory Base Address, MSB
18h
Menu-2 Enable
19h
Menu-2 Start Address, LSB
1Ah
Menu-2 Start Address, MSB
1Bh
Menu-2 End Address, LSB
1Ch
Menu-2 End Address, MSB
20h
BMP Control Register
21h
BMP Start Address, LSB
22h
BMP Start Address, MSB
23h
BMP Alpha Blending Control
24h
BMP Horizontal Size, LSB
25h
BMP Horizontal Size, MSB
26h
BMP Vertical Size, LSB
27h
BMP Vertical Size, MSB
28h
BMP Position, Horizontal Start, LSB
29h
BMP Position, Horizontal Start, MSB
2Ah
BMP Position, Vertical Start, LSB
2Bh
BMP Position, Vertical Start, MSB
2Ch
BMP LUT Base Address
2Dh
BMP Background Color
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Groups
Block
Write
Index
Description
40h
Block Write Data LSB
41h
Block Write Data MSB
42h
Block Write Starting Address LSB
43h
Block Write Starting Address MSB
44h
Block Write Count
45h
Block Write Control
A2h – ORAM_A
OSD1 RAM Address Port of Starting Access (LSB A[7:0] first, then MSB A[12:8]).
A3h – ORAM_D
OSD1 RAM Data Port (Low Byte first, then High Byte). After two Writes, the
address will be increased by 1.
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OSD1 Color Scheme
For drawing a graphic menu, a colorful icon or logo, …., T108 OSD1 provides 1BPP (one bit per pixel) ~ 5BPP
(5 bits per pixel) BMP coding. For n-BPP BMP, it has one background color and (2^n – 1) foreground colors.
For character menus with pre-defined fonts, T108 OSD1 provides mono characters (Char1BP) and color
characters (Char2BP, Char4BP), randomly mix-able. So that, simple icon can be implemented by color
characters. The color mapping of character/menu is more complicate, please refer to the following drawing.
The OSD1 main Color LUT is 256 entries SRAM, color in RGB565 format.
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Character RAM Format
T108 OSD1 character decoding supports 512 fonts. By setting FontROM, Char2BP and Char4BP Font Index
Base, we could assign different percentage for those character fonts, depends on application, menu color
requirement, memory size, fonts replacing, ...
The character “MENU” in T108 OSD1 is combined with 1~n character “ROW”s, each ROW can have its own
rendering behavior, such as alpha blending, position, zooming ratio, color groups, border/shadow modes, row
length,…, these are defined as ROW Attributes (RAtt, current version supports 8 types). Or, few rows can share
the same setting without redefining those RAtt.
2.6.4.1 Character Format
Each character is 16-bits length, includes foreground/background color, blinking, font index.
Bit
Symbol
Description
[15:14]
BG_Color[1:0]
[13]
[12:9]
Blink
FG_Color[3:0]
[8:0]
Char_Index[8:0]
Background Color, which combined with the RAtt_C<10> to become 3 bit,
selects 6 background remap colors. If both 0, then transparent background.
Enable this Character display with blinking feature.
Foreground (FG) Color, depends font index is Char1BP, Char2BP or Char4BP:
1. When Char1BP, these 4 bits as FG LSB 4 bits, combine with RAtt_A<11:8>
(as FG MSB 4 bits), total 8 bits for selecting color LUT as character FG color. If
the value is set as 0000b, then there will be no foreground, i.e. transparent.
(Char1BP only)
2. When Char2BP, these 4 bits select one of 16 Char2BP remap LUT. Each
Char2BP remap LUT entry is 3*8 bits for 2BP font pixel value: 01b, 10b and 11b.
For 2BP font pixel value = 00b, then it will render as transparent.
3. When Char4BP, these 4 bits as FG MSB, then combine with 4BP font pixel 4
bits value to become 8 bits for addressing LUT. For 4BP font pixel value =
0000b, then it will render as transparent.
Character Address (Index), selects the character font (i.e., 0,1,2,.. A,B,C,
a,b,c,$,%,…). If the value is number N, then it selects the Nth font, and that font
starting address is (N x Font_Height ). The Font_Height is defined in
OSD1_01h<4:0>.
2.6.4.2 Row Attribute Alpha-Blending Type Format (RAtt_A)
Bit
Symbol
[15:12]
[11:8]
RAtt_ID = 1101b
FGC_1BP[7:4]
[7:6]
[5:4]
Reserved
FG_aB_Mode[1:0]
Description
Must set value 1101b for RAtt_A
Defines the MSB 4 bits for Char1BP FG color for current row or below in same
thread menu.
Defines the FG alpha-Blending mode (see OSD1 configuration register
OSD1_0B for detail) for current row or below in same thread menu.
[3:0] aB_Source_Percentage[3: Defines the alpha-Blending ratio (of source video/graphic) for current row or
0]
below in same thread menu.
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2.6.4.3 Row Attribute Character Type Format (RAtt_C)
This RAtt_C is a must-have attribute for each menu row, and those content in OSD1 memory followed will be
rendering as characters, not other row attributes except exceeding the row length (see Row_Length[5:0] below).
Bit
Symbol
[15:13]
[12]
RAtt_ID = 000b
Skip_This
[11]
[10]
[9:8]
[7:6]
[5:0]
Description
Must set value 000b for RAtt_C
When set to 1, the following one character row of current thread menu could be
skipped, and continues the next row instead.
End_After
When set to 1, the following all character rows of current thread menu will be
skipped.
BG_RGB[2]
Background color bit 2, combined with the BG_Color[1:0] in each character
become 3 bits to select background remap color.
CharHeight_Scale[1:0] Defines the enlarge ratio (x1, x2, x3, x4) of the character height of the menu
rows following and after.
CharWidth_Scale[1:0] Defines the enlarge ratio (x1, x2, x3, x4) of the character width of the menu rows
following and after.
Row_Length[5:0]
Indicates the following character row length (how many characters), valid value
range is 1 to 63.
2.6.4.4 Row Attribute Dummy Type Format (RAtt_D)
This RAtt_D is a dummy attribute, it is used for replacing other non-RAtt_C type attributes when changing
rendering behavior if need, also it is used when switch between rows with different BDS behavior, 4 lines will be
inserted.
Bit
Symbol
[15:0]
RAtt_ID = E001h
Description
Must set value E001h for RAtt_D
2.6.4.5 Row Attribute Gap Type Format (RAtt_G)
This RAtt_G is used to insert fix vertical null lines between menu rows.
Bit
Symbol
[15:13]
[12:11]
[10:0]
RAtt_ID = 001b
Reserved
Gap[10:0]
Description
Must set value 001b for RAtt_G
Line number inserted before the following menu row.
2.6.4.6 Row Attribute Jump Menu Type Format (RAtt_J)
This RAtt_J is used to redirect menu to other assigned new menu block in OSD1 memory. This is useful for
controlling menu flows.
Bit
Symbol
[15:14]
[13]
RAtt_ID = 10b
Jump_En
[12:0]
Jump_MenuA[12:0]
Description
Must set value 10b for RAtt_J
Set to 1 enables the menu jump to new assigned address in RAtt_J<12:0>.
When set to 0, this RAtt_J has no effect.
Jump to the OSD1 RAM address, which should still point to a row attribute of
menu.
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2.6.4.7 Row Attribute Horizontal Position Type Format (RAtt_H)
Bit
Symbol
[15:13]
[12:11]
[10:0]
RAtt_ID = 011b
Reserved
HStart[10:0]
Description
Must set value 011b for RAtt_H
Set the horizontal start position of the following menu rows.
2.6.4.8 Row Attribute Vertical Position Type Format (RAtt_V)
Bit
Symbol
[15:13]
[12:11]
[10:0]
RAtt_ID = 010b
Reserved
VStart[10:0]
Description
Must set value 010b for RAtt_V
Set the vertical start position of the following menu rows.
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OSD1 Configuration Registers
2.6.5.1 OSD1 Enable/Blinking Register
Address Offset:
Default Value:
Bit
Access
[7]
[6]
[5:4]
R/W
R/W
R/W
[3:2]
R/W
[1:0]
R/W
OSD1_00h
0Ah
Access:
Size:
Read/Write
8 bits
Symbol
Description
OSD1_En
Set to 1 for globally enabling OSD1 function.
Color_1_Half
Set to 1 for allowing shadow effect when color value is 1
CRAM_ByteAccess[1:0] Byte Access mode when programming character of menu:
0Xb: Word access (LSB first, then MSB byte)
10b: LSB only (not affect font index >= 256)
11b: MSB only (character BG/FG colors, Blinking, and Index bit 8)
BlinkFreq[1:0]
Blinking Frequency Select (internal 4x BCLK for Blinking State
Machine). Set 00b for Refresh Rate /16; 01b for 1/32; 10b for 1/64;
11b for 1/128.
BlinkDuty[1:0]
For adjusting the blinking duty cycle, Set:
00b for Global Blink Off, i.e., 0% Background, 100% Pattern Fill.
01b for 25% Background, 75% Pattern Fill.
10b for 50% Background, 50% Pattern Fill.
11b for 75% Background, 25% Pattern Fill.
2.6.5.2 OSD1 Font Size Register
Address Offset:
Default Value:
OSD1_01h
12h
Bit
Access
Symbol
[7]
[6]
[5]
R/W
R/W
R/W
vDE_from_VS
hDE_from_HS
FontW16
[4:0]
R/W
FontHeight[4:0]
Access:
Size:
Read/Write
8 bits
Description
Shift OSD1 more up
Shift OSD1 more left
Set Font Width:
0b: Font Width = 12
1b: Font Width = 16
Font Height, valid value between 1 and 24
2.6.5.3 OSD1 Char2BP Font Index Base Register
Address Offset:
Default Value:
OSD1_02h
80h
Access:
Size:
Read/Write
8 bits
Bit
Access
Symbol
Description
[7:0]
R/W
Font_Index_2BP[8:1]
Defines the Char2BP font index base (offset). When character index
small than this value*2 will be decoded as Char1BP (mono char). And
if the character index greater than or equal to this value*2 will be
decoded as Char2BP (<= Font_Index_4BP * 2).
2.6.5.4 OSD1 Char4BP Font Index Base Register
Address Offset:
Default Value:
OSD1_03h
C0h
Bit
Access
Symbol
[7:0]
R/W
Font_Index_4BP[8:1]
Access:
Size:
Read/Write
8 bits
Description
Defines the Char4BP font index base (offset). When character index
small than this value*2 will be decoded as Char1BP (mono char) or
Char2BP; else, Char4BP.
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2.6.5.5 OSD1 Char2BP Font Memory Base Address LSB Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
OSD1_04h
00h
Access:
Size:
Read/Write
8 bits
Symbol
Description
Font_BaseA_2BP[7:0] Defines the Char2BP font in memory, start with this base address
(offset).
2.6.5.6 OSD1 Char2BP Font Memory Base Address MSB Register
Address Offset:
Default Value:
Bit
Access
[7:5]
[4:0]
RO
R/W
OSD1_05h
0Ch
Access:
Size:
Read/Write
8 bits
Symbol
Description
Reserved
Font_BaseA_2BP[12:8] Defines the Char2BP font in memory, start with this base address
(offset).
2.6.5.7 OSD1 Char4BP Font Memory Base Address LSB Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
OSD1_06h
00h
Access:
Size:
Read/Write
8 bits
Symbol
Description
Font_BaseA_4BP[7:0] Defines the Char4BP font in memory, start with this base address
(offset).
2.6.5.8 OSD1 Char4BP Font Memory Base Address MSB Register
Address Offset:
Default Value:
Bit
Access
[7:5]
[4:0]
RO
R/W
OSD1_07h
0Fh
Access:
Size:
Read/Write
8 bits
Symbol
Description
Reserved
Font_BaseA_4BP[12:8] Defines the Char4BP font in memory, start with this base address
(offset).
2.6.5.9 OSD1 LUT Address Register
Address Offset:
Default Value:
OSD1_08h
00h
Access:
Size:
Write Only
8 bits
Bit
Access
Symbol
Description
[7:0]
WO
LUT_A[8:1]
Assign access pointer of Color LUT. When assigning, LUT_A[0]
always = 0. LUT[0..255] are main color LUT (16-bits); LUT[256..271]
are Char2BP remap LUT (24-bits); LUT[272..273]are BMP remap LUT
(24-bits).
2.6.5.10 OSD1 LUT Data Port Register
Address Offset:
Default Value:
OSD1_09h
00h
Bit
Access
Symbol
[7:0]
WO
LUT_D[7:0]
Access:
Size:
Write Only
8 bits
Description
Data written to this port will overwrite OSD1 LUT.
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2.6.5.11 OSD1 Window Shadow Width/Height Register
Address Offset:
Default Value:
Bit
Access
[7:4]
[3:0]
R/W
R/W
OSD1_0Ah
46h
Access:
Size:
Read/Write
8 bits
Symbol
Description
Wx_ShadowWidth[3:0] Defines the shadow width (count in 2 dots).
Wx_ShadowHeight[3:0] Defines the shadow height (count in 2 lines).
2.6.5.12 OSD1 Global Alpha-Blending Control Register
Address Offset:
Default Value:
OSD1_0Bh
1Ah
Bit
Access
Symbol
[7]
R/W
Global_aB_Control
[6]
[5:4]
RO
R/W
[3:0]
R/W
Access:
Size:
Read/Write
8 bits
Description
Set to 1 for all the alpha-blending behavior of Menu-1, Menu-2 and
BMP are control by this register; Set to 0 for separate controls.
Reserved
Global_FG_aB_Mode[1:0]Defines global alpha-blending for foreground when BG already alphaBlended:
00b: All FG need alpha-Blended if BG is alpha-Blended;
01b: All FG no need alpha-Blended;
10b: All FG no need alpha-Blended, except their color is LUT[1];
11b: All FG no need alpha-Blended, except their color is LUT[1..3];
Global_aB_SourcePercentDefines the percentage of source image/video for mixed with OSD1
[3:0]
menu.
2.6.5.13 OSD1 Char1BP Color High bits Register
Address Offset:
Default Value:
OSD1_0Ch
00h
Bit
Access
Symbol
[7:4]
[3:0]
RO
R/W
Reserved
FGC_1BP_Color[7:4]
Access:
Size:
Read/Write
8 bits
Description
Defines the Char1BP FG color [7:4]
2.6.5.14 OSD1 FontROM Index Base Register
Address Offset:
Default Value:
OSD1_0Dh
40h
Access:
Size:
Read/Write
8 bits
Bit
Access
Symbol
Description
[7:0]
R/W
FontROM_IndexBase
[8:1]
For font index value less than this value is mono character (Char1BP)
RAM font segment;
For font index >= this value but less than Char2BP_IndexBase is
mono character (Char1BP) ROM font segment.
2.6.5.15 OSD1 Revision ID Register
Address Offset:
Default Value:
OSD1_0Fh
31h
Bit
Access
Symbol
[7:0]
RO
Revision_ID[7:0]
Access:
Size:
Read Only
8 bits
Description
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2.6.5.16 OSD1 Menu-1 Enable Register
Address Offset:
Default Value:
OSD1_10h
00h
Bit
Access
Symbol
[7]
[6:0]
R/W
RO
M1_En
Reserved
Access:
Size:
Read/Write
8 bits
Description
Set to 1 enable Menu-1 thread to display
2.6.5.17 OSD1 Menu-1 Start Address LSB Register
Address Offset:
Default Value:
Bit
[7:0]
Access
R/W
OSD1_11h
00h
Access:
Size:
Read/Write
8 bits
Symbol
M1_Menu_SA[7:0]
Description
st
Point to the 1 row attribute of Menu-1 in OSD1 RAM.
2.6.5.18 OSD1 Menu-1 Start Address MSB Register
Address Offset:
Default Value:
OSD1_12h
10h
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
M1_Menu_SA[12:8]
Access:
Size:
Read/Write
8 bits
Description
Point to the 1st row attribute of Menu-1 in OSD1 RAM.
2.6.5.19 OSD1 Menu-1 End Address LSB Register
Address Offset:
Default Value:
OSD1_13h
00h
Bit
Access
Symbol
[7:0]
R/W
M1_Menu_EA[7:0]
Access:
Size:
Read/Write
8 bits
Description
Point to the end of Menu-1 in OSD1 RAM.
2.6.5.20 OSD1 Menu-1 End Address MSB Register
Address Offset:
Default Value:
OSD1_14h
14h
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
M1_Menu_EA[12:8]
Access:
Size:
Read/Write
8 bits
Description
Point to the end of Menu-1 in OSD1 RAM.
2.6.5.21 OSD1 FontROM Base Address LSB Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
OSD1_16h
00h
Access:
Size:
Read/Write
8 bits
Symbol
Description
st
Font_BaseA_ROM[7:0] Point to the start address in ROM, i.e., point to the 1 Font in ROM.
2.6.5.22 OSD1 FontROM Base Address MSB Register
Address Offset:
Default Value:
Bit
Access
[7:5]
[4:0]
RO
R/W
OSD1_17h
00h
Access:
Size:
Symbol
Read/Write
8 bits
Description
Reserved
st
Font_BaseA_ROM[12:8] Point to the start address in ROM, i.e., point to the 1 Font in ROM.
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2.6.5.23 OSD1 Menu-2 Enable Register
Address Offset:
Default Value:
OSD1_18h
00h
Bit
Access
Symbol
[7]
[6:0]
R/W
RO
M2_En
Reserved
Access:
Size:
Read/Write
8 bits
Description
Set to 1 enable Menu-2 thread to display
2.6.5.24 OSD1 Menu-2 Start Address LSB Register
Address Offset:
Default Value:
Bit
[7:0]
Access
R/W
OSD1_19h
00h
Access:
Size:
Read/Write
8 bits
Symbol
M2_Menu_SA[7:0]
Description
st
Point to the 1 row attribute of Menu-2 in OSD1 RAM.
2.6.5.25 OSD1 Menu-2 Start Address MSB Register
Address Offset:
Default Value:
OSD1_1Ah
15h
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
M2_Menu_SA[12:8]
Access:
Size:
Read/Write
8 bits
Description
Point to the 1st row attribute of Menu-2 in OSD1 RAM.
2.6.5.26 OSD1 Menu-2 End Address LSB Register
Address Offset:
Default Value:
OSD1_1Bh
00h
Bit
Access
Symbol
[7:0]
R/W
M2_Menu_EA[7:0]
Access:
Size:
Read/Write
8 bits
Description
Point to the end of Menu-2 in OSD1 RAM.
2.6.5.27 OSD1 Menu-2 End Address MSB Register
Address Offset:
Default Value:
OSD1_1Ch
16h
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
M2_Menu_EA[12:8]
Access:
Size:
Read/Write
8 bits
Description
Point to the end of Menu-2 in OSD1 RAM.
2.6.5.28 OSD1 BMP Control Register
Address Offset:
Default Value:
OSD1_20h
00h
Bit
Access
Symbol
[7]
[6:4]
R/W
R/W
BMP_En
BMP_Nbpp
[3:2]
[1:0]
R/W
R/W
Access:
Size:
Read/Write
8 bits
Description
Set to 1 enable BMP to display
Defines current BMP for displaying is N bits per pixel.
000b: Reserved
001b: 1 bit/pixel
010b: 2 bits/pixel
011b: 3 bits/pixel
100b: 4 bits/pixel
101b: 5 bits/pixel
11Xb: 5 bits/pixel
BMP_Extra_Height[1:0] BMP enlarge ratio in vertical direction: x1, x2, x3, x4 lines
BMP_Extra_Width[1:0] BMP enlarge ratio in horizontal direction: x1, x2, x3, x4 dots
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2.6.5.29 OSD1 BMP Start Address LSB Register
Address Offset:
Default Value:
OSD1_21h
00h
Bit
Access
Symbol
[7:0]
R/W
BMP_SA[7:0]
Access:
Size:
Read/Write
8 bits
Description
Point to the top-left dot of BMP for displaying in OSD1 RAM.
2.6.5.30 OSD1 BMP Start Address MSB Register
Address Offset:
Default Value:
OSD1_22h
0Bh
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
BMP_SA[12:8]
Access:
Size:
Read/Write
8 bits
Description
Point to the top-left dot of BMP for displaying in OSD1 RAM.
2.6.5.31 OSD1 BMP Alpha-Blending Control Register
Address Offset:
Default Value:
Bit
Access
[7:6]
[5:4]
RO
R/W
[3:0]
R/W
OSD1_23h
1Ah
Access:
Size:
Read/Write
8 bits
Symbol
Description
Reserved
BMP_FG_aB_Mode[1:0] Defines BMP alpha-blending for foreground when BG already alphaBlended:
00b: All FG need alpha-Blended if BG is alpha-Blended;
01b: All FG no need alpha-Blended;
10b: All FG no need alpha-Blended, except their color is LUT[1];
11b: All FG no need alpha-Blended, except their color is LUT[1..3];
BMP_aB_SourcePercent[ Defines the percentage of source image/video for mixed with OSD1
3:0]
BMP.
2.6.5.32 OSD1 BMP Horizontal Size LSB Register
Address Offset:
Default Value:
OSD1_24h
10h
Bit
Access
Symbol
[7:0]
R/W
BMP_HSize[7:0]
Access:
Size:
Read/Write
8 bits
Description
Defines the horizontal size of BMP for displaying in OSD1 RAM. Unit
is how manys word (16-bits) count (before enlarged).
2.6.5.33 OSD1 BMP Horizontal Size MSB Register
Address Offset:
Default Value:
OSD1_25h
00h
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
BMP_HSize[10:8]
Access:
Size:
Read/Write
8 bits
Description
Defines the horizontal size of BMP for displaying in OSD1 RAM.
2.6.5.34 OSD1 BMP Vertical Size LSB Register
Address Offset:
Default Value:
OSD1_26h
60h
Bit
Access
Symbol
[7:0]
R/W
BMP_HSize[7:0]
Access:
Size:
Read/Write
8 bits
Description
Defines the vertical size of BMP for displaying in OSD1 RAM. Unit is
how many lines count (before enlarged).
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2.6.5.35 OSD1 BMP Vertical Size MSB Register
Address Offset:
Default Value:
OSD1_27h
00h
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
BMP_HSize[10:8]
Access:
Size:
Read/Write
8 bits
Description
Defines the vertical size of BMP for displaying in OSD1 RAM.
2.6.5.36 OSD1 BMP Horizontal Start Position LSB Register
Address Offset:
Default Value:
OSD1_28h
00h
Bit
Access
Symbol
[7:0]
R/W
BMP_HStart[7:0]
Access:
Size:
Read/Write
8 bits
Description
Defines the left boundary position of BMP for displaying, count in
display clocks.
2.6.5.37 OSD1 BMP Horizontal Start Position MSB Register
Address Offset:
Default Value:
OSD1_29h
03h
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
BMP_HStart[10:8]
Access:
Size:
Read/Write
8 bits
Description
Defines the left boundary position of BMP for displaying.
2.6.5.38 OSD1 BMP Vertical Start Position LSB Register
Address Offset:
Default Value:
OSD1_2Ah
80h
Bit
Access
Symbol
[7:0]
R/W
BMP_VStart[7:0]
Access:
Size:
Read/Write
8 bits
Description
Defines the top boundary position of BMP for displaying, count in
lines.
2.6.5.39 OSD1 BMP Vertical Start Position MSB Register
Address Offset:
Default Value:
OSD1_2Bh
02h
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
BMP_VStart[10:8]
Access:
Size:
Read/Write
8 bits
Description
Defines the top boundary position of BMP for displaying.
2.6.5.40 OSD1 BMP LUT Base Address Register
Address Offset:
Default Value:
Bit
Access
[7:1]
R/W
[0]
RO
OSD1_2Ch
10h
Access:
Size:
Read/Write
8 bits
Symbol
Description
BMP_LUT_BaseA[7:1] Defines the LUT offset. For N-BPP BMP, its LUT segment starts with
{BMP_LUT_BaseA[7:N], N’b0};
Reserved
2.6.5.41 OSD1 BMP Background Color Register
Address Offset:
Default Value:
OSD1_2Dh
00h
Bit
Access
Symbol
[7:0]
R/W
BMP_BG_Color[7:0]
Access:
Size:
Read/Write
8 bits
Description
Defines the address of one LUT as BMP background color.
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2.6.5.42 OSD1 Block Write Data LSB Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
OSD1_40h
00h
Access:
Size:
Read/Write
8 bits
Symbol
Description
OSD1_BlockWr_D[7:0] LSB Data to be block fill
2.6.5.43 OSD1 Block Write Data MSB Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
OSD1_41h
00h
Access:
Size:
Read/Write
8 bits
Symbol
Description
OSD1_BlockWr_D[15:8] MSB Data to be block fill
2.6.5.44 OSD1 Block Write Starting Address LSB Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
OSD1_42h
00h
Access:
Size:
Read/Write
8 bits
Symbol
Description
OSD1_BlockWr_SA[7:0] Starting Address of block fill
2.6.5.45 OSD1 Block Write Starting Address MSB Register
Address Offset:
Default Value:
Bit
Access
[7:5]
[4:0]
RO
R/W
OSD1_43h
00h
Access:
Size:
Read/Write
8 bits
Symbol
Description
Reserved
OSD1_BlockWr_SA[12:8] Starting Address of block fill
2.6.5.46 OSD1 Block Write Length Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
OSD1_44h
10h
Access:
Size:
Read/Write
8 bits
Symbol
Description
OSD1_BlockWr_L[7:0] Block fill length (count)
2.6.5.47 OSD1 Block Write Control Register
Address Offset:
Default Value:
Bit
Access
[7]
WO/
RO
R/W
RO
R/W
[6]
[5]
[4:0]
OSD1_45h
00h
Access:
Size:
Symbol
Read/Write
8 bits
Description
OSD1_BlockWr_Trig Set to 1 to trigger block fill operation
OSD1_BlockWr_Done Get 1 means the block fill operation is done
OSD1_BlockWr_mode
Reserved
OSD1_BlockWr_L[12:8] Block fill length (count)
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2.7 Pattern Fill
2.7.1
Pattern Fill Register Map
I/O Port
Groups
Index
00h
A8h – OSD1_Index
A9h – OSD1_Data
Pattern
Fill
Description
OSD1 Pattern Fill Enable/Blinking Register
08h
OSD1 Pattern Fill Color LUT Address port
09h
OSD1 Pattern Fill Color LUT Data Port
30h
Pattern Fill Control Register
31h
Pattern Fill LUT Base Address
32h
Pattern Fill Horizontal Size
33h
Pattern Fill Vertical Size
34h
Pattern Fill Row Shift
35h
Pattern Fill Alpha Blending Control
36h
OSD1 BIST Result and Pattern Fill Enlarge
37h
Pattern Fill RAM Write Data Port
38h
Pattern Fill Horizontal Start, LSB
39h
Pattern Fill Horizontal Start, MSB
3Ah
Pattern Fill Vertical Start, LSB
3Bh
Pattern Fill Vertical Start, MSB
3Ch
Pattern Fill Horizontal End, LSB
3Dh
Pattern Fill Horizontal End, MSB
3Eh
Pattern Fill Vertical End, LSB
3Fh
Pattern Fill Vertical End, MSB
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OSD1 Pattern Fill Color Scheme
Pattern Fill can be implemented by Bitmap. The color mapping of Bitmap is more complicate, please refer to the
following drawing. The OSD1 Pattern Fill main Color LUT is 256 entries SRAM, color in RGB565 format.
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OSD1 Pattern Fill Configuration Registers
2.7.3.1 OSD1 Pattern_Fill Enable/Blinking Register
Address Offset:
Default Value:
Bit
Access
[7]
[6]
[5:4]
R/W
R/W
R/W
[3:0]
R/W
OSD1PF_00h
0Ah
Access:
Size:
Read/Write
8 bits
Symbol
Description
OSD1PF_En
Set to 1 for globally enabling OSD1 Pattern Fill function.
Reserved
CRAM_ByteAccess[1:0] Byte Access mode when programming character of menu:
0Xb: Word access (LSB first, then MSB byte)
10b: LSB only (not affect font index >= 256)
11b: MSB only (character BG/FG colors, Blinking, and Index bit 8)
Reserved
2.7.3.2 OSD1 Pattern_Fill LUT Address Register
Address Offset:
Default Value:
OSD1PF_08h
00h
Access:
Size:
Write Only
8 bits
Bit
Access
Symbol
Description
[7:0]
WO
LUT_A[8:1]
Assign access pointer of Color LUT. When assigning, LUT_A[0]
always = 0. LUT[0..255] are main color LUT (16-bits); LUT[256..271]
are Char2BP remap LUT (24-bits); LUT[272..273]are BMP remap LUT
(24-bits).
2.7.3.3 OSD1 Pattern_Fill LUT Data Port Register
Address Offset:
Default Value:
OSD1 PF _09h
00h
Bit
Access
Symbol
[7:0]
WO
LUT_D[7:0]
Access:
Size:
Write Only
8 bits
Description
Data written to this port will overwrite OSD2 LUT.
2.7.3.4 OSD1 Pattern_Fill Control Register
Address Offset:
Default Value:
OSD1 PF _30h
48h
Bit
Access
Symbol
[7]
[6:4]
R/W
R/W
Patt_En
Patt_ColorDepth[2:0]
[3:2]
R/W
[1]
R/W
[0]
WO
Access:
Size:
Read/Write
8 bits
Description
Set to 1 enable Pattern_Fill to display
Defines nBP color:
000b: 8BPP
001b: 1BPP
010b: 2BPP
011b: 3BPP
100b: 4BPP
101b: 5BPP
110b: 6BPP
111b: 7BPP
Patt_RAM_Bit[1:0]
Defines the usage in Pattern RAM:
00b: 1 bit/pixel
01b: 2 bits/pixel
10b: 4 bits/pixel
11b: 8 bits/pixel
Patt_Independ_AB
Set to 1 for independent Alpha-Blending setting for Pattern_Fill;
set to 0 for by OSD1_0B
Reset_PRAM_Pointer Write 1 to reset the Pattern RAM pointer for loading pattern data
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2.7.3.5 OSD1 Pattern_Fill LUT Base Address Register
Address Offset:
Default Value:
OSD1 PF _31h
80h
Bit
Access
Symbol
[7:7]
R/W
Patt_LUT_BaseA[7:0]
Access:
Size:
Read/Write
8 bits
Description
Defines the MSB color in LUT for PatternFill color. Bit 0 is not used.
2.7.3.6 OSD1 Pattern_Fill Pattern Horizontal Size Register
Address Offset:
Default Value:
OSD1 PF _32h
10h
Bit
Access
Symbol
[7:0]
R/W
Patt_HSize[7:0]
Access:
Size:
Read/Write
8 bits
Description
For repeated pattern, this defines its width in the unit: Byte.
2.7.3.7 OSD1 Pattern_Fill Pattern Vertical Size Register
Address Offset:
Default Value:
OSD1 PF _33h
10h
Bit
Access
Symbol
[7:0]
R/W
Patt_VSize[7:0]
Access:
Size:
Read/Write
8 bits
Description
For repeated pattern, this defines its height in the unit: line.
2.7.3.8 OSD1 Pattern_Fill Pattern Row Shift Register
Address Offset:
Default Value:
OSD1 PF _34h
00h
Bit
Access
Symbol
[7:0]
R/W
Patt_Row_Shift[7:0]
Access:
Size:
Read/Write
8 bits
Description
For repeated pattern, this defines horizontal shift in the unit: Byte, to
build a delta-type pattern.
2.7.3.9 OSD1 Pattern_Fill Color High Bits Register
Address Offset:
Default Value:
OSD1 PF _35h
05h
Bit
Access
Symbol
[7:4]
[3:0]
RO
R/W
Reserved
Patt_aB_
SourcePencent[3:0]
Access:
Size:
Read/Write
8 bits
Description
Alpha Blending percentage (n/16) for Filled patterns only.
If set 0000b, alpha blending is disabled (0/16 * Original Video Source
+ 8/8 * PatternFill display);
If set 0001b, blending as 1/16 * Original Video Source + 15/16 *
PatternFill display;
...
If set N, blending as N/16 * Original Video Source + (16-N)/16 *
PatternFill display;
2.7.3.10 OSD1 BIST Result and Pattern Enlarge Register
Address Offset:
Default Value:
OSD1 PF _36h
00h
Bit
Access
Symbol
[7]
[6]
RO
RO
Reserved
OSD1_PRAM_Fail
[5:4]
[3:2]
[1:0]
RO
R/W
R/W
Reserved
Patt_V_Enlarge[1:0]
Patt_H_Enlarge[1:0]
Access:
Size:
Read/Write
8 bits
Description
After OSD BIST done, get 1 in this bit shows the OSD1 PatternFill
RAM is failed.
For each repeated pattern, enlarge it in verical direction
For each repeated pattern, enlarge it in horizontal direction
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2.7.3.11 OSD1 Pattern_Fill Pattern RAM Write Port Register
Address Offset:
Default Value:
Bit
Access
[7:0]
WO
OSD1 PF _37h
00h
Access:
Size:
Read/Write
8 bits
Symbol
Description
PRAM_WrD_Port[10:8] For building pattern, need to load via writing pattern to PRAM (Pattern
RAM). After reset PRAM pointer, the PRAM pointer will increase after
each burst write.
2.7.3.12 OSD1 Pattern_Fill Position, Horizontal Start LSB Register
Address Offset:
Default Value:
OSD1 PF _38h
00h
Bit
Access
Symbol
[7:0]
R/W
Patt_HStart[7:0]
Access:
Size:
Read/Write
8 bits
Description
Allowable pattern display region: horizontal start
2.7.3.13 OSD1 Pattern_Fill Position, Horizontal Start MSB Register
Address Offset:
Default Value:
OSD1 PF _39h
00h
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
Patt_HStart[10:8]
Access:
Size:
Read/Write
8 bits
Description
Allowable pattern display region: horizontal start
2.7.3.14 OSD1 Pattern_Fill Position, Vertical Start LSB Register
Address Offset:
Default Value:
OSD1 PF _3Ah
00h
Bit
Access
Symbol
[7:0]
R/W
Patt_VStart[7:0]
Access:
Size:
Read/Write
8 bits
Description
Allowable pattern display region: vertical start
2.7.3.15 OSD1 Pattern_Fill Position, Vertical Start MSB Register
Address Offset:
Default Value:
OSD1 PF _3Bh
00h
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
Patt_VStart[10:8]
Access:
Size:
Read/Write
8 bits
Description
Allowable pattern display region: vertical start
2.7.3.16 OSD1 Pattern_Fill Position, Horizontal End LSB Register
Address Offset:
Default Value:
OSD1 PF _3Ch
00h
Bit
Access
Symbol
[7:0]
R/W
Patt_HEnd[7:0]
Access:
Size:
Read/Write
8 bits
Description
Allowable pattern display region: horizontal End
2.7.3.17 OSD1 Pattern_Fill Position, Horizontal End MSB Register
Address Offset:
Default Value:
OSD1 PF _3Dh
01h
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
Patt_HEnd[10:8]
Access:
Size:
Read/Write
8 bits
Description
Allowable pattern display region: horizontal End
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2.7.3.18 OSD1 Pattern_Fill Position, Vertical End LSB Register
Address Offset:
Default Value:
OSD1 PF _3Eh
80h
Bit
Access
Symbol
[7:0]
R/W
Patt_VEnd[7:0]
Access:
Size:
Read/Write
8 bits
Description
Allowable pattern display region: vertical End
2.7.3.19 OSD1 Pattern_Fill Position, Vertical End MSB Register
Address Offset:
Default Value:
OSD1 PF _3Fh
00h
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
Patt_VEnd[10:8]
Access:
Size:
Read/Write
8 bits
Description
Allowable pattern display region: vertical End
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3 Register Description
Serial Bus Register Set Page 0
3.1 ADC Register Set
3.1.1
Mid-level Clamp Voltage Register
Address Offset:
Default Value:
3.1.2
Bit
Access
[7:6]
[5:4]
[3:2]
[1:0]
RO
R/W
R/W
R/W
Description
Reserved
B_Clamp_Volt_Sel[1:0] Blue channel Clamp voltage select
G_Clamp_Volt_Sel[1:0] Green channel Clamp voltage select
R_Clamp_Volt_Sel[1:0] Red channel Clamp voltage select
07h
FFh
Access:
Size:
Access
Symbol
[7:0]
R/W
ADCRSG
Read/Write
8 bits
Description
This register can set a fixed gain for ADC channel 0 when static gain
control is enabled
ADC Channel 1 Static Gain
08h
FFh
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
ADCGSG
Read/Write
8 bits
Description
This register can set a fixed gain for ADC channel 1 when static gain
control is enabled
ADC Channel 2 Static Gain
Address Offset:
Default Value:
3.1.5
Read/Write
8 bits
Symbol
Bit
Address Offset:
Default Value:
3.1.4
Access:
Size:
ADC Channel 0 Static Gain
Address Offset:
Default Value:
3.1.3
05h
00h
09h
FFh
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
ADCBSG
Read/Write
8 bits
Description
This register can set a fixed gain for ADC channel 2 when static gain
control is enabled
ADC Channel 0 Offset
Address Offset:
Default Value:
0Ah
60h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
R/W
RO
ADC_ROFF
Reserved
Read/Write
8 bits
Description
ADC Channel 0 DC Offset Control
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ADC Channel 1 Offset
Address Offset:
Default Value:
3.1.7
0Bh
60h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
R/W
RO
ADC_GOFF
Reserved
Read/Write
8 bits
Description
ADC Channel 1 DC Offset Control
ADC Channel 2 Offset
Address Offset:
Default Value:
3.1.8
Copyright by Terawins, Inc.
0Ch
60h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
R/W
RO
ADC_BOFF
Reserved
Read/Write
8 bits
Description
ADC Channel 2 DC Offset Control
ADC General Control Configuration Register
Address Offset:
Default Value:
0Dh
20h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
RO
R/W
Reserved
CLPMD
Read/Write
8 bits
Description
Clamping mode
Mode
0
1
[5]
[4]
[3]
[2]
[1]
[0]
R/W
R/W
R/W
RO
R/W
R/W
DCEN
DCSEL
Reserved
DC_CAL_RDY
DC_CALEN
DC_CALMD
Type
Fixed window
Locked Window
DC Clamping Enable
Clamping Source Selection
Test only, vmode
DC Calibration Ready
DC Calibration Enable
DC Calibration Mode
Mode
0
1
3.1.9
Type
minimum
average
ADC Gain ReadBack
Address Offset:
Default Value:
0Eh
-
Access:
Size:
Bit
Access
Symbol
[7:0]
R
adc_auto_gain
Read Only
6 bits
Description
ADC automatic gain control read back.
3.1.10 ADC Power Down Control
Address Offset:
Default Value:
0Fh
00h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
R/W
R/W
PwDn_SOY
PD2 (B)
[5]
R/W
PD1 (G)
Read/Write
8 bits
Description
1 for Power down SOY slicer
1: Power down
0: Power up
1: Power down
0: Power up
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[4]
R/W
PD0 (R)
[3:1]
[0]
R/W
RO
Reserved
Reserved
3.1.11
ADC Polarity Control
Address Offset:
Default Value:
3.1.12
Bit
Access
[7]
RO/WO
[6]
RO/WO
[5]
[4]
[3]
[2]
[1]
[0]
R/W
R/W
R/W
R/W
R/W
R/W
10h
E8h
Access:
Size:
Read/Write
8 bits
Symbol
Description
HSi_Polarity / HSi_Inv_ When Read: get input HSync polarity
When writing, to invert (0) or non-invert (1) input HSync
VSi_Polarity / VSi_Inv_ When Read: get input VSync polarity
When writing, to invert (0) or non-invert (1) input VSync
SOY_Inv_
For invert (0) or non-invert (1) input SOY
Auto_Polarity
Set to 1 for enabling auto-adjusting HSync/VSync polarity.
Clamp_Polarity
Set to 1 for controlling Clamp positive polarity.
Clamp_Sel_GfbHS
Set to 1 to use PLL feedback HSync as clamp reference
Clamp_Leading
Set to 1 to use leading edge of HSync as clamp reference point.
Clamp_Sel_RGB
Clamp control by: 1: RGB/SOY logic, 0: VD logic.
YPbPr Clamping Control Register
Address Offset:
Default Value:
11h
98h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4:3]
[2]
R/W
R/W
R/W
SOY_Threshold
SOY_Discharge
BSCALE
[1]
R/W
GSCALE
[0]
R/W
RSCALE
3.1.13
1: Power down
0: Power up
Read/Write
8 bits
Description
Voltage threshold for SOY slicing
SOY Discharge option
ADC Channel 2 Clamping Mode
0: Clamp to Ground; 1: Clamp to mid-scale
ADC Channel 1 Clamping Mode
0: Clamp to Ground; 1: Clamp to mid-scale
ADC Channel 0 Clamping Mode
0: Clamp to Ground; 1: Clamp to mid-scale
SOY Slice Control
Address Offset:
Default Value:
12h
06h
Access:
Size:
Bit
Access
[7]
RO/WO Done_ / En_Slicer_Status When read: get flag of Slicer status ready or not
When write, to enable monitoring Slicer status
RO
Slicer_Status
0:Slicer always low, 1: always high, 2: almost low, 3: almost high
R/W
Reserved
R/W
SOY_ClampPlacement SOY Clamp Placement
R/W
SOY_ClampDuration SOY Clamp Duration.
[6:5]
[4]
[3:2]
[1:0]
Symbol
Read/Write
8 bits
Description
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3.1.14
Copyright by Terawins, Inc.
VSync Separation Register
Address Offset:
Default Value:
13h
08h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
[5]
[4]
[3]
[2]
[1:0]
RO
RO
R/W
R/W
R/W
R/W
R/W
CSync_Detect_Done
Fs_TooFast
En_CSync_Detect
Reserved
Reserved
Reserved
Div_To14[1:0]
Read/Write
8 bits
Description
flag of whether CSync Detection is done or not
Get 1 if CSync Detecting operation clock is too fast
Set to 1 for enabling CSync Detection function
Reserved for chip testing, should set 0 for normal operation
Reserved for special case, set to 1 for normal conditions
Reserved for special case, set to 0 for normal conditions
00b: power down or reset, 01b: XCLK/1,
10b:XCLK/2 (normal operation for XCLK=27MHz); 11b: XCLK/3
3.1.15 Sync Routine Control
Address Offset:
Default Value:
14h
D1h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
HS2PLL_Polarity
Coast2PLL_Polarity
ADC_is_RGB
HSo_Sel_Fdbk
HRef_Sel_SOY
VS_Sel_Sep
Coast_Sel_Sep
Reserved
Read/Write
8 bits
Description
HRef polarity
Coast polarity
ADC Color space select: Set 1 for RGB input, 0 for YPbPr input.
ADC HSo source from PLL when set to 1
PLL HRef from: 1: SOY Slicer (SOY); 0: HS input pin (SS/CS)
ADC VSo from: 1: VSync Detect (SOY/CS); 0: VS input pin (SS)
PLL Coast from: 1: VSync Detect (SOY/CS); 0: Ground (SS)
3.1.16 Line Lock PLL Divider Register 1
Address Offset:
Default Value:
15h
5Ah
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
APLL_Div[7:0]
Read/Write
8 bits
Description
PLL divider LSB
3.1.17 Line Lock PLL Divider Register 2
Address Offset:
Default Value:
16h
C3h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
[5]
[4]
[3:0]
R/W
R/W
R/W
RO
R/W
APLL_PowerDown
APLL_Sel_HighFreq
APLL_Reset
ADC_Clock_From
APLL_Div[11:8]
Read/Write
8 bits
Description
1: power down, 0: enable
Reserved for testing, 1: high freq., 0: low freq.
1: Reset Line-lock PLL 0: normal operation for RGB and SOY inputs
ADC clock source: 1: XCLK; 0:APLL output
PLL divider MSB
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3.1.18 VCO & Charge Pump Register
Address Offset:
Default Value:
17h
48h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5:3]
[2]
[1]
[0]
R/W
R/W
R/W
R/W
R/W
ADC_VCO
ADC_ChargePump
AutoClampV_B
AutoClampV_G
AutoClampV_R
Read/Write
8 bits
Description
Reserved for testing
Reserved for testing
Reserved for testing
3.1.19 Analog Source MUX Selection
Address Offset:
Default Value:
18h
00h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5:4]
RO
R/W
Reserved
AI2SEL (B)
[3:2]
R/W
AI1SEL (G)
[1:0]
R/W
AI0SEL (R)
3.1.20
Read/Write
8 bits
Description
Analog mux selection for ADC channel 2
00: ACB1
01: ACB0
1x: ACB2
Analog mux selection for ADC channel 1
00: AY1
01: AY0
1x: AY2
Analog mux selection for ADC channel 0
00: ACR1
01: ACR0
1x: ACR2
Y/Cb/Cr Data Switching Control
Address Offset:
Default Value:
19h
07h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5:4]
RO
R/W
Reserved
CBINSEL
[3:2]
R/W
YINSEL
[1:0]
R/W
CRINSEL
Read/Write
8 bits
Description
The digitaized CB or B data can be taken from one of 3 ADCs:
00: ADC Ch0
01: ADC Ch1
1X: ADC Ch2
The digitaized Y or Composite or G data can be taken from one of 3
ADCs:
00: ADC Ch0
01: ADC Ch1
1X: ADC Ch2
The digitaized CR or Chroma or R data can be taken from one of 3
ADCs:
00: ADC Ch0
01: ADC Ch1
1X: ADC Ch2
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3.1.21 ADC Analog AGC Selection
Address Offset:
Default Value:
1Ah
87h
Access:
Size:
Bit
Access
Symbol
[7:6]
R/W
AGC_GAINMD
[5:3]
[2]
RO
R/W
Reserved
CB_AGC_SEL
[1]
R/W
Y_AGC_SEL
[0]
R/W
CR_AGC_SEL
Read/Write
8 bits
Description
Mode
0
1
2
3
Type
Positive gain
Positive gain 1x~2x
Negative gain 1x~2x
Negative gain
If 0, refer to ADCBSG (P0_09h):
0: Static gain; 1: Dynamic gain
If 0, refer to ADCGSG (P0_08h)
0: Static gain; 1: Dynamic gain
If 0, refer to ADCRSG (P0_07h)
0: Static gain; 1: Dynamic gain
3.1.22 Blank Sync Level
Address Offset:
Default Value:
1Ch
F0h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
BLANK_SL
Read/Write
8 bits
Description
3.1.23 ADC Phase Setting Register
Address Offset:
Default Value:
20h
80h
Access:
Size:
Bit
Access
Symbol
[7:3]
[2]
[1]
[0]
R/W
R/W
R/W
R/W
ADC_Phase[4:0]
ADC_Clk_Div2
ADC_Clk_Dly
ADC_Clk_Inv
Read/Write
8 bits
Description
32 phases per clock
Clock divided by 2 if set to 1
Clock delay if set to 1
Clock inverted if set to 1
3.1.24 ADC Detection Register
Address Offset:
Default Value:
21h
00h
Access:
Size:
Bit
Access
Symbol
[7]
RO/WO
[6:5]
R/W
Done_ATK /
En_ATK
ATK_Channel[1:0]
[4:3]
[2]
RO
RO/WO
[1]
[0]
RO
RO
Reserved
Done_Exist_ADC /
En_Exist_ADC
Exist_HSync
Exist_VSync
Read/Write
8 bits
Description
When read: get flag of Phases Tracking finish or not
When write, to enable Phases Tracking
Select which channel to perform ATK:
00: R+G+B
01: R
10: G
11: B
When read: get flag of Checking ADC HS/VS finish or not
When write, to enable Checking ADC HS/VS
HSync input toggle when read 1
HSync input toggle when read 1
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3.1.25 ADC Phase Tracking Register 1
Address Offset:
Default Value:
22h
XXh
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
ATK_Accu[7:0]
Read Only
8 bits
Description
Accumulated Phase Tracking Result
3.1.26 ADC Phase Tracking Register 2
Address Offset:
Default Value:
23h
XXh
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
ATK_Accu[15:8]
Read Only
8 bits
Description
Accumulated Phase Tracking Result
3.1.27 ADC Phase Tracking Register 3
Address Offset:
Default Value:
24h
XXh
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
ATK_Accu[23:16]
3.1.28
Description
Accumulated Phase Tracking Result
Boundary Control Register
Address Offset:
Default Value:
26h
04h
Access:
Size:
Bit
Access
Symbol
[7]
RO/WO
[6]
R/W
Done_Boundary /
En_Boundary
Boundary_hDE
[5:3]
[2:0]
R/W
R/W
3.1.29
Read Only
8 bits
Read/Write
8 bits
Description
When read: get flag of Boundary Detection finish or not
When write, to enable Boundary Detection
Check boundary when:
0: in all range
1: in HDE window
Boundary_Mask_HS_L Set the do not care range near HSync leading edge
Boundary_Mask_HS_T Set the do not care range near HSync trailing edge
Boundary Control Register
Address Offset:
Default Value:
27h
40h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
Boundary_Threshold
Read/Write
8 bits
Description
Set the color threshold for boundary detection
3.1.30 Boundary Left LSB Register
Address Offset:
Default Value:
28h
XXh
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
Left_Bound[7:0]
Read Only
8 bits
Description
Left Boundary Position
3.1.31 Boundary Left MSB Register
Address Offset:
Default Value:
29h
XXh
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
RO
Reserved
Left_Bound[10:8]
Read Only
8 bits
Description
Left Boundary Position
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3.1.32 Boundary Right LSB Register
Address Offset:
Default Value:
2Ah
XXh
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
Right_Bound[7:0]
Read Only
8 bits
Description
Right Boundary Position
3.1.33 Boundary Right MSB Register
Address Offset:
Default Value:
2Bh
XXh
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
RO
Reserved
Right_Bound[10:8]
Read Only
8 bits
Description
Right Boundary Position
3.1.34 Boundary Top LSB Register
Address Offset:
Default Value:
2Ch
XXh
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
Top_Bound[7:0]
Read Only
8 bits
Description
Top Boundary Position
3.1.35 Boundary Top MSB Register
Address Offset:
Default Value:
2Dh
XXh
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
RO
Reserved
Top_Bound[9:8]
Read Only
8 bits
Description
Top Boundary Position
3.1.36 Boundary Bottom LSB Register
Address Offset:
Default Value:
2Eh
XXh
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
Bottom_Bound[7:0]
Read Only
8 bits
Description
Bottom Boundary Position
3.1.37 Boundary Bottom MSB Register
Address Offset:
Default Value:
2Fh
XXh
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
RO
Reserved
Bottom_Bound[9:8]
Read Only
8 bits
Description
Bottom Boundary Position
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3.2 Input Timing Register Set
3.2.1
De-Interlaced Process & Vertical Shadow Control Register
Address Offset:
Default Value:
3.2.2
30h
82h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5]
RO
R/W
Reserved
VST_CHGSEL
[4]
R/W
INT_EDGE
[3]
R/W
LB_SIZE_FIXED
[2]
[1]
R/W
R/W
ENQKHS
ITLCPRO
[0]
R/W
ADC_Odd_in_HsVs
Read/Write
8 bits
Description
1:Vsync timing change determined by 8*# of XCLK
0:Vsync timing change determined by # of hsync (default)
# can be assigned at Reg 0x3A
Interrupt polarity
1: positive
0: negative (default)
This bit control capture size for Scaler.
1: Hsize and Vsize are assigned by 54h ~57h
0: sizes assigned by input sources. (default)
Reserved for chip teset only, set to 0 for normal operation
Set 1 for interlaced video (default)
Set 0 for non-interlaced video
Set to 1 for enabling detecting Odd flag from HS/VS pins
Source Select Register
Address Offset:
Default Value:
31h
04h
Access:
Size:
Bit
Access
Symbol
[7]
[6:4]
RO
R/W
ITLCFLM
VIP_Sel[2:0]
[3:2]
R/W
InSource_Sel[1:0]
[1]
[0]
RO
RO
Reserved
VBI_Field
Read/Write
8 bits
Description
Indicates incoming video signal is interlaced if get 1
Select the digital input source (VIP: Video Input):
000: A656
001: B656
010: L601_8bits
011: L601_16bits
100: Reserved
101: RGB565
110: RGB666
111: RGB888
Select the input source:
00: Digital VIP input
01: select VD input (CVBS, S-Video, YPbPr)
10: Select ADC RGB, SOY(YPbPr)
11: Reserved
Current VBI field information
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3.2.3
Interrupt Status Register
Address Offset:
Default Value:
3.2.4
Access:
Size:
Access
Symbol
[7:0]
RO/W1C
INTSTS
Read-only / Write-1-to-clear
8 bits
Description
Read to get interrupt trigger source, Write 1 to clear it.
[7]: IR packet received
[6]: VBI packet is valid for processing
[5]: Every VSync Leading Edge
[4]: Timer time out
[3]: HSync Timing Changed
[2]: VSync Timing Changed
[1]: Lost HSync
[0]: Lost VSync
Interrupt Mask Register
33h
FFh
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
INTMASK
Read/Write
8 bits
Description
Set to 1 for masking relative interrupt trigger source:
[7]: IR packet received
[6]: VBI packet is valid for processing
[5]: Every VSync Leading Edge
[4]: Timer time out
[3]: HSync Timing Changed
[2]: VSync Timing Changed
[1]: Lost HSync
[0]: Lost VSync
Interrupt Status/Mask 2 Register
Address Offset:
Default Value:
3.2.6
32h
00h
Bit
Address Offset:
Default Value:
3.2.5
Copyright by Terawins, Inc.
34h
10h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4]
R/W
R/W
Reserved
INTMASK_2
[3:1]
[0]
RO/W1C
RO/W1C
Reserved
INTSTS_2
Read/Write
8 bits
Description
Set to 1 for masking relative interrupt trigger source:
[4]: SAR1_Toggling
Read to get interrupt trigger source, Write 1 to clear it.
[0]: SAR1_Toggling
VD/656 Left Border Crop Register
Address Offset:
Default Value:
3Ch
00h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5:0]
RO
R/W
Reserved
CROP_LEFTB
Read/Write
8 bits
Description
Remove noisy pixels appearing on left border.
1LSB =1 pixel
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3.2.7
VD/656 VSync Offset Register
Address Offset:
Default Value:
3.2.8
3Dh
00h
Access:
Size:
Bit
Access
Symbol
[7]
R/W
VD_VsOfs_Mode
[6]
[5:0]
RO
R/W
Reserved
VD_VsOffset
Read/Write
8 bits
Description
VD/656 VSync Offset mode:
0: Crop Top Border
1: VSync Offset, delay lines
Remove noisy pixels appearing on top border or re-shape VSync
1LSB =1 line, value 0 means disable.
VD/656 Left Border Crop Register
Address Offset:
Default Value:
3.2.9
Copyright by Terawins, Inc.
3Eh
10h
Access:
Size:
Read/Write
8 bits
Bit
Access
Symbol
Description
[7]
[6]
R/W
R/W
En_VD_VsOfs_P1
VD_VsOfs_on_Odd
[5:0]
R/W
VD_VsBP
Enable VSync Offset add 1 line for even or odd field on VD path
Set to 1 for selecting VD VSync Offset delay 1 line on Odd field; Set to
0 for Even field. This bit works only when En_VD_VsOfs_P1=1.
VD/656 VSync Back Proch (# lines)
Input Sync Signal Detection Register
Address Offset:
Default Value:
3Fh
00h
Access:
Size:
Bit
Access
Symbol
[7]
R/W
HSTLSPVS
[6]
R/W
AUTOVSD6
Read/Write
8 bits
Description
1:use trailing edge of hsync to sample
0:use leading edge of hsync to sample
When the edges of vsync and hsync are too close, input detection
circuit can delay vsync 6 cycle of XCLK to avoid unstable detection
1:Automatically delay 6 cycles of XCLK if CFSEEDGE is true.
0:Dealy 6 cycles of XCLK if FCVSD6 is true
[5]
[4]
[3]
[2]
[1:0]
R/W
RO
RO
RO
RO
Reserved
CFSEEDGE
HS_Polarity
VS_Polarity
Reserved
VS and HS edges are too close.
Detected HSync polarity (for Analog RGB raw input)
Detected VSync polarity (for Analog RGB raw input)
3.2.10 ADC Sync Offset Control Register
Address Offset:
Default Value:
40h
D0h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
[5]
[4]
[3:2]
[1]
[0]
R/W
R/W
R/W
R/W
RO
R/W
R/W
En_HsOffset
En_VsOffset
En_VsOfs_Evn_P1
SOY_Odd_Inv_
Reserved
RGB_PowerDown_
HS_in_SyncSel
Read/Write
8 bits
Description
Set to 1 for enabling ADC HSync Offset.
Set to 1 for enabling ADC VSync Offset.
Set to 1 for enabling ADC VSync Offset delay 1 line for even field.
Set to 0 for inverting SOY Odd field flag.
Set to 0 for power down RGB related logic. 1 for enabling RGB path.
Select the sampling edge of HSync pin.
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3.2.11 ADC HSync Offset LSB Register
Address Offset:
Default Value:
41h
02h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HsOffset[7:0]
Read/Write
8 bits
Description
Delay ADC HSync by # dots.
3.2.12 ADC HSync Offset MSB Register
Address Offset:
Default Value:
42h
00h
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
HsOffset[10:8]
Read/Write
8 bits
Description
Delay ADC HSync by # dots.
3.2.13 ADC VSync Offset LSB Register
Address Offset:
Default Value:
43h
01h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
VsOffset[7:0]
Read/Write
8 bits
Description
Delay ADC VSync by # lines.
3.2.14 ADC VSync Offset MSB Register
Address Offset:
Default Value:
44h
00h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
R/W
Reserved
VsOffset[9:8]
Read/Write
8 bits
Description
Delay ADC VSync by # lines.
3.2.15 ADC HSync Offset Pulse Width Register
Address Offset:
Default Value:
45h
10h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HsPulseWidth[7:0]
Read/Write
8 bits
Description
Pulse width of the regenerated ADC HSync (# dots).
3.2.16 ADC VSync Offset Pulse Width Register
Address Offset:
Default Value:
46h
01h
Access:
Size:
Bit
Access
Symbol
[7:4]
[3:0]
RO
R/W
Reserved
VsPulseWidth[3:0]
Read/Write
8 bits
Description
Pulse width of the regenerated ADC VSync (# lines).
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3.2.17 ADC Capture Control Register
Address Offset:
Default Value:
47h
00h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
[5]
[4]
[3:1]
[0]
R/W
R/W
R/W
R/W
RO
R/W
Mask_H_Left
Mask_H_Right
Mask_V_Top
Mask_V_Bottom
Reserved
Reserved
Read/Write
8 bits
Description
Set to 1 for mask left portion when wrap.
Set to 1 for mask right portion when wrap.
Set to 1 for mask top portion when wrap.
Set to 1 for mask bottom portion when wrap.
Reserved for chip test only
3.2.18 ADC Capture HSize LSB Register
Address Offset:
Default Value:
48h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
ADC_HSize[7:0]
Read/Write
8 bits
Description
ADC Capture window: Horizontal Size (# dots).
3.2.19 ADC Capture HSize MSB Register
Address Offset:
Default Value:
49h
02h
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
ADC_HSize[10:8]
Read/Write
8 bits
Description
ADC Capture window: Horizontal Size (# dots).
3.2.20 ADC Capture VSize LSB Register
Address Offset:
Default Value:
4Ah
E0h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
ADC_VSize[7:0]
Read/Write
8 bits
Description
ADC Capture window: Vertical Size (# lines).
3.2.21 ADC Capture VSize MSB Register
Address Offset:
Default Value:
4Bh
01h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
R/W
Reserved
ADC_VSize[9:8]
Read/Write
8 bits
Description
ADC Capture window: Vertical Size (# lines).
3.2.22 ADC Capture HSync Back Porch LSB Register
Address Offset:
Default Value:
4Ch
10h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
ADC_HStart[7:0]
Read/Write
8 bits
Description
ADC Capture window: HSync Start Point (# dots).
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3.2.23 ADC Capture HSync Back Porch MSB Register
Address Offset:
Default Value:
4Dh
00h
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
ADC_HStart[10:8]
Read/Write
8 bits
Description
ADC Capture window: HSync Start Point (# dots).
3.2.24 ADC Capture VSync Back Porch LSB Register
Address Offset:
Default Value:
4Eh
05h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
ADC_VStart[7:0]
Read/Write
8 bits
Description
ADC Capture window: VSync Start Point (# linees).
3.2.25 ADC Capture VSync Back Porch MSB Register
Address Offset:
Default Value:
4Fh
00h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
R/W
Reserved
ADC_VStart[9:8]
Read/Write
8 bits
Description
ADC Capture window: VSync Start Point (# linees).
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3.3 Picture Enhancement Register Set
3.3.1
DCTI Control Register
Address Offset:
Default Value:
3.3.2
Bit
Access
Symbol
RO
R/W
RO
R/W
Reserved
DCTi_Dist_Sel
Reserved
DLTi_Dist_Sel
Description
DCTI distance selection: 1 for longer distance
DLTI distance selection: 1 for longer distance
Access:
Size:
Access
Symbol
[7]
[6]
[5:0]
R/W
R/W
R/W
Peaking_En
Peaking_LR_Disable
Peaking_Coring
8 bits
Description
Enable Peaking function
Peaking boundary mode
Peaking Band-Pass Coefficient Register
62h
04h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
Peaking_BP_Coef
8 bits
Description
Peaking High-Pass Coefficient Register
63h
04h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
Peaking_HP_Coef
8 bits
Description
Peaking Low-Pass Coefficient Register
Address Offset:
Default Value:
3.3.6
61h
08h
Bit
Address Offset:
Default Value:
3.3.5
Read/Write
8 bits
Peaking Register
Address Offset:
Default Value:
3.3.4
Access:
Size:
[7:3]
[2]
[1]
[0]
Address Offset:
Default Value:
3.3.3
60h
00h
64h
02h
Access:
Size:
Bit
Access
Symbol
[7:3]
[1:0]
RO
R/W
Reserved
Peaking_LP_Coef
8 bits
Description
DCTI_0 Gain and Coring Register
Address Offset:
Default Value:
65h
08h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4:0]
R/W
R/W
DCTI_GAIN_0
DCTI_CO_0
Read/Write
8 bits
Description
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DCTI_1 Gain and Coring Register
Address Offset:
Default Value:
66h
08h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4:0]
R/W
R/W
DCTI_GAIN_1
DCTI_CO_1
3.3.8
Read/Write
8 bits
Description
Cb/Cr Delay control
Address Offset:
Default Value:
67h
1Eh
Access:
Size:
Bit
Access
Symbol
[7]
R/W
U_delay
[6:5]
R/W
V_delay
[4:0]
R/W
DCTI_Threshold
3.3.9
Read/Write
8 bits
Description
Cb signal delay control.
0: no delay (default)
1: 1 pixel delay
Cr signal delay control.
00: no delay (default)
01: 1 pixel delay
10: 2 pixel delay
11: 3 pixel delay
DCTI performing Threshold Limit
Contrast Adjust Register
Address Offset:
Default Value:
68h
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
LumaCON
3.3.10
Description
Brightness Adjust Register
Address Offset:
Default Value:
69h
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
LumaBRI
3.3.11
Read/Write
8 bits
Read/Write
8 bits
Description
Hue Sin Adjust Register
Address Offset:
Default Value:
6Ah
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HueSin
Read/Write
8 bits
Description
3.3.12 Hue Cos Adjust Register
Address Offset:
Default Value:
6Bh
7Fh
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HueCos
Read/Write
8 bits
Description
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Chroma Saturation Adjust Register
Address Offset:
Default Value:
6Ch
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
ChomSat
Read/Write
8 bits
Description
3.3.14 Black Level Expansion Threshold Register
Address Offset:
Default Value:
6Eh
10h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
BLE_TH
3.3.15
Read/Write
8 bits
Description
VIP Black level Expansion Gain / Offset Control Register
Address Offset:
DefaultValue:
6Fh
00h
Access:
Size:
Bit
Access
Symbol
[7:4]
R/W
BLE_GAIN
[3:2]
RO
Reserved
[1:0]
R/W
BLE_OFFSET
Read/Write
8 bits
Description
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3.4 Scaling Register Set
3.4.1
Scaling General Control Register
Address Offset:
Default Value:
3.4.2
Bit
Access
Symbol
R/W
R/W
Reserved
Inv_VideoF
[4:3]
[2:1]
[0]
R/W
RO
WO
Reserved
Reserved
Coef_Pointer_Reset
Description
Inv_VideoF: Reverse input odd field control for intra-field scaling, only
take action when ITLCPRO set to 1.
Write 1 to reset pointer, must be performed before programming
scaling coefficients.
Access:
Size:
Access
Symbol
[7:0]
R/W
H_Scale_Step [7:0]
Read/Write
8 bits
Description
Horizontal Scale Step MSB Register
73h
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
H_Scale_Step [15:8]
Read/Write
8 bits
Description
Vertical Scale Step LSB Register
74h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
V_Scale_Step [7:0]
Read/Write
8 bits
Description
Vertical Scale Step MSB Register
Address Offset:
Default Value:
3.4.6
72h
00h
Bit
Address Offset:
Default Value:
3.4.5
Read/Write
8 bits
Horizontal Scale Step LSB Register
Address Offset:
Default Value:
3.4.4
Access:
Size:
[7:6]
[5]
Address Offset:
Default Value:
3.4.3
70h
00h
75h
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
V_Scale_Step [15:8]
Read/Write
8 bits
Description
Horizontal Aspect Ratio LSB Register
Address Offset:
Default Value:
76h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
H_Aspect[7:0]
Read/Write
8 bits
Description
Horizontal Aspect Ratio [7:0]
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Horizontal Aspect Ratio MSB Register
Address Offset:
Default Value:
Bit
Access
[7]
[6]
R/W
R/W
[5:4]
[3:0]
RO
R/W
3.4.8
77h
00h
Access:
Size:
Read/Write
8 bits
Symbol
Description
H_Aspect_En
Horizontal Aspect Ratio Enable
HASP_Center_Enlarge Horizontal Aspect adjusting effect:
0: Center portion shrink
1: Center portion enlarge
Reserved
H_Aspect[11:8]
Horizontal Aspect Ratio [11:8]
Low Pass Filter Register
Address Offset:
Default Value:
78h
00h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
[5:4]
[3]
[2]
[1:0]
R/W
RO
R/W
R/W
RO
R/W
En_Half_input
Reserved
LP_Average[1:0]
LP_Boundary_Dup
Reserved
LP_ShiftDot[1:0]
3.4.9
Read/Write
8 bits
Description
Enable Low pass
Shift average level in Low Pass enabled
Duplicate the first dot or not
Shift dot count during Low Pass enabled
Frame Color (Luma-Y) in Scaler Register
Address Offset:
Default Value:
7Dh
10h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
Scale_Frame_Y[7:0]
Read/Write
8 bits
Description
Background (Frame) Y Color of Scaler.
3.4.10 Frame Color (Chroma-U) in Scaler Register
Address Offset:
Default Value:
7Eh
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
Scale_Frame_U[7:0]
3.4.11
Description
Background (Frame) U Color of Scaler.
Frame Color (Chroma-V) in Scaler Register
Address Offset:
Default Value:
7Fh
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
Scale_Frame_V[7:0]
3.4.12
Read/Write
8 bits
Read/Write
8 bits
Description
Background (Frame) V Color of Scaler.
Line Buffer Configuration LSB Register
Address Offset:
Default Value:
84h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
LBPRFL[7:0]
Read/Write
8 bits
Description
LBPRFL can cause a time dealy in XCLK count between the leading
edge of input Vsync and leading edge of output Vsync.
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Line Buffer Configuration MSB Register
Address Offset:
Default Value:
85h
01h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
LBPRFL[15:8]
Read/Write
8 bits
Description
3.4.14 Left Display Border Configuration LSB Register
Address Offset:
Default Value:
88h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HLDSPLB[7:0]
Read/Write
8 bits
Description
When Output pixel’s index is less than HRDSPLB, output pixel value
is assigned as left display border with Frame color: {FMCLRRED,
FMCLRGRN , FMCLRBLU}
3.4.15 Left Display Border Configuration MSB Register
Address Offset:
Default Value:
89h
00h
Access:
Size:
Bit
Access
Symbol
[7]
R/W
HDSPLB_INV
[6]
R/w
VDSPLB_INV
[5]
R/W
HDSPLB_STY
[4]
R/W
VDSPLB_STY
[3]
[2:0]
RO
R/W
Reserved
HLDSPLB[10:8]
3.4.16
Description
Horizontal border is on if HDSPLB_INV is set as follows
1: HLDSPLB < Horizontal border < HRDSPLB
0: Horizontal border < HLDSPLB or it > HRDSPLB
Vertical border is on if VDSPLB_INV is set as follows
1: VTDSPLB < < VBDSPLB
0: Vertical border < VTDSPLB or it > VBDSPLB
Horizontal Border style
1: mesh
0: solid
Vertical Border style
1: mesh
0: solid
Right Display Border Configuration LSB Register
Address Offset:
Default Value:
8Ah
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HRDSPLB[7:0]
3.4.17
Read/Write
8 bits
Read/Write
8 bits
Description
When Output pixel’s index is greater than HRDSPLB, output pixel
value is assigned as right display border with Frame color
Right Display Border Configuration MSB Register
Address Offset:
Default Value:
8Bh
00h
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
HRDSPLB[10:8]
Read/Write
8 bits
Description
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Top Display Border Configuration LSB Register
Address Offset:
Default Value:
8Ch
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
VTDSPLB[7:0]
3.4.19
8Dh
00h
Access:
Size:
Bit
Access
Symbol
[7:6]
R/W
HDSPLB_GRID[1:0]
[5:4]
R/W
VDSPLB_GRID[1:0]
[3:2]
[1:0]
RO
R/W
Reserved
VTDSPLB[9:8]
Read/Write
8 bits
Description
H grip precision,
00b: 1 pixel
01b: 4 pixels
10b: 16 pixels
11b: 32 pixels
V grip precision
00b: 1 line
01b: 4 lines
10b: 16 lines
11b: 32 lines
Bottom Display Border Configuration LSB Register
Address Offset:
Default Value:
8Eh
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
VBDSPLB[7:0]
3.4.21
Description
Top Display Border Configuration MSB Register
Address Offset:
Default Value:
3.4.20
Read/Write
8 bits
Read/Write
8 bits
Description
Bottom Display Border Configuration MSB Register
Address Offset:
Default Value:
8Fh
00h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
R/W
Reserved
VBDSPLB[9:8]
Read/Write
8 bits
Description
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3.5 Gamma and Pattern Gen. Register Set
3.5.1
Image Function Control Register
Address Offset:
Default Value:
3.5.2
90h
04h
Access:
Size:
Bit
Access
Symbol
[7:6]
R/W
GATS[1:0]
[5]
[4:2]
[1]
[0]
R/W
R/W
R/W
R/W
Gamma_BIST_En
Reserved
EN_GAMMA
EN_DITHER
Read/Write
8 bits
Description
Gamma Table Select. Default=2’b00.
00b: All R/G/B Gamma tables
01b: B Gamma table
10b: G Gamma table
11b: R Gamma table
Enable Gamma RAM BIST.
Enable Gamma.
Enable Dithering:
0: Disable Dithering, output full 8 bit
1: 6 bits Dithering
Built-in Pattern Generator Control Register
Address Offset:
Default Value:
91h
04h
Access:
Size:
Bit
Access
Symbol
[7]
R/W
EFMCLR
[6]
R/W
ESLDSW
[5]
[4]
R/W
R/W
EVBAR
PLBIT
[3:0]
R/W
PTN
Read/Write
8 bits
Description
Enable Frame background color
Turn on this bit may disable Scaler’s color and show userdefined color on LCD panel.
See 0x9D, 0x9E and 0x9F for user-defined frame color.
This bit may enable pattern generator shows 9 patterns
sequentially.
EFMCLR, ESLDSW
Output
2'b0X
Normal Color
2'b10
Still pattern
2'b11
Motion patterns
Enable Vertical Bar Patterns
1: indicate 8-bit patterns
0:indicate 6-bit patterns
Show nth pattern on LCD panel when EFMCLR is enabled
When Both EFMCLR and ESLDSW are enabled, pattern generator
may show 0, 1 ,2 ...up to PTNth.
3.5.3
GAMMA RAM BIST Result Register
Address Offset:
Default Value:
92h
X0h
Access:
Size:
Read/Write
8 bits
Bit
Access
Symbol
Description
[7]
RO
Gamma_BIST_Done
[6:4]
[3:0]
RO
RO
Gamma_R/G/B_Fail
Reserved
When Gamma RAM BIST finish, this bit will be set to 1, then the other
P0_92<6:4> bits are valid.
When Gamma RAM (R/G/B RAMs) BIST result: 0=pass, 1=fail.
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GAMMA Table Address Port Register
Address Offset:
Default Value:
93h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
GAMMA_ADR
3.5.5
Read/Write
8 bits
Description
Gamma coefficient table address. The Index range is 00h~FFh
GAMMA Table Write Data Port Register
Address Offset:
Default Value:
94h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
WO
GAMMA_WR_D
3.5.6
Write Only
8 bits
Description
Gamma coefficient write data port.
Pattern Bar Width Register
Address Offset:
Default Value:
96h
3Ch
Access:
Size:
Read/Write
8 bits
Bit
Access
Symbol
Description
[7:0]
R/W
Pattern_Bar_Width
This is for generated pattern vertical bar width (for patterns: Color Bar
or Gray ramp)
3.5.7
Pattern Color Gradient & Dithering Mode Register
Address Offset:
Default Value:
9Ch
00h
Access:
Size:
Bit
Access
Symbol
[7:4]
R/W
CLRGRDT[3:0]
[3:0]
R/W
Reserved
3.5.8
Read/Write
8 bits
Description
When EFMCLR are enabled, CLRGRDT may set color gradient at
pattern 2, 3 ,4, 5
Frame Color Red Configuration Register
Address Offset:
Default Value:
9Dh
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
FMCLRRED
3.5.9
Read/Write
8 bits
Description
8 bits of red color depth for frame color.
Frame Color Green Configuration Register
Address Offset:
Default Value:
9Eh
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
FMCLRGRN
3.5.10
Read/Write
8 bits
Description
8 bits of green color depth for frame color.
Frame Color Blue Configuration Register
Address Offset:
Default Value:
9Fh
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
FMCLRBLU
Read/Write
8 bits
Description
8 bits of blue color depth for frame color.
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3.6 OSD1 Register Set
(For detail OSD1 description, please refer to section 2.6 OSD.)
3.6.1
OSD1 Configuration Index Port Register
Address Offset:
Default Value:
3.6.2
Bit
Access
Symbol
W
OSD1_CFG_INDEX
Description
OSD1 Configuration Address Port
Access:
Size:
Access
Symbol
[7:0]
R/W
OSD1_CFG_DATA
Read/Write
8 bits
Description
OSD1 Configuration Data Port
OSD1 RAM Address Port Register
A2h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
[1]
[0]
WO
RO
RO
OSD1_RAM_A
OSD1_RAM_Ready
OSD1_Cfg_Ready
Write Only
8 bits
Description
OSD1 RAM Address Port, LSB first, then MSB
OSD1 RAM is ready for next programming
OSD1 configuration is ready for next programming
OSD1 RAM Data Port Register
A3h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
OSD1_RAM_D
Read/Write
8 bits
Description
OSD1 RAM Data Port
OSD1 Pattern Fill Configuration Index Port Register
Address Offset:
Default Value:
3.6.6
A1h
00h
Bit
Address Offset:
Default Value:
3.6.5
Write Only
8 bits
OSD1 Configuration Data Port Register
Address Offset:
Default Value:
3.6.4
Access:
Size:
[7:0]
Address Offset:
Default Value:
3.6.3
A0h
00h
Bit
Access
[7:0]
WO
A8h
00h
Access:
Size:
Write Only
8 bits
Symbol
Description
OSD1PF_CFG_INDEX OSD1 Pattern Fill Configuration Address Port
OSD1 Pattern Fill Configuration Data Port Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
A9h
00h
Access:
Size:
Symbol
Read/Write
8 bits
Description
OSD1PF_CFG_DATA OSD1 Pattern Fill Configuration Data Port
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3.7 LCD Output Control Register Set
3.7.1
Display Window Horizontal Start Register
Address Offset:
Default Value:
3.7.2
Bit
Access
Symbol
R/W
DWHS_L[7:0]
Symbol
[7:0]
R/W
DWVS[7:0]
Read/Write
8 bits
Description
Vertical back porch
Display Window Horizontal Width LSB Register
B4h
E0h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
DWHSZ[7:0]
Read/Write
8 bits
Description
Horizontal Active.
Display Window Horizontal Width MSB Register
B5h
01h
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
DWHSZ[10:8]
Read/Write
8 bits
Description
Horizontal Active.
Display Window Vertical Width LSB Register
B6h
EAh
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
DWVSZ[7:0]
Read/Write
8 bits
Description
Vertical Active.
Display Window Vertical Width MSB Register
Address Offset:
Default Value:
3.7.7
Description
Horizontal back porch.
Access:
Size:
Access
Address Offset:
Default Value:
3.7.6
B2h
10h
Bit
Address Offset:
Default Value:
3.7.5
Read/Write
8 bits
Display Window Vertical Start Register
Address Offset:
Default Value:
3.7.4
Access:
Size:
[7:0]
Address Offset:
Default Value:
3.7.3
B0h
20h
B7h
00h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
R/W
Reserved
DWVSZ[9:8]
Read/Write
8 bits
Description
Display Panel Horizontal Total Dots per Scan Line LSB Register
Address Offset:
Default Value:
B8h
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
PH_TOT[7:0]
Read/Write
8 bits
Description
Output horizontal total dots
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Display Panel Horizontal Total Dots per Scan Line MSB Register
Address Offset:
Default Value:
B9h
03h
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
PH_TOT[10:8]
3.7.9
Read/Write
8 bits
Description
Display Panel Vertical Total Lines per Frame LSB Register
Address Offset:
Default Value:
BAh
58h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
PV_TOT[7:0]
3.7.10
BBh
02h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
R/W
Reserved
PV_TOT[9:8]
Read/Write
8 bits
Description
Display Panel HSYNC Width Register
Address Offset:
Default Value:
BCh
10h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
PH_PW[7:0]
3.7.12
Description
Output vertical total lines
Display Panel Vertical Total Lines per Frame MSB Register
Address Offset:
Default Value:
3.7.11
Read/Write
8 bits
Read/Write
8 bits
Description
Display Panel VSYNC Width Register
Address Offset:
Default Value:
BEh
02h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
PV_PW[4:0]
Read/Write
8 bits
Description
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Panel Output Signal Control 1 Register
Address Offset:
Default Value:
3.7.14
Copyright by Terawins, Inc.
C0h
01h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
[5]
R/W
RO
R/W
Reserved
Reserved
En_sPanel
[4]
[3]
R/W
R/W
Reserved
Data_Neg
[2]
R/W
PHSync_Polarity
[1]
R/W
PVSync_Polarity
[0]
R/W
PHDE_Polarity
Read/Write
8 bits
Description
Enable Serial RGB (sPanel) output.
0: for Analog panel (DAC output with TCON)
1: for Serial RGB panel (sD[7:0] + DCLKO + HS/VS/HDE)
Reverse RGB output.
0: No reverse
1: RGB reverse.
PHSYNC Polarity. Default=0.
0: Active Low
1: Active High
PVSYNC Polarity. Default=0.
0: Active Low
1: Active High
PDE polarity. Default=1.
0: Active Low
1: Active High
Panel Output Signal Control 3 Register
Address Offset:
Default Value:
C1h
10h
Access:
Size:
Bit
Access
Symbol
[7:4]
[3]
R/W
R/W
Reserved
DCLK_INV
[2:1]
[0]
RO
R/W
Reserved
Half_CPHn
Read/Write
8 bits
Description
CLKO Polarity. Default=0.
0: Non-Invert, CLKO rising aligns to Data transition
1: Inverted, CLKO falling aligns to Data transition
Half CPHn frequency when set to 1.
3.7.15 Panel VSYNC Frame Delay Control Register
Address Offset:
Default Value:
C2h
00h
Access:
Size:
Bit
Access
Symbol
[7]
[6:5]
[4]
RO
R/W
R/W
Reserved
Reserved
PSYNC_STR
[3]
[2]
[1]
R/W
RO
R/W
Reserved
Reserved
IGNORE_VSYNC
[0]
WO
Reserved
Read/Write
8 bits
Description
For Frame lock, input VSync (if exist) will trigger output VSync
0: Allow input vsync to trigger output vsync
1: Block input vsync triggering on output vsync
Ignore the input VSYNC. This can be used for output free run when
input VSYN is not available
For Chip Test only
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3.7.16 Serial RGB HSync Delay Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
C5h
60h
Access:
Size:
Read/Write
8 bits
Symbol
Description
sPanel_HS_Delay[7:0] Delay output HSync for sPanel. (count in 3x panel clock) Value must
>= 02h. This register is used to shift sPanel_HS, and align correct
RGB color in sequence, for some sPanel do not have HDE input.
3.7.17 Output RGB Reordering Register
Address Offset:
Default Value:
C7h
00h
Access:
Size:
Bit
Access
Symbol
[7]
[6:4]
[3]
RO
R/W
R/W
Reserved
Reserved
BIGENDIANE
[2:0]
R/W
RGBSWAPE
3.7.18
C8h
15h
Reverse bit [7:0] of RGB:
0: Non-Inverted, Little Endian.
1: Inverted, Big Endian.
RGB Channel Swapping
Access:
Size:
Bit
Access
Symbol
[7]
[6:0]
RO
R/W
Reserved
PLLDIV_F
Read/Write
8 bits
Description
PLL feedback divider.
Output PLL Divider 2 Register
Address Offset:
Default Value:
Bit
Access
[7]
[6:5]
[4:0]
R/W
R/W
R/W
3.7.20
Description
Output PLL Divider 1 Register
Address Offset:
Default Value:
3.7.19
Read/Write
8 bits
C9h
02h
Access:
Size:
Read/Write
8 bits
Symbol
Description
SS_Clock_En
Enable Spread Spectrum clock output
SS_Clock_Deviation[1:0] Spread Spectrum clock deviation selection
PLLDIV_I
PLL Input Divider.
Output PLL Divider 3 Register
Address Offset:
Default Value:
CAh
03h
Access:
Size:
Bit
Access
Symbol
[7:6]
R/W
PLLMX
Read/Write
8 bits
Description
PLL MUX Function Select
PLLMX
2'b00
2'b01
2'b10
2'b11
[5]
R/W
PLLPD
[4]
R/W
PLL_Div2
Mode
PLLCLK
Keep High
Bypass PLL
Bypass PLL
Display PLL power down Control:
0: Display PLL power on
1: Display PLL power down
Display PLL analog divider, set 1 to half frequency output
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[3:2]
R/W
PLL_OUT_SEL
[1:0]
R/W
PLLDIV_O
PLL additional divider
0: no divider
1: divided by 2
2: divided by 4
3: divided by 8
PLL Output Divider. Default=1.
output_freq = 27Mhz * (F + 2) / (I+2) / (2^(O+1) )
3.7.21 LLCKn Clock Register
Address Offset:
Default Value:
CBh
10h
Access:
Size:
Bit
Access
Symbol
[7:4]
[3:0]
R/W
R/W
LLCK1_Phase[3:0]
LLCK_DivideN[3:0]
Read/Write
8 bits
Description
CPH1 (LLCK1) phase, 1<= value <= LLCK_DivideN[3:0]
LLCK pre-divider. 0/1 for no divide;
3.7.22 Output LLCK Control 2 Register
Address Offset:
Default Value:
CCh
32h
Access:
Size:
Bit
Access
Symbol
[7:4]
[3:0]
R/W
R/W
LLCK3_Phase[3:0]
LLCK2_Phase[3:0]
3.7.23
Description
CPH3 (LLCK3) phase, 1<= value <= LLCK_DivideN[3:0]
CPH2 (LLCK2) phase, 1<= value <= LLCK_DivideN[3:0]
Display Window Horizontal Start Register
Address Offset:
Default Value:
D8h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HMDISP_STR[7:0]
3.7.24
Read/Write
8 bits
Read/Write
8 bits
Description
Display Window Vertical Start Register
Address Offset:
Default Value:
DAh
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
VMDISP_STR
Read/Write
8 bits
Description
3.7.25 Display Window Horizontal Size LSB Register
Address Offset:
Default Value:
DCh
E0h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HMDISP_SIZE[7:0]
Read/Write
8 bits
Description
3.7.26 Display Window Horizontal Size MSB Register
Address Offset:
Default Value:
DDh
01h
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
HMDISP_SIZE[10:8]
Read/Write
8 bits
Description
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3.7.27 Display Window Vertical Size LSB Register
Address Offset:
Default Value:
DEh
EAh
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
VMDISP_SIZE[7:0]
Read/Write
8 bits
Description
3.7.28 Display Window Vertical Size MSB Register
Address Offset:
Default Value:
DFh
00h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
R/W
Reserved
VMDISP_SIZE[9:8]
Read/Write
8 bits
Description
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3.8 Global Control Register Set
3.8.1
Power Management Control Register
Address Offset:
Default Value:
3.8.2
Access:
Size:
Bit
Access
Symbol
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PD_TotalPad_
PD_ADCD_
PD_VIP_
PD_VD_
LLCK1_EN
LLCK2_EN
LLCK3_EN
PD_TC_
Read/Write
8 bits
Description
Set to 0 for Power Down all I/O pads, except I2C I/F.
Set to 0 for Power Down ADC digital portion.
Power down ITU-R656, L601 interface, active low
Set to 0 for Power Down Comb Video Decoder block.
LLCK1 enable
LLCK2 enable
LLCK3 enable
Set to 0 for Power down TC interface.
Output Pin Configuration
Address Offset:
Default Value:
3.8.3
E0h
10h
E1h
00h
Access:
Size:
Read/Write
8 bits
Bit
Access
Symbol
[7:6]
R/W
RowSTV_Sel
Description
RowSTV_Sel
2'b00
2'b01
2'b10
2'b11
Mode
Output both
Output both
Output STV1
Output STV2
[5:4]
R/W
ColSTH_Sel
ColSTH_Sel
2'b00
2'b01
2'b10
2'b11
Mode
Output both
Output both
Output STH1
Output STH2
[3]
[2]
[1:0]
R/W
R/W
RO
UD_Sel
RL_Sel
Reserved
Set UD output value
Set RL output value
Shadow Control Configuration
Address Offset:
Default Value:
E2h
10h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4]
[3:1]
[0]
RO
R/W
RO
WO
Reserved
Shadow_Enable
Reserved
Shadow_Sync
Read/Write
8 bits
Description
1: Enable registers shadow control
Write 1 to sync all shadowed registers
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3.8.4
DAC Power Management
Address Offset:
Default Value:
3.8.5
Access:
Size:
Access
Symbol
[7]
R/W
PDn_Bias
[6]
R/W
PDn_VCOM
[5]
R/W
PDn_Regulator
[4]
R/W
PDn_DC2DC
[3]
R/W
SL
[2]
R/W
SLR
[1]
R/W
SLG
[0]
R/W
SLB
Read/Write
8 bits
Description
1: power down Bias circuit
0: power on Bias circuit
1: power down Analog VCOM Amp circuit
0: power on Analog VCOM Amp circuit
1: power down Regulator circuit
0: power on Regulator circuit
1: power on DC to DC circuit
0: power down DC to DC circuit
1: power down 3 channels
0: power on 3 channels
1: power down R channel
0: power on R channel
1: power down G channel
0: power on G channel
1: power down B channel
0: power on B channel
Analog Output Current 1 Register
E4h
0Fh
Access:
Size:
Bit
Access
Symbol
[7:5]
[4:0]
R/W
R/W
VCOM_DC[2:0]
DAC_Amp[4:0]
Read/Write
8 bits
Description
LSB of VCOM DC setting
DAC Amp setting
Analog Output Current 2 Register
Address Offset:
Default Value:
3.8.7
E3h
10h
Bit
Address Offset:
Default Value:
3.8.6
Copyright by Terawins, Inc.
E5h
00h
Access:
Size:
Bit
Access
Symbol
[7]
[6:5]
[4:0]
R/W
R/W
R/W
VCOM_VoltagePeak
VCOM_DC[4:3]
VCOM_Amp[4:0]
Read/Write
8 bits
Description
VCOM voltage peak setting
MSB of VCOM DC setting
VCOM Amp setting
Power Down Register
Address Offset:
Default Value:
E6h
3Ch
Access:
Size:
Bit
Access
Symbol
[7]
R/W
PD_CombLB
[6]
R/W
PD_XCLK2MC
[5]
R/W
PDn_LED
[4]
R/W
PDn_Inverter
[3]
[2:0]
R/W
R/W
OpnLmpPrtct_En
BackLight_Dim [2:0]
Read/Write
8 bits
Description
1: power down Video Decoder Comb Line Buffers
0: power on Video Decoder Comb Line Buffers
1: Tri-state XCLK2MC output
0: Allow XCLK2MC output
1: power on LED circuit
0: power down LED circuit
1: power on Inverter circuit
0: power down Inverter circuit
1 for Open Lamp Protection Enabled; else disabled
Back Light Dim level control.
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3.8.8
CCFL/LED Control Register
Address Offset:
Default Value:
3.8.9
Copyright by Terawins, Inc.
E7h
80h
Access:
Size:
Bit
Access
Symbol
[7]
R/W
DIM_Source_Sel
[6]
[5:4]
[3:0]
R/W
R/W
R/W
Read/Write
8 bits
Description
DIM PWM source select:
0: analog PWM
1: digital PWM
DeadTimeControl
Dead Timer Control
OpnLmp_Current[1:0] Open Lamp Current setting
Inverter_Freq_Sel[1:0] Inverter frequency selection
PWM_1 General Control Register
Address Offset:
Default Value:
E8h
07h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5]
[4]
[3]
[2:0]
R/W
R/W
R/W
RO
R/W
PWM1_Low[4:3]
PWM1_Alt_Mode
PWM1_En
Reserved
PWM1_Freq_Sel
Read/Write
8 bits
Description
1: Alternative PWM1 mode; 0: Legacy {PWM1_High/256} mode
Enable PWM_1
This register set the PWM1 counter base clock = XCLK / 2^N, N=0, 1,
2, 3, 5, 7, 9, 11. That is, the PWM1 freq = PWM1 base clock freq /
256.
3.8.10 PWM_1 Active High Time Counter Register
Address Offset:
Default Value:
E9h
80h
Access:
Size:
Bit
Access
Symbol
[7:5]
R/W
PWM1_High[7:5] /
PWM1_Low[2:0]
[4:0]
R/W
PWM1_High[4:0]
Read/Write
8 bits
Description
InPWM1 legacy mode, this register set PWM1 high time
(PWM1_High[7:0]/256) counted by PWM1 base clock.
In PWM1 Alternative mode, the PWM1 output: PWM1_High[4:0] /
( PWM1_Low[4:0] + PWM1_High[4:0]), based clock is divide from
XCLK , see P0_E8<2:0>
This register set PWM1 high time counted by PWM1 base clock. The
based clock is divide from XCLK , see P0_E8<2:0>
3.8.11 PWM_2 General Control Register
Address Offset:
Default Value:
Bit
Access
[7]
R/W
[6]
R/W
[5]
R/W
[4]
[3]
R/W
RO
EAh
27h
Access:
Size:
Symbol
Read/Write
8 bits
Description
PWM2_Fine_Freq_Mode Select PWM_2 operating clock mode:
0: original XCLK/2^n mode, same as PWM1
1: fine frequency mode, XCLK/PWM2_Fine_Freq[10:0]
PWM2_Cfg_FineFreq Select which setting for programming
1: allow configuring clock divider: PWM2_Fine_Freq[10:0];
0: configure original PWM2_Freq_Sel[2:0] and PWM2_High[7:0]
CCFL_PWM_Sel
Select digital PWM output to CCFL:
0: PWM1 output
1: PWM2 output
PWM2_En
Enable PWM_2
Reserved
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PWM2_Freq_Sel[3:0] When PWM2_Cfg_FineFreq=0, these bits select PWM2 counter base
or
clock = XCLK / 2^(2*n+3), That is, the PWM2 freq = PWM2 base clock
PWM2_Fine_Freq[10:8] freq / 256.
When PWM2_Cfg_FineFreq=1, these bits as MSB for PWM2 clock
divider.
3.8.12 PWM_2 Active High Time Counter Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
3.8.13
EBh
80h/D1h
Read/Write
8 bits
Symbol
Description
When PWM2_Cfg_FineFreq=0, this register sets PWM2 high time
counted by PWM2 base clock. Default value is 80h. The based clock
is divide from XCLK , see P0_EA<2:0>.
PWM2_Fine_Freq[7:0] When PWM2_Cfg_FineFreq=1, this register as LSB for PWM2 clock
divider. Default value is D1h.
PWM2_High[7:0]
or
DAC Offset Control Register
Address Offset:
Default Value:
EDh
00h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
DAC_Offset[4:0]
3.8.14
Access:
Size:
Read/Write
8 bits
Description
DAC Offset setting
Serial Bus Control Register
Address Offset:
Default Value:
F1h
C4h
Access:
Size:
Read/Write
8 bits
Bit
Access
Symbol
Description
[7]
[6]
[5]
[4]
[3]
[2]
R/W
RO
R/W
RO
R/W
R/W
SCL_Out
SCL_In
SDA_Out
SDA_In
XBus_En
I2CATINCADR
SCL output value, when i8051 enabled and acts as an I2C master
SCL input status
SDA output value, when i8051 enabled and acts as an I2C master
SDA input status
Reserved for chip testing
Set to 1 for enabling 2-wire serial bus automatic address increment in
multiple R/W Access mode. Default=1’b1.
[1:0]
RO
Reserved
3.8.15
Vendor ID 1 Register
Address Offset:
Default Value:
F3h
54h
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
VID_L
3.8.16
Read Only
8 bits
Description
Reading this register obtains ASCII code “T”.
Vendor ID 2 Register
Address Offset:
Default Value:
F4h
57h
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
VID_H
Read Only
8 bits
Description
Reading this register obtains ASCII code “W”.
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3.8.17 Device ID Register
Address Offset:
Default Value:
F5h
C8h
Access:
Size:
Bit
Access
Symbol
[7:0]
RO
DID
3.8.18
Access:
Size:
Access
Symbol
[7:0]
RO
RID
Read Only
8 bits
Description
This field puts a revision number in Hex “A3”.
SRAM BIST Enable Register
Address Offset:
Default Value:
F8h
00h
Access:
Size:
Bit
Access
Symbol
[7]
[6:5]
[4]
[3]
[2]
[1]
[0]
R/W
RO
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
En_8051RAM_BIST
En_VBI_BIST
En_OSD_BIST
En_Comb_BIST
En_SM_BIST
Read/Write
8 bits
Description
Enable Cache RAM, iRAM, xRAM BIST, if set to 1.
Enable VBI RAM BIST, if set to 1.
Enable OSD1 RAM/ROM BIST, if set to 1.
Enable VD Comb RAM BIST, if set to 1.
Enable Scaler Machine LB RAM BIST, if set to 1.
SRAM BIST Finish Register
Address Offset:
Default Value:
F9h
00h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5]
[4]
[3]
[2]
[1]
[0]
RO
RO
RO
RO
RO
RO
RO
Reserved
Done_VHalf_BIST
Done_8051RAM_BIST
Done_VBI_BIST
Done_OSD_BIST
Done_Comb_BIST
Done_SM_BIST
3.8.21
This field puts a part number in Hex “C8” as T108
F6h
A4h
Bit
3.8.20
Description
Revision ID Register
Address Offset:
Default Value:
3.8.19
Read Only
8 bits
Read Only
8 bits
Description
V_Half Line Buffer BIST finish if get 1.
Cache RAM, iRAM, xRAM BIST finish if get 1.
VBI RAM BIST finish if get 1.
OSD1 RAM/ROM BIST finish if get 1.
VD Comb RAM BIST finish if get 1.
Scaler Machine LB RAM BIST finish if get 1.
SRAM BIST Result Register 1
Address Offset:
Default Value:
FAh
XXh
Access:
Size:
Bit
Access
Symbol
[7]
[6]
[5]
[4]
[3:0]
RO
RO
RO
RO
RO
VBI_RAM_Fail
OSD1_BDSRAM_Fail
OSD1_ORAM_Fail
Comb_BIST_fail
SM[3:0]_BIST
Read Only
8 bits
Description
VBI RAM BIST fail if get 1.
OSD1 BDSRAM BIST fail if get 1.
OSD1 ORAM BIST fail if get 1.
VD Comb RAM BIST fail if get 1.
Scaler Machine LB[3:0] BIST fail if get 1.
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SRAM BIST Result Register 2
Address Offset:
Default Value:
FBh
XXh
Access:
Size:
Bit
Access
Symbol
[7:4]
[5]
[4]
[3]
[2]
[1]
[0]
RO
RO
RO
RO
RO
RO
RO
Reserved
VHalf_Buffer_Fail
CacheH_Fail
CacheL_Fail
xRAM_Fail
iRAM_fail
Reserved
3.8.23
Description
V_Half buffer fail if get 1.
8051 Cache high 8KB RAM BIST fail if get 1.
8051 Cache low 8KB RAM BIST fail if get 1.
8051 external RAM BIST fail if get 1.
8051 internal RAM BIST fail if get 1.
Pin Function Select Register
Address Offset:
Default Value:
FEh
00h
Access:
Size:
Bit
Access
Symbol
[7]
R/W
GPOA54_as_UDRL
[6]
R/W
GPOA321_as_TCON
[5]
R/W
GPIC_from_LVY
[4:2]
[1]
[0]
R/W
R/W
R/W
Reserved
BYPS_DAC
BYPS_ADC
3.8.24
Read Only
8 bits
Read/Write
8 bits
:Description
GPOA[5:4] act as:
0: GPOA[5:4] (controlled by P1_51<5:4>);
1: UD and RL (controlled by P0_E1<3:2>)
GPOA[3:1] act as:
0: GPOA[3:1] (controlled by P1_51<3:1>);
1: TCON: STB/CKVB (inverted of some TCON signals)
GPIC[7:0] input from:
0: GPIC[7:0] mux-ed pins;
1: LVY[7:0] pins
For chip testing DAC block
For chip testing ADC block
Page Select Register
Address Offset:
Default Value:
FFh
00h
Access:
Size:
Bit
Access
Symbol
[7:2]
[1:0]
RO
R/W
Reserved
PAGE[1:0]
Read/Write
8 bits
Description
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Serial Bus Register Set Page 1
3.9 TCON Register Set
3.9.1
Timing Controller (TCON) Control Register
Address Offset:
Default Value:
20h
00h
Access:
Size:
Bit
Access
Symbol
[7]
R/W
GScanInt
Read/Write
8 bits
Description
Enable interlaced scanning
Mode
0
1
[6]
R/W
DDR_GDRV
Type
Processive
Interlacing
Enable DDR gate driver
Mode
0
1
[5]
R/W
GTOE
Type
1 line/GCLK
2 lines/GLK
Enable gate driver output
Mode
0
1
[4]
R/W
DbScan_Edge
Type
Shutdown output
Enable
Clock edge of STV
When DbScan_STV_1p is enabled, DbScan_Edge can control STV
alignment with the falling edge o rising edge of GCLK
Mode
0
1
[3]
R/W
DbScan_STV_1p5
Type
Falling edge of GCLK
Rising edge of GCLK
STV 1.5 lines wide
Mode
0
1
[2]
R/W
DbScan_En
Type
1 line wide
1.5 lines wide
Gate driver Scanning control
Mode
0
1
[1]
R/W
Q1HPL
Type
1 GCLK/line
2 GCLKs/line
Q1H polarity
Mode
0
1
[0]
R/W
PNINV
Type
Negative
Positive
Enable line-inverted function.
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Copyright by Terawins, Inc.
Timing Protocol & Polarity Control Register
Address Offset:
Default Value:
21h
FFh
Access:
Size:
Read/Write
8 bits
Bit
Access
Symbol
Description
[7]
RW
DRVRSTPL
[6]
R/W
GTOEPL
This bit may control Source Drive Reset polarity
When P0_E1h<7:6> is not 11b, pin STV2 becomes the rese of source
driver.
This bit may control GOE polarity
Mode
0
1
[5]
R/W
STVPL
Type
Low-active
Highactive
Row Driver start pulse polarity
Mode
0
1
[4]
R/W
CLKVPL
Type
Negative
Positive
Data Inversion Polarity
Mode
0
1
[3]
R/W
FLD1PL
Video Field Polarity
Mode
0
1
[2]
R/W
POLPL
Type
Negative
Positive
Type
Inverted field flag
Non-inverted field flag
Column Driver POL inversion polarity
Mode
0
1
[1]
R/W
LPPL
Type
Negative
Positive
Column Driver Latch Pulse polarity
Mode
0
1
[0]
R/W
STHPL
Type
Negative
Positive
Column Driver Start Pulse polarity
Mode
0
1
Type
Negative
Positive
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3.10 Infra-Red Register Set
3.10.1 IR Sampling Tick LSB Register
Address Offset:
Default Value:
40h
10h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
IR_Tick[7:0]
Read/Write
8 bits
Description
Sampling Tick LSB byte (Unit: XCLK is 27MHz):
NEC mode: 560μs (3B10h);
Philips RC5 mode: 900μs (5EECh)
3.10.2 IR Sampling Tick MSB Register
Address Offset:
Default Value:
41h
3Bh
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
IR_Tick[15:8]
3.10.3
Read/Write
8 bits
Description
Sampling Tick MSB byte.
IR Stream 1~4 Register (when IR_Counter_Mode=0)
Address Offset:
Default Value:
42h~45h
--h
Bit
Access
Symbol
[7:0]
x4
RO
IR_Stream[0..31]
Access:
Size:
Read Only
32 bits
Description
Decoded IR stream (packet) stored in P1_42h~45h
The first received bit is IR_Stream[0], then the next IR_Stream[1], ….
and the last available bit is IR_Stream[31] if packet that long.
IR_Stream[7:0] in P1_42, IR_Stream[15:8] in P1_43,
IR_Stream[23:16] in P1_44, IR_Stream[31:24] in P1_45;
3.10.4 IR Duration 1~3 Register (when IR_Counter_Mode=1)
Address Offset:
Default Value:
42h~44h
--h
Access:
Size:
Read Only
24 bits
Bit
Access
Symbol
Description
[7:0]
x3
RO
IR_Duration[0..21]
(P1_44<7:6> are 00b)
The duration (count in XCLK) of input IR. When IR protocol is not
supported, F/W can use this counter result and IR interrupt to decode.
3.10.5
IR Stream 1 Register
Address Offset:
Default Value:
47h
00h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
R/W
R/W
IR_En
IR_Counter_Mode
[5:4]
R/W
IR_Mode[1:0]
[3]
[2]
[1]
[0]
R/W
RO
RO
RO
IR_Invert
IR_Value
IR_Overflow
IR_Repeat
Read/Write
8 bits
Description
Enable IR Decoder.
Set to 0 for supported IR protocols;
Set to 1 for monitoring IR transition duration (count in XCLK)
IR Decoder Mode:
00: NEC mode; 01: Philips RC5 mode; 1X: Sony mode
Invert IR1 input to IR Decoder.
Current IR value (high or low)
IR duration counter overflow if get 1, then the
Getting 1 indicates the current IR packet is Repeat.
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3.11 ITU - 656 Decoder Register Set
3.11.1 ITU-656 Decoder HS Delay Register
Address Offset:
Default Value:
D0h
30h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HS_DELAY656[7:0]
Read/Write
8 bits
Description
Unit: Cycles of Half VCLK
3.11.2 ITU-656 Decoder HS Pulse Width Register
Address Offset:
Default Value:
D2h
10h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5:3]
[2:0]
RO
R/W
RO
Reserved
HS_WIDTH656[5:3]
Reserved
Read/Write
8 bits
Description
Unit: Cycles of Half VCLK, HS_WIDTH656[2:0] = 000b
3.11.3 ITU-656 Decoder VS Delay Register
Address Offset:
Default Value:
D3h
01h
Access:
Size:
Bit
Access
Symbol
[7:5]
[4:0]
RO
R/W
Reserved
VS_DELAY656[4:0]
Read/Write
8 bits
Description
Unit: HS
3.11.4 ITU-656 Decoder VS Pulse Width Register
Address Offset:
Default Value:
D4h
01h
Access:
Size:
Bit
Access
Symbol
[7]
R/W
VS_in_LineCnt
[6]
[5]
[4:2]
[1:0]
R/W
R/W
RO
R/W
VS_Ex1_Odd
VS_Ex1_Evn
Reserved
VS_WIDTH656[1:0]
Read/Write
8 bits
Description
0: VSync Delay/Width in VCLK count (for those digital video inputs
which have no HREF or its codeword during vertical blank)
1: VSync Delay/Width in Line count (for those digital video inputs
which keeps sending HREF or its codeword during Vertical Blank)
Set to 1 for extra 1 line VSync Offset for Odd field
Set to 1 for extra 1 line VSync Offset for Even field
Unit: HS
3.11.5 ITU-656 Decoder HDE Start Register
Address Offset:
Default Value:
D5h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HSTART656[7:0]
Read/Write
8 bits
Description
Unit: Pixel
3.11.6 ITU-656 Decoder HDE Size LSB Register
Address Offset:
Default Value:
Bit
Access
[7:0] R/W or RO
D7h
D0h
Access:
Size:
Symbol
HSIZE656[7:0]
Read/Write
8 bits
Description
Unit: Pixel, RO if SIZE_DET=1; else R/W
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3.11.7 ITU-656 Decoder HDE Size MSB Register
Address Offset:
Default Value:
Bit
D8h
02h
Access
[7:3]
RO
[2:0] R/W or RO
Access:
Size:
Read/Write
8 bits
Symbol
Reserved
HSIZE656[10:8]
Description
Unit: Pixel
3.11.8 ITU-656 Decoder Odd Field VDE Start Register
Address Offset:
Default Value:
D9h
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
OVSTART656[7:0]
Read/Write
8 bits
Description
Odd Filed VDE Start, Unit: HS
3.11.9 ITU-656 Decoder Odd/Even Field VDE Start Register
Address Offset:
Default Value:
DAh
00h
Access:
Size:
Bit
Access
Symbol
[7]
R/W
EVPluse1
[6:0]
RO
Reserved
Read/Write
8 bits
Description
Even Filed VDE Start
1: EVSTART656=OVSTART + 1
0: EVSTART656=OVSTART
3.11.10 ITU-656 Decoder VDE Size LSB Register
Address Offset:
Default Value:
Bit
DBh
F0h
Access
[7:0] R/W or RO
Access:
Size:
Read/Write
8 bits
Symbol
VSIZE656[7:0]
Description
Unit: HS, RO if SIZE_DET=1; else R/W
3.11.11 ITU-656 Decoder VDE Size MSB Register
Address Offset:
Default Value:
Bit
DCh
00h
Access
[7:2]
RO
[1:0] R/W or RO
Access:
Size:
Read/Write
8 bits
Symbol
Reserved
VSIZE656[9:8]
Description
Unit: HS
3.11.12 ITU-656 Decoder VCLK Tuning Register
Address Offset:
Default Value:
DEh
02h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
RO
R/W
Reserved
LHDE_Yes
[5]
[4]
[3]
[2]
[1]
[0]
R/W
R/W
R/W
R/W
R/W
R/W
LODD_INV
LODD_is_VSYNC
LHREF_INV
LFIEDLD_in_LHREF
VCLK_INV
VCLK_DLY
Read/Write
8 bits
Description
Enable LHDE input for digital RGB input:
0: Ignore LHDE, then requiring setting capture window
1: Use LHDE to capture active window
Set to 1 for invert LODD/LVSYNC pin
Set to 1 if LODD pin acts as VSYNC input
to 1 for invert LHREF/LHSYNC pin
Set to 1 for enabling extract Odd flag from LHREF pin
VCLK skew: invert
VCLK skew: delay
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3.11.13 ITU-656 Decoder Format Control Register
Address Offset:
Default Value:
DFh
40h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
RO
R/W
Reserved
ODDF_INV
[5]
[4]
[3]
[2]
[1]
R/W
R/W
R/W
R/W
R/W
ReSync_OddF
RGB_for_HDTV
A656_V_Align
A656_UV_Intrplt
SIZE_DET
[0]
R/W
Detect_Update_
Read/Write
8 bits
Description
Filed flag indicator
0: 1st field =0, 2nd field=1
1: 1st filed =1, 2nd field=0
Set to 1 for re-synchronizing Odd Flag
Option different color space convert coefficient set
Chroma_V pixel alignment
Interpolate UV pixel values when 422 => 444 converting
Read back Size of HDE and VDE
0:Disable
1:Enable
Size detect result update allow, depends on:
0:Update current detection
1:Keep previous detection
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Serial Bus Register Set Page 2
3.12 Y/C Separation and Chroma Decoder Register Set
3.12.1 Video Source Selection of Comb Filter Register
Address Offset:
Default Value:
00h
00h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5]
RO
R/W
Reserved
PIXEL_CNT
[4]
R/W
LINE_CNT
[3:1]
R/W
TV_MODE
[0]
R/W
INPUT_MODE
3.12.2
Read/Write
8 bits
Description
Pixel per scan line.
0: 858 pixels (default)
1: 864 pixels
Scan lines per frame.
0 = 525 (default)
1 = 625
Video standard.
000 = NTSC (default)
001 = PAL (I,B,G,H,D,N)
010 = PAL (M)
011 = PAL (CN)
100 = SECAM
Video format.
0 = composite (default)
1 = S-Video (separated Y/C)
Bandwidth Control Register
Address Offset:
Default Value:
01h
01h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5:4]
RO
R/W
Reserved
LUMA_FILTER
[3:2]
R/W
CHROMA_FILTER
Read/Write
8 bits
Description
Luma notch filter bandwidth
00 = none (default)
01 = narrow
10 = medium
11 = wide
Chroma low pass filter bandwidth
0 = narrow (default)
1 = wide
2 = extra wide
3 = extra wide
[1]
R/W
BURST_NUMBER
[0]
R/W
PED_ENABLE
Burst gate width
0 = 5 subcarrier clock cycles (default)
1 = 10 subcarrier clock cycles
Blank-to-black pedestal enable
0 = no pedestal subtraction
1 = pedestal subtraction (default)
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Comb Filtering Mode Register
Address Offset:
Default Value:
03h
00h
Access:
Size:
Bit
Access
Symbol
[7:3]
[2:0]
RO
R/W
Reserved
COMB_MODE
Read/Write
8 bits
Description
000 = fully adaptive comb (2-D adaptive comb) (default)
010 = 5-tap adaptive comb filter (PAL mode only)
011 = must be used for S-Video
110 = 5-tap hybrid adaptive comb filter (PAL mode only)
others = reserved.
3.12.4 Luma AGC Target Value Register
Address Offset:
Default Value:
04h
DDh
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
AGC_LEVEL
3.12.5
Read/Write
8 bits
Description
Luma AGC target value.
Standard
Programming Value
NTSC M
DDh (221d) (default)
NTSC J
CDh (205d)
PAL B,D,G,H,I, COMB N, SECAM
DCh (220d)
PAL M,N
DDh (221d)
Y/C Output Control Register
Address Offset:
Default Value:
07h
20h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5:4]
RO
R/W
Reserved
BLUE_SCREEN
[3:0]
R/W
YC_DELAY
Read/Write
8 bits
Description
This bit controls the blue screen mode.
00 = Disabled
01 = Enabled
10 = Auto (Default)
11 = reserved
The range is [-5,7]. Default = 0.
3.12.6 Luma Contrast Register
Address Offset:
Default Value:
08h
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
CONTRAST
Read/Write
8 bits
Description
Luma_out = Luma_in * CONTRAST
where CONTRAST is a 1.7-bit fixed point value.
3.12.7 Luma Brightness Register
Address Offset:
Default Value:
09h
20h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
BRIGHTNESS
Read/Write
8 bits
Description
Luma_out = Luma_in + BRIGHTNESS - 32
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Chroma Saturation Register
Address Offset:
Default Value:
0Ah
80h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
SATURATION
Read/Write
8 bits
Description
Chroma_out = Chroma_in * SATURATION
where SATURATION is a 1.7-bit fixed point value
3.12.9 Chroma Hue Phase Register
Address Offset:
Default Value:
0Bh
00h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
HUE
Read/Write
8 bits
Description
U_out = U_in*cos(HUE/256*360) + V_in * sin(HUE/256*360)
V_out = V_in*cos(HUE/256*360) - U_in * sin(HUE/256*360)
3.12.10 Chroma AGC Register
Address Offset:
Default Value:
0Ch
8ah
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
CHROMA_AGC
Read/Write
8 bits
Description
Chroma AGC target. Default = 138.
3.12.11 AGC Peak Nominal Register
Address Offset:
Default Value:
10h
0ah
Access:
Size:
Bit
Access
Symbol
[7]
[6:0]
RO
R/W
Reserved
AGC_PEAK
Read/Write
8 bits
Description
Luma peak value. Default = 10.
3.12.12 Chroma DTO Incremental 0 Register
Address Offset:
Default Value:
Bit
Access
[7]
R/W
[6]
[5:0]
RO
R/W
18h
21h
Access:
Size:
Read/Write
8 bits
Symbol
Description
CHROMA_FREQ_FIX Fix chroma frequency.
0: disable (default).
1: enable.
Reserved
C_FREQ[29:24]
Bits 29:24 of the 30-bit-wide chroma frequency increment.
3.12.13 Chroma DTO Incremental 1 Register
Address Offset:
Default Value:
19h
F0h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
C_FREQ[23:16]
Read/Write
8 bits
Description
Bits 23:16 of the 30-bit-wide chroma frequency increment.
3.12.14 Chroma DTO Incremental 2 Register
Address Offset:
Default Value:
1Ah
7Ch
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
C_FREQ[15:8]
Read/Write
8 bits
Description
Bits 15:8 of the 30-bit-wide chroma frequency increment.
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3.12.15 Chroma DTO Incremental 3 Register
Address Offset:
Default Value:
1Bh
0Fh
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
C_FREQ[7:0]
Read/Write
8 bits
Description
Bits 7:0 of the 30-bit-wide chroma frequency increment.
3.12.16 Active Video Horizontal Start Time Register
Address Offset:
Default Value:
Bit
Access
[7:0]
R/W
2Eh
82h
Access:
Size:
Symbol
H_START
Read/Write
8 bits
Description
Active video horizontal start position. Default = 130.
3.12.17 Active Video Horizontal Width Register
Address Offset:
Default Value:
2Fh
50h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
H_WIDTH
Read/Write
8 bits
Description
Active video horizontal pixel counts.
Default = 80 Æ 640+80 = 720
3.12.18 Active Video Vertical Start Register
Address Offset:
Default Value:
30h
22h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
V_START
Read/Write
8 bits
Description
Active video vertical line start position. Default = 34.
3.12.19 Active Video Vertical Height Register
Address Offset:
Default Value:
31h
61h
Access:
Size:
Bit
Access
Symbol
[7:0]
R/W
V_WIDTH
Read/Write
8 bits
Description
Active video vertical line counts.
Default = 97 ( 384+97 = 481 half lines
3.12.20 Comb Video Status Register 1
Address Offset:
Default Value:
3Ah
00h
Access:
Size:
Bit
Access
Symbol
[7:5]
RO
mv_colourstripes
[4]
RO
mv_vbi_detected
[3]
RO
chromalock
[2]
RO
vlock
[1]
RO
hlock
[0]
RO
no_signal
Read only
8 bits
Description
Macrovision color stripes detected. The number indicates the number
of color stripe lines in each group
MacroVision VBI pseudo-sync pulses detection
1 = Detected
0 = Undetected
Chroma PLL locked to color burst
1 = Locked
0 = Unlocked
Vertical lock
1 = Locked
0 = Unlocked
Horizontal line locked
1 = Locked
0 = Unlocked
No signal detection
1 = No Signal Detected
0 = Signal Detected
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3.12.21 Soft Reset Register
Address Offset:
Default Value:
3Fh
01h
Access:
Size:
Bit
Access
Symbol
[7:1]
[0]
RO
R/W
Reserved
RESET
Read/Write
8 bits
Description
Soft Reset: Write 1 to reset initial values for comb filter
3.12.22 Luminance Peaking Control Register
Address Offset:
Default Value:
80h
04h
Access:
Size:
Bit
Access
Symbol
[7:6]
[5:4]
[3:1]
[0]
RO
R/W
R/W
R/W
Reserved
Reserved
PEAK_GAIN
PEAK_EN
Read/Write
8 bits
Description
peak_gain. Default = 2.
Luma horizontal peaking control enable.
0 = Disabled (default)
1 = Enabled
3.12.23 Comb Filter Configuration Register
Address Offset:
Default Value:
82h
42h
Access:
Size:
Bit
Access
Symbol
[7]
[6]
RO
R/W
Reserved
PAL_ERR
[5]
R/W
PAL_AUTO_EN
[4]
R/W
COMB_PAL
[3:2]
[1:0]
RO
R/W
Reserved
PAL_SW_LEVEL
Read/Write
8 bits
Description
PAL error reduced.
0: disable.
1: enable.
PAL error detect enable
0: disable.
1: enable.
PAL comb filter enable.
0: disable.
1: enable.
PAL switch level.
Default = 2.
3.12.24 Comb Lock Configuration Register
Address Offset:
Default Value:
Bit
Access
[7:4]
R/W
[3:1]
R/W
[0]
R/W
83h
6Fh
Access:
Size:
Read/Write
8 bits
Symbol
Description
This
register
is
used
to
tune
the
chromakill, higher values are more
lose_chromalock_count
sensitive to losing lock
Default = 6.
lose_chromalock_level Set the level for chromakill.
Default = 7.
lose_chromalock_ckill When set, chroma is killed whenever chromlock is lost.
Default = 1.
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4 Electrical Characteristics
4.1 Digital I/O Pad Operation Condition
Table 4-1 Operation Condition
Parameter
Min
Typ
Max
Digital Core Power Supply
1.62V
1.8V
1.98V
Digital I/O Power Supply
3.0V
3.3V
3.6V
Input Low Voltage
-0.3V
0.8V
Input High Voltage
2.0V
5.0V
Schmitt Trigger Low-to-High Threshold
1.44V
1.58V
1.71V
Schmitt Trigger High-to-Low Threshold
1.09V
1.19V 1.31V
Input Leakage Current@ VI=3.3V or 0V
±1μA
Tri-state Output Leakage Current@ Vo=3.3V or 0V
±1μA
Low level Output Current@ VOL=0.4V
2mA
2.1mA
3.4mA
4.2mA
4mA
4.2mA
6.9mA
8.6mA
8mA
8.4mA 13.9mA 17.2mA
12mA
12.5mA 20.8mA 25.8mA
High level Output Current@ VOH=2.4V
IOH
2mA
3.0mA
6.2mA 10.0mA
4mA
5.7mA 11.6mA 18.6mA
8mA
9.5mA 19.4mA 30.9mA
12mA
13.3mA 27.1mA 43.3mA
Pull-up resistor
74KΩ
104KΩ 177KΩ
RPU
RPD
Pull-down resistor
62KΩ
90KΩ
176KΩ
Note: RPU and RPD are always present no matter normal operation or power down mode is enabled. A typical
30~40μA false leakage current is resulted from RPU and RPD when a tester forces I/O to 3.3V or 0.0 V.
VDD18
VD33
VIL
VIH
VT+
VT+
II
IOZ
IOL
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4.2 DC Characteristics
( VDD25=2.5V; VD33=3.3V; AVDDR=AVDDG=AVDDB=AVDDP=AVDDAC=3.3V; VREF=1.235V; RL=37.5ohm,
CL=10pF; RSET=386ohm; Temp=75oC, unless otherwise noted )
Table 4-2 DC Characteristics
Parameter
Operating
voltage
range
Operating
voltage
range
AVDDR
supply
current
AVDDG
supply
current
AVDDB
supply
current
VD33
supply
current
VDD25
supply
current
Full scale
current
Output
voltage
range
DAC
resolution
Integral
nonlinearity
error
Differential
nonlinearity
error
Gain error
DAC to
DAC
matching
Symbol
AVDDR
AVDDG
AVDDB
AVDDP
AVDDAC
VD33
Min
Typ
Max
Unit
Condition
3.0
3.3
3.6
V
VDD18
1.62
1.8
1.98
V
IAVDDR
--
35
--
mA
SL=0, SLR=0
IAVDDG
--
35
--
mA
SL=0, SLG=0
IAVDDB
--
35
--
mA
SL=0, SLB=0
IVD33
--
1
--
mA
SL=0
IVDD25
--
TBD
--
mA
IOFS
2.00
34.08
--
mA
Full-Scale adjust resistor. A resistor
should be connected between this
pin and AVS33 to control the
magnitude of the full-scale video
signal.
RSET(ohm)=VREFIN(V)*10.66/IOF
S(A)
,where IOFS is full-scale output
current.
V(IO)
--
1.28
--
V
.
--
--
10
--
bits
.
INL
--
0.5
+-2
LSB
.
DNL
--
0.5
+-1
LSB
.
---
---
-TBD
TBD
TBD
%
%
.
.
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4.3 AC Characteristics
(VDD25=2.5V; VD33=3.3V; AVDDR=AVDDG=AVDDB=AVDDP=AVDDAC =3.3V; VREF=1.235V; RL=37.5ohm;
CL=10pF; RSET=386ohm; Temp=75oC, unless otherwise noted)
Table 4-3 AC Characteristics
Parameter
CK period
CK to valid output
Output rise time
Sym
Tck
Tdelay
Tr
Min
5
---
Typ
----
Max
-0.5*Tck+2
4
Unit
Ns
Ns
Ns
Output fall time
Tf
--
--
4
Ns
Output settling time
Tsettle
--
--
TBD
Ns
Glitch energy
--
--
--
--
pvs
DAC to DAC
crosstalk
--
--
TBD
--
Db
Condition
10% to 90% IOFS;
assume no package
inductance.
90% to 10% IOFS;
assume no package
inductance.
assume no package
inductance
assume no package
inductance
.
4.4 Analog Processing and A/D Converters
Table 4-4 Analog Characteristics
Zi
Ci
Vi(pp)
△G
DNL
INL
Fr
SNR
NS
DP
DG
PARAMETER
Input impedance, analog video inputs
Input capacitance, analog video inputs
Input voltage range†
Gain control range
DC differential nonlinearity
DC integral nonlinearity
Frequency response
Signal-to-noise ratio
Noise spectrum
Differential phase
Differential gain
TEST CONDITIONS
By design
By design
Ccoupling = 0.1μF
A/D only
A/D only
6 MHz
6 MHz, 1.0 Vp-p
50% flat field
MIN
500
TYP
MAX
10
0
0
0.75
12
±0.5
±1
−0.9
−3
50
50
1.5
UNIT
kΩ
pF
V
dB
LSB
LSB
dB
dB
dB
0.5%
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4.5 I²C Host Interface Timing
Table 4-5 I2C Host Interface Timing
t1
t2
t3
t4
t5
t6
t7
t8
tLow
tHigh
fSCL
Cb
Stop
Parameter
Bus free time between a Stop and Start condition
Hold time (repeated) Start condition
Rise time of both SDA and SCL
Data hold time
Data setup time
Fall time of both SDA and SCL
Setup time for a repeated Start condition
Setup time for Stop condition
Low period of the SCL
High period of the SCL
SCL clock frequency
Capacitive load for each bus line
Min
4.7us
4.0us
Typ
Max
1000ns
5.0us
250ns
300ns
4.7us
4.0us
4.7us
4.0us
1Mhz
400pF
Stop
Start
t1
t2
tLow
t3
tHigh
t4
t6
t5
t7
t8
Figure 4-1 I2C Timing
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5 Package Dimensions
6 Ordering Information
Table 6-1 Ordering Information
Part No.
Package
T108
100 LQFP
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7 Revisions Note
Table 7-1 Revision Note
Revisions
0.1
0.2
0.3, 0.4
0.7
0.8
Description of changes
First draft
Add P0_C1h[6:4] and P0_CBh[7:0] register description
Skipped for minor modification of T108 2nd cut
Update TCON registers
Chip Change PinOut
Date
May 25, 2005
August 3, 2005
November 15, 2005
October 19, 2006
March 22, 2007
Note
8 General Disclaimer
Disclaimer
This document provides technical information for the user. The information furnished by Terawins Inc. believed to be accurate and reliable.
However, this document subject to change without any notice. The customer should make sure that they have the most recent version.
Terawins Inc. holds no responsibility for any errors that may appear in this document , and Terawins, Inc. does not assume any
responsibility for its use, nor for infringement of patents or any other rights of third parties.
Copyright Notice
This document is copyrighted by Terawins Inc. All rights are reserved.
This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine
readable form without prior written consent from Terawins, Inc.
Trademark Acknowledgment
Terawins is the Terawins Logo.
VESA is a registered trademark of Video Electronics Standards Association.
All other trademarks are the property of their respective companies.
Life Support Policy
Terawins’ products are not authorized for use within Life Support Systems without the specific written consent of Terawins, Inc.
Life support systems are systems which are intended for support or sustain life and whose failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. A critical
component in any component of a life support system whose failure to perform can be reasonably expected to cause the failure of the life
support system, or to affect its safety or effectiveness.
9 Contact Information
Taipei Main Office
4F-6, No.716, Chung-Cheng Road,
Chung-Ho City, Taipei Hsien,
Taiwan
Tel:
Fax:
Email:
Web:
(02) 8227-8277
(02) 8227-8333
[email protected]
www.terawins.com
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