Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 Features: Description • Vcc operation voltage : 2.0V ~ 3.6V • Low power consumption : 10mA (Max.) operating current 0.1uA (Typ.) CMOS standby current • High Speed Access time : 35ns (Max.) at Vcc = 2.7V 55ns (Max.) at Vcc = 2.7V 70ns (Max.) at Vcc = 2.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Data retention supply voltage as low as 1.2V • Easy expansion with CE\ and OE\ options The UC62LV0256 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates from a wide range of 2.0V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1uA and maximum access time of 70ns in 2.0V operation. Easy memory expansion is provided enable (CE), and active LOW output enable (OE) and three-state output drivers. The UC62LV0256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The UC62LV0256 is available in the JEDEC standard 28 pin 330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and 8mmx13.4mm TSOP (normal type). PRODUCT FAMILY Product Family Operating Temperature UC62LV0256BC UC62LV0256CC UC62LV0256DC UC62LV0256EC UC62LV0256AC UC62LV0256BI UC62LV0256CI UC62LV0256DI UC62LV0256EI UC62LV0256AI Vcc Range Speed (ns) Vcc=2.7V 2.0V ~ 3.6V -35/ -55/ -70 0.1uA 17mA 13mA 10mA -25℃ ~ 85 2.0V ~ 3.6V -35/ -55/ -70 0.1uA 17mA 13mA 10mA ROW Address COL Address SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE MEMORY ARRAY 32K X 8 Bits COLUMN DECODER CE WE OE CONTROL BLOCK CE WE OE CONTROL INPUT BUFFER SENSE AMPLIFIER & WRITE DRIVER X8 I/O BUFFER DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 UC62LV0256CC UC62LV0256CI VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 ROW DECODER UC62LV0256BI UC62LV0256DI UC62LV0256EI UC62LV0256BC UC62LV0256DC UC62LV0256EC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ADDRESS INPUT BUFFER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Package Type BLOCK DIAGRAM A0 - A14 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 Power Consumption VCC=3.6V Operating (Max) 35ns 55ns 70ns 0℃ ~ 70℃ PIN CONFIGURATIONS A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND STANDBY Vcc=3.0V 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 1 Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 PIN DESCRIPTION Name Type Function A0 – A14 Input Address inputs for selecting one of the 32768 x 8 bit words in the RAM CE\ Input CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip enable is not active, the device is deselected and not in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. WE\ Input The Write enable input is active LOW and controls read and write operations. With the chip selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when WE\ is LOW, the data present on the DQ pins will be written into the selected memory location. OE\ Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE\ is inactive. DQ0 – DQ7 I/O Vcc Power Power Supply Gnd Power Ground These 8 bi0directional ports are used to read data from or write data into the RAM. TRUTH TABLE Mode WE\ CE\ OE\ I/O state Vcc Current Not Selected X H X High Z ISB,ISB1 Output Disabled H L H High Z ICC Read H L L DOUT ICC Write L L X DIN ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER VTERM Terminal Voltage with Respect to GND TBIAS Temperature Under Bias TSTG Storage Temperature RATING -0.5 to VCC+0.5 OPERATING RANGE UNIT RANGE V Commercial -40 to 125 ℃ Industrial -50 to 150 ℃ PT Power Dissipation 50mW W IOUT DC Output Current 10 mA 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AMBIENT TEMPERATURE VCC 0℃ to 70℃ 2.0V~ 3.6V -25℃ to 85℃ 2.0V ~ 3.6V CAPACITANCE(1)(TA=25℃,f=1.0MHz) SYMBOL PARAMETER CONDITIONS MAX. UNIT Input VIN=0V 6 pF CIN Capacitance Input/Output VDQ 8 pF CDQ Capacitance 1. This parameter is guaranteed and not 100% tested. U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 2 Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 DC ELECTRICAL CHARACTERISTICS (TA=-25℃ to 85℃ , VCC=2.0V to 3.6V) Symbol MIN. TYP.(1) MAX. UNITS VCC=2.7V -0.5 - 0.8 V VCC=3.6V 2.0 - Vcc-0.2 V Test Condition Comment VIH Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage IL Input Leakage Current VCC=3.6V VIN=0V to VCC - - 1 uA IOL Output Leakage Current VCC=3.6V CE\=VIH or OE\=VIH VIO=0V t VCC - - 1 uA VOL Output Low Voltage VCC=3.6V, IOL=2 mA - - 0.4 V VOH Output High Voltage VCC=3.0V, IOH=-1 mA 2.4 - - V ICC Operating Power Supply Current CE\=VIL,IDQ=0mA, F=Fmax - - 10 mA ISB1 TTL Standby Current CE\=VIH, VIN=VIH to VIL - - 1 mA CMOS Standby Current CE\≧VCC-0.2V, VIN=VCC-0.2V to 0.2V - 0.1uA 1 uA VIL ISB2 (3) 1. Typical characteristics are at TA = 25℃. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC, tRC=70ns . DATA RETENTION CHARACTERISTICS ( TA=0℃ to 70℃) Symbol Comment VDR VCC to Data Retention ICCDR Data Retention Current tDR Chip Deselect to Data Retention Time tR Test Condition CE\≧VCC - 0.2V VIN≧VCC-0.2V or VIN≦0.2V CE\≧VCC - 0.2V VIN≧VCC-0.2V or VIN≦0.2V VCC = 1.5V, TA = 25℃. 2. tRC = Read Cycle Time (1) TYP. MAX. UNITS 1.2 - - V - 0.05 0.5 uA - - ns - - ns 0 See Retention Waveform Operation Recovery Time 1. MIN. TRC (2) LOW VCC DATA RETENTION WAVEFORM(1) (CE\ Controlled) Vcc CE tCDR VIH Data Retention Mode VDR >= 1. 2V CE >= VCC - 0. 2V U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. tR VIH Revision 2.0 PAGE 3 Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level VCC/0V 1V/ns 0.5VCC WAVEFORMS INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON’T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE AC TEST LOADS AND WAVEFORMS 3.3V 3.3V 1269Ω INCLUDING JIG AND SCOPE 1269Ω INCLUDING JIG AND SCOPE 5pF 100pF 1404Ω OUTPUT 1404Ω OUTPUT FIGURE 1A FIGURE 1B TERMINAL EQUIVALENT 667Ω OUTPUT 1.73V ALL INPUT PULSES VCC GND 90% 90% 10% 10% FIGURE 2 5ns 5ns AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=3.0V) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION tAVAX tRC Read Cycle Time tAVQV tAA tELQV UC62LV0256-35 UC62LV0256-70 Min Typ Max Min Typ Max 35 - - 70 - - ns Address Access Time - - 35 - - 70 ns tCE Chip Select Access Time - - 35 - - 70 ns tGLQV tOE Output Enable to Output Valid - - 15 - - 50 ns tELQX tCLZ Chip Select to Output Low Z 5 - - 10 - - ns tGLQX tOLZ Output Enable to Output Low Z 5 - - 10 - - ns tEHQZ tCHZ Chip Deselect to Output in High Z 0 - 35 0 - 35 ns tGHQZ tOHZ Output Disable to Output in High Z 0 - 20 0 - 30 ns tAXOX tOH Address Chang to Output Change 10 - - 10 - - ns U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. UNIT Revision 2.0 PAGE 4 Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) tRC ADDRESS tAA tOH tOH DOUT READ CYCLE2 (1,3,4) CE tCLZ (5) tCE tCHZ (5) DOUT READ CYCLE3 (1,4) tRC ADDRESS tAA tOH OE tOE tOHZ (1,5) tOLZ CE tCLZ (5) tCE tCHZ (5) DOUT NOTES: 1. WE\ is high in read cycle. 2. Device is continuously selected when CE\ = VIL 3. Address valid prior to or coincident with CE\ transition low. 4. OE\ = VIL. 5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 5 Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=3.0V) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION tAVAX tWC tE1LWH UC62LV0256-35 UC62LV0256-70 Min Typ Max Min Typ Max Write Cycle Time 35 - - 70 - - ns tCW Chip Select to END of Write 35 - - 70 - - ns tAVWL tAS Address Setup Time 0 - - 0 - - ns tAVWH tAW Address valid to End of Write 35 - - 70 - - ns tWLWH tWP Write Pulse Width 20 - - 50 - - ns tWHAX tWR Write Recovery Time 0 - - 0 - - ns tWLOZ tWHZ Write to Output in High Z - - 15 - - 30 ns tDVWH tDW Data to Write Time Overlap 15 - 40 - tWHDX tDH Data Hold Time for Write End 0 - - 0 - - ns tGHOZ tOHZ Output Disable to Output In High Z 0 - 15 0 - 30 ns tWHQX tOW End of Write to Output Active 5 - - 5 - - ns UNIT ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITECYCLE1(1) tWC ADDRESS tAW OE tCW(11) CE tAS (4,10) tWP(2) WE tOHZ DOUT tDW tDH DIN U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 6 Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 WRITE CYCLE2(1,6) tWC ADDRESS tAW tCW(11) CE tAS tWP(2) WE tWHZ tOH DOUT (7) tDW (8) tDH DIN NOTES: 1. WE\ must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals must be active to initiate a write and any one can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\ transition, output remain in a high impedance state. 6. OE\ is continuously low (OE\ = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 7 Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 ORDERING INFORMATION UC62LV0256AB -- YY A => PACKAGE A : DICE B : 28 SOP – 330mil C : 28 TSOP – 8X13.4mm D : 28 PDIP – 600mil E : 28 SOJ – 300mil B => GRADE C :COMMERCIAL; 0 ~ 70℃ I : INDUSTRIAL; -25 ~ 85℃ YY => SPEED 70 : 70ns 55 : 55ns 35 : 35ns PACKAGE DIMENSIONS 28 15 0.020±0.005X45" E E1 "A" 1 14 A b e INCH MM A A1 0.106±0.006 0.009±0.005 2.692±0.152 0.226±0.124 A2 b 0.098±0.005 0.014 ~ 0.020 2.489±0.127 0.35 ~ 0.50 b1 c 0.014 ~ 0.020 0.008 ~ 0.012 0.35 ~ 0.45 0.20 ~ 0.32 c1 D 0.008 ~ 0.011 0.713±0.005 0.20 ~ 0.28 18.110±0.127 E 0.331±0.005 8.407±0.127 E1 e 0.465±0.012 0.050±0.006 11.811±0.305 1.270±0.152 L1 L L1 0.0380±0.0104 0.0677±0.0079 0.964±0.264 1.72±0.2 DETAIL "A" (2:1) y θ 0.004 Max. 0° ~ 10° 0.1 Max. 0° ~ 10° D θ A L 7°(4X) b A A2 UNIT SYMBOL Seating Plane "y" A1 WITH PLATING c c1 BASE METAL SOP - 28 b1 SECTION A-A U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 8 Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 PACKAGE DIMENSIONS (continued) 12°(2X) 12°(2X) e 1 b E HD 28 SEATING PLANE 14 12°(2X) 15 GAUGE PLANE "A" A A A2 D A1 θ A 12°(2X) 14 L L1 SEATING PLANE 15 0.254 UNIT SYMBOL INCH MM A A1 0.0433±0.004 0.0045±0.0026 1.10±0.10 0.226±0.124 A2 b 0.039±0.002 0.009±0.020 1.00±0.05 0.22± 0.05 b1 c 0.008± 0.001 0.004 ~ 0.008 0.20± 0.03 0.10 ~ 0.21 c1 D 0.004 ~ 0.006 0.465±0.004 0.10 ~ 0.16 11.80±0.10 E e 0.315±0.004 0.22±0.004 8.00±0.10 0.55±0.10 HD L 0.528±0.008 0.0197±0.008 13.40±0.20 0.50±0.20 L1 y θ 0.0315±0.004 0.004 Max. 0.80±0.10 0.1 Max. 0° ~ 8° 0° ~ 8° "A" DETAIL VIEW b WITH PLATING c c1 28 1 BASE METAL b1 SECTION A-A TSOP - 28 D S B B1 e UNIT SYMBOL INCH(BASE) MM A1 A2 0.010(MIN) 0.150±0.005 0.254(MIN) B B1 0.018±0.005 0.060±0.010 c D 0.010±0.004 0.146±0.005 E E1 0.600±0.010 0.544±0.004 e eB 0.100(TYP) 0.640±0.020 L S 0.130±0.010 0.080±0.010 0.070±0.005 Q1 θ 6° ± 3° 3.810±0.127 0.457±0.127 1.524±0.254 0.254±0.102 37.084±0.127 15.240±0.254 13.818±0.102 2.540(TYP) 16.256±0.508 3.302±0.254 2.032±0.254 1.778±0.127 6° ± 3° E L c Q1 A2 5° ~ 7° A1 5° ~ 7° E1 eB θ PDIP - 28 U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 9 Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 PACKAGE DIMENSIONS (continued) 28 Nom Max Min Nom Max A A1 -0.027 --- 0.140 -- -0.69 --- 0.140 -- A2 b1 0.095 0.026 0.1 0.028 0.105 0.032 2.41 0.66 2.54 0.71 2.67 0.81 b c 0.016 0.008 0.018 0.010 0.022 0.014 0.41 0.20 0.46 0.25 0.56 0.36 D E -0.295 0.710 0.300 0.730 0.305 -7.49 18.03 7.62 18.54 7.75 e e1 0.044 0.245 0.050 0.265 0.056 0.285 1.12 6.22 1.27 6.73 1.42 7.24 HE L 0.327 0.077 0.337 0.087 0.347 0.097 8.31 1.96 8.56 2.21 8.81 2.46 S y θ --- --- 0.045 0.004 --- --- 1.14 0.10 0° -- 10° 0° -- 10° E E1 14 b b1 e SOJ - 28 A1 L A A2 c D S Seating Plane MM Min 15 1 INCH UNIT SYMBOL e1 Note: 1. Dimension D Max & s include mold flash or tie bar burns. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch and are determined at the mold parting line. 4. Controlling dimension: Inch 5. General appearance spec. should be based on final visual inspection spec. U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 10