TPS65562 www.ti.com SLVS775 – JUNE 2007 INTEGRATED PHOTO FLASH CHARGER AND IGBT DRIVER FEATURES APPLICATIONS • • • • • • • • • • • • • • High Integrated Solution to Reduce Components Integrated Voltage Reference Integrated 50-V Power Switch Integrated Insulated Gated BiPolar Transistor (IGBT) Driver High Efficiency Programmable Peak Current, 0.9 A ~ 1.8 A Input Voltage of 1.6 V to 12 V Optimized Control Loop for Fast Charge Time Isolate IGBT VCC from VCC Output Voltage Feedback From Primary Side 16-pin QFN Package Protection – MAX On Time – MAX Off Time – Over Current Shutdown to Monitor VDS at SW Pin (OVDS) – Thermal Disable Digital Still Cameras Optical Film Cameras DESCRIPTION/ORDERING INFORMATION This device offers a complete solution for charging photo flash capacitor from battery input, and subsequently discharging the capacitor to a xenon flash tube. This device has an integrated voltage reference, power switch, IGBT driver, and control logic blocks for charging applications and driving IGBT application. Compared with discreet solutions, this device reduces the component count, shrinks the solution size, and eases designs for xenon tube application. Additional advantages are a fast charging time and high efficiency from an optimized pulse width modulation (PWM) control algorithm. Other provisions of the device includes sensing the output voltage from the primary side, programmable peak current, thermal shutdown, an output pin for charge completion, and input pins for charge enable and flash enable. VA T1 VCC IGBT_VCC VCC IGBT_VCC VBAT D1 VOUT C1 SW VI/F VI/F CHG DQ F1 Controller R1 XFULL or OVDS DQ F2 ENA VCC U1 ENA U0 V_FULL D/A Conv. or U2 MAX ON TSD I_PEAK LOGIC PGND I_PEAK ref Analog Circuit SW Vref U3 IGBT_VCC or F_ON ENA G_IGBT U4 SW1 IGBT (NC) Figure 1. Typical Application Circuit Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPS65562 www.ti.com SLVS775 – JUNE 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGE (1) TA –35°C to 85°C (1) CAH ORDERABLE PART NUMBER 16-pin QFN TOP-SIDE MARKING TPS65562RGT Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT Supply voltage VCC, IGBT_VCC –0.6 to 6 VBAT –0.6 to 13 V VSW Switch terminal voltage ISW Switch current between SW and PGND VI Input voltage of CHG, I_PEAK, F_ON –0.3 to VCC V Tstg Storage temperature –40 to 150 °C TJ Maximum junction temperature ESD rating (1) HBM (Human Body Model) JEDEC JES22-A114 –0.6 to 50 V 3 A 125 °C 1 kV Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN MAX Supply voltage UNIT VCC 2.7 4 IGBT_VCC 2.7 5.5 1.6 12 –0.3 45 V 2 A 85 °C VBAT VSW Switch terminal voltage ISW Switch current between SW and PGND Operating free-air temperature range –35 VIH High-level digital input voltage at CHG and F_ON VIL Low-level digital input voltage at CHG and F_ON 2 V V 0.5 V DISSIPATION RATINGS (1) 2 PACKAGE RθJA (1) POWER RATINGS TA < 25°C POWER RATINGS RATE TA = 70°C POWER RATINGS RATE TA = 85°C QFN 47.4°C/W 2.11 W 1.16 W 844 mW The thermal resistance, RθJA, is based on a soldered PowerPAD™ package on 2S2P JEDEC board using thermal vias. Submit Documentation Feedback TPS65562 www.ti.com SLVS775 – JUNE 2007 ELECTRICAL CHARACTERISTICS TA = 25°C, VBAT = 4.2 V, VCC = 3 V, IGBT_VCC = 3 V, V(SW) = 4.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS RONL ON resistance of XFULL IXFULL = –1 mA VPKH (1) Upper threshold voltage of I_PEAK VCC = 3 V (1) VPKL MIN TYP MAX 1.5 3 2.4 UNIT kΩ V Lower threshold voltage of I_PEAK VCC = 3 V 0.6 V ICC1 Supply current from VBAT CHG = H, VSW = 0 V (free run by tMAX) 17 50 μA ICC2 Supply current from VCC CHG = H, VSW = 0 V (free run by tMAX) 1.3 3 mA ICC3 Supply current from VCC and VBAT CHG = L 1 μA ILKG1 Leakage current of SW terminal 2 μA ILKG2 Leakage current of XFULL terminal 1 μA Isink Sink current at I_PEAK RONSW SW ON resistance between SW and PGND ISW = 1 A, VCC = 3 V RIGBT1 G_IGBT pull up resistance VG_IGBT = 0 V, IGBT_VCC = 3 V RIGBT2 G_IGBT pull down resistance VG_IGBT = 3 V, IGBT_VCC = 3 V 36 IPEAK1 Upper peak of ISW VI_IPEAK = 3 V 1.58 IPEAK2 Lower peak of ISW VI_IPEAK = 0 V 0.7 VFULL Charge completion detect voltage at V(SW) VBAT = 1.6 V, VCC = 3 V VCC = 3 V VZERO Zero current detection at VSW TSD (1) OVDS TMIX VXFULL = 5 V VI_PEAK = 3 V, CHG: High 2 VI_PEAK = 3 V, CHG: Low 0.1 μA 0.4 0.9 Ω 12 19.4 Ω 53 70 Ω 1.68 1.78 A 0.8 0.9 A 28.0 28.7 29.4 V 28.6 29.0 29.4 1 20 60 mV Thermal shutdown temperature 150 160 170 °C Over current detection at VSW 0.95 1.2 1.45 V MAX OFF time 25 50 80 μs TMAX MAX ON time 50 100 160 μs RINPD Pull down resistance of CHG, F_ON (1) 8 VCHG = VF_ON = 4.2 V 100 V kΩ Specified by design SWITCHING CHARACTERISTICS TA =25°C, VBAT = 4.2 V, VCC = 3 V, IGBT_VCC = 3 V, VSW =4.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS F_ON↑↓ G_IGBT↑↓ tPD (1) (1) Propagation delay MIN TYP MAX UNIT 50 ns SW ON after VSW dips from VZERO 500 ns SW OFF after ISW exceeds IPEAK 270 ns XFULL↓ after VSW exceeds VFull 400 ns SW ON after CHG↑ 12 μs SW OFF after CHG↓ 20 ns Specified by design Submit Documentation Feedback 3 TPS65562 www.ti.com SLVS775 – JUNE 2007 NC TEST_GND NC VBAT QFN PACKAGE (TOP VIEW) 16 15 14 13 VCC 3 F_ON 4 Power PAD 11 PGND 10 CHG XFULL 9 5 6 7 8 IGBT_VCC 2 PGND NC SW 12 I_PEAK 1 G_IGBT SW TERMINAL FUNCTIONS TERMINAL NAME I/O DESCRIPTION SW 1, 2 O Primary side switch. Connect SW to the switched side of the transformer VCC 3 I Power supply input. Connect VCC to an input supply from 2.7 V to 4.0 V. Bypass VCC to GND with a 1 μF ceramic capacitor as close as possible to the IC. F_ON 4 I G_IGBT control input. Drives F_ON with the flash discharge signal. A logic high on F_ON drives G_IGBT high when CHG is Low. See the IGBT driver control section for details. I_PEAK 5 I Primary side Peak current control input. The voltage at I_PEAK sets the peak current into SW. See the Programming Peak Current section for details on selecting VI_PEAK. G_IGBT 6 O IGBT gate driver output. G_IGBT swings from PGND to VCC to drive external IGBT devices. NC 7, 13, 16 No internal connection IGBT_VCC 8 I Power supply input for IGBT Driver output. Connect IGBT_VCC to an input supply from 2.7 V to 5.5 V. XFULL 9 O Charge completion indicator output. XFULL is an open-drain output that pulls low once the output is fully charged. XFULL is high impedance during charging and all fault conditions. XFULL is reset when CHG turns Low from High. See the Indicating Charging status section for details. CHG 10 I Charge control input. Drive CHG high to initiate charging of the output. Drive CHG low to terminate charging. PGND 4 NO. 11, 12 TEST_GND 14 VBAT 15 Power ground. Connect to the ground plane. Used by TI, should be connected to PGND and ground plane. I Battery voltage monitor input. Connect VBAT to an input supply from 1.6 V to 12 V. Bypass VBAT to GND with a 10 μF ceramic capacitor (C1 in Figure 1 as close as possible to the battery) and a 1 μF ceramic capacitor (C2 in Figure 1, as close as possible to the IC). It is no problem to input VBAT before VCC input. Submit Documentation Feedback TPS65562 www.ti.com SLVS775 – JUNE 2007 VBAT VCC SW IGBT_VCC DQ CHG F1 XFULL OVDS DQ F2 ENA VCC U1 ENA U0 V_FULL MAX ON U2 TSD I_PEAK LOGIC I_PEAK ref PGND SW Vref U3 IGBT_VCC ENA F_ON G_IGBT U4 (NC) Figure 2. Block Diagram Submit Documentation Feedback 5 TPS65562 www.ti.com SLVS775 – JUNE 2007 I/O Equivalent Circuits CHG, F_ON SW I_PEAK XFULL VBAT G_IGBT Figure 3. I/O Equivalent Circuits 6 Submit Documentation Feedback TPS65562 www.ti.com SLVS775 – JUNE 2007 PRINCIPLES OF OPERATION ~ CHG ~ (VOUT) XFULL ~ F_ON ~ G_IGBT ~ (ENA) ~ eA tim eB tim eC tim tim eD tim eE tim eF eG tim eH tim tim eI tim eJ Figure 4. Whole Operation Sequence Chart Start/Stop Charging TPS65562 has one internal enable latch, F1, that holds the charge enable (ON/OFF status) of the device (see Figure 4). The only way to start charging is to input CHG↑ (see time A/C/H in Figure 4). Each time CHG↑ is applied, the TPS65562 starts charging. There 1. 2. 3. are three trigger events to stop charging: Forced stop by inputting CHG = L from the controller (see timeB in Figure 4). Automatic stop by detecting a full charge. VOUT reaches the target value (see TimeD in Figure 4). Protected stop by detecting an overcurrent function (OVDS) trigger at SW pin (see TimeI in Figure 4). Indicate Charging Status When the charging operation is complete, the TPS65562 drives the charge completion indicator pin, XFULL, to GND. A controller can detect the status of the device as a logic signal when connected through a pullup resister, R1 (see Figure 1). The XFULL output enables the controller to detect the OVDS protection status. If OVDS protection occurs, XFULL never goes L during CHG = H. Therefore, the controller detects OVDS protection by measuring the time from CHG high to XFULL low. If the time to XFULL low is longer than the maximum designed charge time, then an OVDS protection occurred. The device starts charging at timeH, and OVDS protection occurs at TimeI (see Figure 5). At TimeI, XFULL stays H. At TimeJ, the controller detects OVDS protection through the expiration of a timer ends and then sets CHG to low to terminate the operation. Submit Documentation Feedback 7 TPS65562 www.ti.com SLVS775 – JUNE 2007 ~ ~ ~ ~ ~ ~ Logic PRINCIPLES OF OPERATION (continued) CHG OFF SW ON OFF XFULL SW VSW OFF ON OFF OFF ON OFF VZERO V VFULL V SW VBAT ~ 0[V] ~ V SW VOUT ~ VA ~ V BAT V 0[V] ~ V V BAT VOUT VA 0[V] V OUT ~ V 0[V] ~ ~ VA ISW I IPEAK I I 0[A] IPEAK ~ 0[A] ISW IOUT I IPEAK /NTRUN IOUT time3 time4 time5 time2 Figure 5. Timing Diagram at One Switching IPEAK /NTRUN IOUT ~ T ~ 0[A] time1 ~ ISW 0[A] T Figure 6. Timing Diagram at Beginning/Ending Control Charging The TPS65562 provides three comparators to control charging. Figure 2 shows the block diagram of TPS65562, and Figure 5 shows a timing diagram of one switch cycle. Note that emphasis is placed on Time1 and Time3 of the waveform in Figure 5. While SW is ON (Time1 to Time2 in Figure 5), U3 monitors current flow through the integrated power switch from SW pin to GND. When I(SW) exceeds I(PEAK), SW turns OFF (Time2 in Figure 5). When SW turns OFF (Time2 in Figure 5), the magnetic energy in the transformer starts discharging. Meanwhile, U2 monitors the kickback voltage at the SW terminal. As the energy is discharging, the kickback voltage is increasing according to the increase of VO (Time2 to Time3 in Figure 5). When almost all energy is discharged, the system cannot continue rectification via the diode, and the charging current of IO goes to zero (Times3 in Figure 5). After rectification stops, the small amount of energy left in the transformer is released via parasitic paths, and the kickback voltage reaches zero (Time3 to Time4 in Figure 5). During this period, U2 makes SW turn ON when (V(SW) - VBAT) dips from V(ZERO) (Time5 in Figure 5). In the actual circuit, the period between Time4 and Time5 in Figure 5 is small or does not appear dependent on the delay time of the U2 detection to SW ON. U1 also monitors the kickback voltage. When (V(SW) - VBAT) exceeds V(FULL), the TPS65562 stops charging (see Figure 6). In Figure 5 and Figure 6, ON time is always the same period in every switch cycle. The ON time is calculated by Equation 1. L and IPEAK are selected to ensure that tON does not exceed the MAX ON time (tMAX). I TON = L PEAK VBAT (1) The OFF time is dependant on output voltage. As the output voltage gets higher, the OFF time gets shorter (see Equation 2). 8 Submit Documentation Feedback TPS65562 www.ti.com SLVS775 – JUNE 2007 PRINCIPLES OF OPERATION (continued) TOFF I = NTURN ´ L PEAK VOUT (2) Programming Peak Current The TPS65562 provides a method to program the peak primary current with a voltage applied to the I_PEAK pin. Figure 7 shows how to program IPEAK. The I_PEAK input is treated as a logic input below VPKL (0.6 V) and above VPKH (2.4 V). Between VPKL and VPKH, I_PEAK input is treated as an analog input. Using this characteristic, IPEAK can be set by a logic signal or by an analog input. Typical usages of this function are: 1. Setting the peak charging currents based on the battery voltage. Larger IPEAK for a fully charged battery and lower IPEAK for a discharged battery. 2. Reducing IPEAK when powering a zooming lens motor. This avoids inadvertent shutdowns due to large current from the battery. In Figure 1, three optional connections to I_PEAK are shown. 1. Use the controller to treat I_PEAK as the logic input pin. This option is the easiest. 2. Use a D/A converter to force IPEAK to follow analog information, such as battery voltage. 3. Use an analog circuit to achieve the same results as the D/A converter. Figure 7. I_PEAK vs ISW IGBT Driver Control The IGBT driver is provided by the TPS65562. The driver voltage depends on VCC. TPS65562 has a mask filter as shown in Figure 8. The mask does not have hysteresis; therefore, there is no wait time from CHG forcing Low after FULL CHARGE to F_ON turning High. Submit Documentation Feedback 9 TPS65562 www.ti.com SLVS775 – JUNE 2007 PRINCIPLES OF OPERATION (continued) Figure 8. Relationships Between F_ON and CHG Protections TPS65562 provides four protection mechanisms: max on time, max off time, thermal disable, and over current shutdown. MAX ON TIME To prevent a condition such as pulling current from a poor power source (i.e., an almost empty battery), and never reaching peak current, the TPS65562 provides a maximum ON time function. If the ON time exceeds tMAX, the TPS5562 is forced OFF regardless of IPEAK detection. MAX OFF TIME To prevent a condition such as never increasing the voltage at the SW pin when the internal FET is OFF, the TPS65562 provides a maximum OFF time function. If the OFF time exceeds tMIN, the TPS65562 is forced ON regardless of VZERO detection. THERMAL DISABLE Once the die temperature of the TPS65562, reaches 160°C, all functions stop. Once the die cools below 160°C, the TPS65562 restarts charging if CHG remains high during the entire over temperature condition. OVER CURRENT SHUTDOWN The TPS65562 provides an over voltage monitor function of the SW pin. The TPS65562 is latched off if the voltage on the SW pin is above OVDS during the switch ON time (see Figure 4 and its descriptions). This function protects against short-circuits on the primary side of the transformer. A short-circuit of the primary side shorts the battery voltage to GND. SW pin can damage the device if not protected. 10 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 13-Nov-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS65562RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65562RGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65562RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65562RGTTG4 ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65562RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS65562RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65562RGTR QFN RGT 16 3000 367.0 367.0 35.0 TPS65562RGTT QFN RGT 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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