TPS714xx SBVS116C – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com 80mA, 10V, 3.2μA Quiescent Current LOW-DROPOUT LINEAR REGULATOR in SC70 or SON 2x2 FEATURES DESCRIPTION • • • • • • The TPS714xx low-dropout (LDO) voltage regulators offer the benefits of wide input voltage range, low-dropout voltage, low-power operation, and miniaturized packaging. These devices, which operate over an input range of 2.5V to 10V, are stable with any capacitor ≥ 0.47μF. The 2.5V to 10V input voltage range, combined with 3.2μA quiescent current, makes this device particularly well-suited for two-cell alkaline, and two-cell lithium, and other low quiescent current sensitive battery applications. The low dropout voltage and low quiescent current allow operation at extremely low power levels. Therefore, the devices are ideal for power battery management ICs. Specifically, because the device is enabled as soon as the applied voltage reaches the minimum input voltage, the output is quickly available to power continuously-operating, battery-charging ICs. 1 2 • • • • Wide Input Voltage Range: 2.5V to 10V Low Quiescent Current: 3.2μA at 80mA Stable with any Capacitor > 0.47μF Output Current: 80mA Dropout Voltage: 415mV at 50mA Load Available in Fixed 3.3V or Adjustable (1.2V to 8.8V) Versions Current Limit SC70-5 and 2mm x 2mm SON-6 Packages Specified Junction Temperature Range: –40°C to +125°C For MSP430-Specific Output Voltages, see the TPS715xx APPLICATIONS • • • • The typical PNP pass transistor has been replaced by a PMOS pass element. Because the PMOS pass element behaves as a low-value resistor, the low dropout voltage (typically 415mV at 50mA of load current) is directly proportional to the load current. The quiescent current (3.2μA, typical) is stable over the entire range of the output load current (0mA to 80mA). Ultralow-Power Microcontrollers Industrial/Automotive Applications PDAs Portable, Battery-Powered Equipment The TPS714xx is available in a 2mm x 2mm SON-6 package ideal for high power dissipation, or an SC70-5 package ideal for handheld and ultra-portable applications. DCK PACKAGE SC70-5 (TOP VIEW) DRV PACKAGE 2mm x 2mm SON (TOP VIEW) NC 2 GND 3 6 OUT GND IN 1 5 NC 4 FB/NC FB/NC 1 GND 2 NC 3 IN 5 OUT 4 IN TPS71433 OUT GND MSP430 9V 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2011, Texas Instruments Incorporated TPS714xx SBVS116C – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) PRODUCT XX is nominal output voltage (for example 33 = 3.3V, 01 = Adjustable) YYY is Package Designator Z is Package Quantity TPS714xxyyyz (1) (2) (2) VOUT For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Custom output voltages are available on a quick-turn basis for prototyping. Production quantities are available; minimum package order quantities apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS Over operating temperature range, unless otherwise noted. (1) PARAMETER TPS714xx UNIT VIN range –0.3 to +24 V VOUT range - 0.3 to +9.9 V -0.3 to +4 V V FB range Peak output current Internally limited Continuous total power dissipation See Power Dissipation Rating table Junction temperature range, TJ –40 to +125 °C Storage temperature range –65 to +150 °C 2 kV 500 V Human body model (HBM) ESD rating (1) Charged device model (CDM) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POWER DISSIPATION RATING TABLE BOARD PACKAGE RθJA°C/W DERATING FACTOR ABOVE TA = +25°C TA ≤ 25°C POWER RATING High-K (1) DCK 315 3.18mW/°C 320mW 175mW 100mW High-K (1) DRV 65 15.4mW/°C 1.54W 850mW 0.62W (1) 2 TA = +70°C POWER TA = +85°C POWER RATING RATING The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated TPS714xx SBVS116C – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS Over the operating junction temperature range (TJ = –40°C to +125°C), VIN = VOUT(NOM) + 1V, IOUT = 1mA, and COUT = 1μF, unless otherwise noted. The adjustable version is tested with VOUT = 2.8V. Typical values are at TJ = +25°C. TPS714xx PARAMETER TEST CONDITIONS 2.5 10 3 10 VFB 8.8 Output voltage range (TPS71401) VOUT Internal reference (TPS71401) VFB Output voltage accuracy (1) TPS71433 over VIN, IOUT, and Temp 4.3V < VIN < 10V, 1mA ≤ IOUT ≤ 80mA Output voltage line regulation (1) ΔVOUT/ΔVIN VOUT + 1V < VIN ≤ 10V Load regulation ΔVOUT/ΔIOUT IOUT = 1mA to 80mA Feedback pin bias current IFB IOUT = 0mA, VIN = 3V to 10V, VOUT = 1.2V, Dropout voltage VDO IOUT = 80mA, VIN = VOUT(NOM) – 0.1V Output current limit ICL VOUT = 0V IGND 1.12 1.20 1.24 3.135 3.3 3.465 670 nA 1300 mV 1100 mA 1mA ≤ IOUT ≤ 80mA 3.2 5.8 VIN BW = 200Hz to 100kHz, COUT = 10μF, IOUT = 50mA V mV 4.2 Output noise voltage V 2 3.2 f = 100kHz, COUT = 10μF V 30 100 PSRR V mV TJ = –40°C to +85°C, 1mA ≤ IOUT ≤ 80mA Power-supply ripple rejection UNIT 5 VIN = 10V, 1mA ≤ IOUT ≤ 80mA (1) MAX IOUT = 80mA VIN Ground pin current TYP IOUT = 10mA Input voltage range (1) BIAS MIN μA 7.4 60 dB 575 μVrms Minimum VIN = VOUT + VDO, or the value shown for Input voltage, whichever is greater. PIN CONFIGURATION DRV PACKAGE SON-6 (TOP VIEW) NC 2 GND 3 6 OUT GND IN 1 DCK PACKAGE SC70-5 (TOP VIEW) 5 NC FB/NC 1 GND 2 NC 3 5 OUT 4 IN 4 FB/NC Table 1. Pin Descriptions TPS714xx DCK NAME DRV FIXED ADJ. FIXED FB/NC - 1 - 4 GND 2 2 3, Pad 3, Pad NC 1,3 3 2, 4, 5 2, 5 IN 4 4 1 1 Unregulated input voltage. OUT 5 5 6 6 Regulated output voltage. Any output capacitor ≥ 0.47μF can be used for stability. Copyright © 2008–2011, Texas Instruments Incorporated ADJ. DESCRIPTION Adjustable version only. This pin is used to set the output voltage. Ground No connection. May be left open or tied to ground for improved thermal performance. Submit Documentation Feedback 3 TPS714xx SBVS116C – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAMS VIN VOUT Current Sense ILIM R1 GND FB R2 Bandgap Reference VREF = 1.205V Figure 1. Adjustable Voltage Version VIN VOUT Current Sense ILIM R1 GND R2 840kW Bandgap Reference VREF = 1.205V Figure 2. Fixed Voltage Version 4 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated TPS714xx SBVS116C – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. TPS71433 OUTPUT VOLTAGE vs OUTPUT CURRENT 3.465 3.399 3.366 3.333 3.300 3.267 3.234 3.201 3.168 3.399 3.366 3.333 IOUT = 10mA 3.300 3.267 3.234 IOUT = 80mA 3.201 3.168 3.135 10 20 30 40 50 60 70 80 -40 -25 -10 5 20 35 50 65 80 95 110 125 4.0 3.5 3.0 2.5 2.0 -40 -25 -10 5 TJ - Junction Temperature - °C IOUT - Output Current - mA Figure 4. Figure 5. TPS71433 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS71433 OUTPUT IMPEDANCE vs FREQUENCY TPS71433 DROPOUT VOLTAGE vs OUTPUT CURRENT 18 IOUT = 1mA IOUT = 50mA 4 3 2 1 1000 VIN = 4.3V VOUT = 3.3V COUT = 1mF TJ = +25°C 16 ZO - Output Impedance - W VIN = 4.3V VOUT = 3.3V COUT = 1mF 6 5 14 10 8 6 IOUT = 1mA 4 VIN = 4.3V 900 12 2 TJ = +125°C 800 700 600 TJ = +25°C 500 400 300 200 TJ = -40°C 100 0 IOUT = 50mA 0 0 0 100 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C Figure 3. 8 7 VIN = 4.3V VOUT = 3.3V IOUT = 1mF 3.135 0 Output Spectral Noise Density - mV/ÖHz 4.5 VIN =4 .3V 3.432 IGND - Ground Current - mA VIN = 4.3V TPS71433 QUIESCENT CURRENT vs JUNCTION TEMPERATURE VDO - Dropout Voltage - mV VOUT - Output Voltage - V 3.432 VDO - Dropout Voltage - mV 3.465 TPS71433 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 1k 10k f - Frequency - Hz 100k Figure 6. Copyright © 2008–2011, Texas Instruments Incorporated 10 100 1k 10k 100k 1M 10M 10 20 30 40 50 60 70 80 I OUT - Output Current - mA f - Frequency - Hz Figure 7. Figure 8. Submit Documentation Feedback 5 TPS714xx SBVS116C – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. TPS71433 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 800 IOUT = 80mA 700 600 500 400 300 200 IOUT = 10mA 100 2.5 2.0 1.5 1.0 0.5 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 TJ - Junction Temperature - °C 400 500 70 60 IOUT = 1mA 50 40 30 IOUT = 50mA 20 10 0 10 100 1k 10k 100k 1M 10M f - Frequency - Hz TPS71433 POWER-UP/POWER-DOWN TPS71433 LINE TRANSIENT RESPONSE TPS71433 LOAD TRANSIENT RESPONSE 4 3 VIN 2 VOUT 1 0 2 4 6 8 10 12 14 16 18 20 t - Time - ms Figure 12. Submit Documentation Feedback VOUT = 3.3V IOUT = 50mA COUT = 10mF 100 50 0 IOUT - Output Current - mA 5 VOUT - Output Voltage - mV Figure 11. VIN - Input Voltage - V VIN - Input Voltage - V VOUT - Output Voltage - V 300 80 Figure 10. 6 0 200 VIN = 4.3V VOUT = 3.3V COUT = 10mF TJ = +25°C 90 Figure 9. VOUT = 3.3V RL = 66W COUT = 10mF 7 100 100 IOUT - Current Limit - mA 8 6 PSRR - Power Supply Ripple Rejection - dB VIN = 4.3V VOUT = 3.3V 3.0 VOUT - Output Voltage - V VDO - Dropout Voltage - mV 3.5 VIN = 4.3V 900 -50 5.3 4.3 0 50 100 150 200 250 300 350 400 450 500 t - Time - ms Figure 13. VOUT - Output Voltage - mV 1000 TPS71433 POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY TPS71433 VOUT vs CURRENT LIMIT V IN = 4.3V 200 V OUT = 3.3V COUT = 10mF 0 -200 100 50 0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 t - Time - ms Figure 14. Copyright © 2008–2011, Texas Instruments Incorporated TPS714xx SBVS116C – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION The TPS714xx family of LDO regulators has been optimized for ultralow power applications such as the MSP430 microcontroller. Its ultralow supply current maximizes efficiency at light loads, and its high input voltage range makes it suitable for supplies such as unconditioned solar panels. TPS71433 VIN IN C1 0.1mF OUT GND VOUT 0.47mF Figure 15. Typical Application Circuit (Fixed Voltage Version) External Capacitor Requirements Although not required, a 0.047μF or larger input bypass capacitor, connected between IN and GND and located close to the device, is recommended to improve transient response and noise rejection of the power supply as a whole. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated and if the device is located several inches from the power source. The TPS714xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. Any capacitor (including ceramic and tantalum) that is greater than or equal to 0.47μF properly stabilizes this loop. Power Dissipation and Junction Temperature To ensure reliable operation, worst-case junction temperature should not exceed +125°C. This restriction limits the power dissipation that the regulator can manage in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(MAX), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using Equation 1: T max * T A P D(max) + J R qJA Where: • • • TJmax is the maximum allowable junction temperature. RθJA is the thermal resistance junction-to-ambient for the package (see the Power Dissipation Rating table). TA is the ambient temperature. (1) The regulator dissipation is calculated using Equation 2: P D + ǒVIN * VOUTǓ I OUT (2) Power dissipation resulting from quiescent current is negligible. Regulator Protection The TPS714xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (for example, during power-down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. The TPS714xx features internal current limiting. During normal operation, the TPS714xx limits output current to approximately 500mA. When current limiting engages, the output voltage scales back linearly until the over-current condition ends. There is no internal thermal shutdown circuit in this device; therefore, care must be taken not to exceed the power dissipation ratings of the package during a fault condition. This device does not have undervoltage lockout; therefore, this constraint should be taken into consideration for specific applications. Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS714xx SBVS116C – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com Programming the TPS71401 Adjustable LDO Regulator The output voltage of the TPS71401 adjustable regulator is programmed using an external resistor divider as shown in Figure 16. The output voltage is calculated using Equation 3: V OUT + VREF Ǔ ǒ1 ) R1 R2 (3) where: VREF = 1.20V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately a 1.5μA divider current. Lower value resistors can be used for improved noise performance, but the solution consumes more power. Higher resistor values should be avoided because leakage current out of the FB pin across R1/R2 creates an offset voltage that artificially increases the feedback voltage and thus erroneously decreases VOUT. The recommended design procedure is to choose R2 = 1MΩ to set the divider current at 1.5μA, and then calculate R1 using Equation 4: V OUT R1 + *1 R2 V REF ǒ Ǔ (4) TPS71401 VIN OUTPUT VOLTAGE PROGRAMMING GUIDE IN 0.1mF OUTPUT VOLTAGE R1 R2 1.8V 392MW 806kW 2.8V 1.07MW 806kW 5.0V 2.55MW 806kW VOUT OUT R1 0.47mF FB GND R2 Figure 16. TPS71401 Adjustable LDO Regulator Programming 8 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated TPS714xx SBVS116C – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (December, 2009) to Revision C • Page Changed Ground pin current maximum specifications ......................................................................................................... 3 Changes from Revision A (April, 2009) to Revision B Page • Changed battery type shown in typical circuit illustration ..................................................................................................... 1 • Changed VIN range absolute maximum rating from +11.5V to +24V ................................................................................... 2 Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 9 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS71401DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVG TPS71401DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVG TPS71401DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVG TPS71401DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVG TPS71433DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVH TPS71433DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVH TPS71433DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVH TPS71433DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jan-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS71401DCKR SC70 DCK 5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 TPS71401DCKT SC70 DCK 5 250 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 TPS71401DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS71401DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS71433DCKR SC70 DCK 5 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 TPS71433DCKT SC70 DCK 5 250 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 TPS71433DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS71433DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jan-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS71401DCKR SC70 DCK 5 3000 202.0 201.0 28.0 TPS71401DCKT SC70 DCK 5 250 202.0 201.0 28.0 TPS71401DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS71401DRVT SON DRV 6 250 203.0 203.0 35.0 TPS71433DCKR SC70 DCK 5 3000 202.0 201.0 28.0 TPS71433DCKT SC70 DCK 5 250 202.0 201.0 28.0 TPS71433DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS71433DRVT SON DRV 6 250 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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