IS24C128B IS24C128B 2-WIRE (I2C) 128K-bit SERIAL EEPROM Intregrated Silicon Solution, Inc. - www.issi.com Rev. 00F 09/18/09 1 IS24C128B Table of Contents Features ……………………………………………………….……………............3 Description ………………………………………………...………………............3 Functional Block Diagram ………………………………………………............4 Pin Configuration & Description ……………………………………….............5 Device Operations …..……………………………………………………............6 Absolute Maximum Ratings …………………………………………….............12 DC Characteristics ………………………………………………………..............12 AC Characteristics ………………………………………………………..............13 Ordering Information ……………………………………………………..............15 Packaging Information ….………………………………………………..............16 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 IS24C128B 128K-bit 2-WIRE SERIAL CMOS EEPROM FEATURES • Two-Wire Serial Interface, I2CTM compatible – Bi-directional data transfer protocol • Wide Voltage Operation – Vcc = 1.8V to 5.5V • 400 KHz (1.8V) and 1 MHz (5.0V) compatibility • 128K-bit memory • Low Power CMOS Technology – Active Current less than 3 mA (1.8V) – Standby Current less than 15 µA (1.8V) • Hardware Data Protection – Write Protect Pin • Sequential Read Feature • Filtered Inputs for Noise Suppression • Self time write cycle with auto clear – 5 ms @ 1.8V • Memory Organization: –16Kx8 (256 pages of 64 bytes) • 64-Byte Page Write Buffer • High Reliability – Endurance: 1,000,000 Cycles – Data Retention: 40 Years • Industrial temperature range • Packages: SOIC/SOP (JEDEC) and TSSOP PRELIMINARY INFORMATION OCTOBER 2009 Description The IS24C128B is an electrically erasable PROM device that uses the standard 2-wire interface for communications. The IS24C128B is 128K-bit (16Kx8). These EEPROM are offered in a wide operating voltage range of 1.8V to 5.5V to be compatible with most application voltages. ISSI designed the IS24C128B to be an efficient 2-wire EEPROM solution. The devices are offered in lead free, RoHS, halogen free or Green. The available package types are 8-pin SOIC (JEDEC) and TSSOP. The IS24C128B maintains compatibility with the popular 2-wire bus protocol, so it is easy to design into applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as the IS24C128B. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24C128B has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus. Copyright © 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment, aerospace systems, or for other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products. Intregrated Silicon Solution, Inc. - www.issi.com Rev. 00F 09/18/09 3 IS24C128B FUNCTIONAL BLOCK DIAGRAM HIGH VOLTAGE GENERATOR, TIMING & CONTROL Vcc SCL CONTROL LOGIC WP SLAVE ADDRESS REGISTER & COMPARATOR A0 X DECODER SDA EEPROM ARRAY WORD ADDRESS COUNTER A1 Y DECODER A2 ACK GND nMOS 4 Clock DI/O > DATA REGISTER Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 IS24C128B PIN CONFIGURATION 8-Pin SOIC, TSSOP A0 1 8 VCC A1 2 7 WP A2 3 6 SCL GND 4 5 SDA PIN DESCRIPTIONS A0-A2 SDA SCL WP Vcc GND Address Inputs Serial Address/Data I/O Serial Clock Input Write Protect Input Power Supply Ground SCL A0, A1, A2 This input clock pin is used to synchronize the data transfer to and from the device. The A0, A1, and A2 are the device address inputs that are hardwired or left not connected for hardware compatibility with the IS24C32A/64A. When pins are hardwired, as many as eight 128K devices may be addressed on a single bus system. When the pins are not hardwired, the default values of A0, A1, and A2 are zero. SDA The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire Or'ed with other open drain or open collector outputs. The SDA bus a pullup resistor to Vcc. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 WP WP is the Write Protect pin. If the WP pin is tied to Vcc the entire array becomes Write Protected (Read only). When WP is tied to GND or left floating, normal read/write operations are allowed to the device. 5 IS24C128B DEVICE OPERATION Standby Mode The IS24C128B features a serial communication and supports a bi-directional 2-wire bus transmission protocol called I2CTM. Power consumption is reduced in standby mode. The IS24C128B will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if no write operation is initiated; or c) Following any internal write operation 2-WIRE BUS The two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers. The bus is controlled by Master device which generates the SCL, controls the bus access and generates the Stop and Start conditions. The IS24C128B is the Slave device on the bus. The Bus Protocol: – Data transfer may be initiated only when the bus is not busy – During a data transfer, the SDA line must remain stable whenever the SCL line is high. Any changes in the data line while the SCL line is high will be interpreted as a Start or Stop condition. The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. DEVICE ADDRESSING The Master begins a transmission by sending a Start condition. The Master then sends the address of the particular Slave devices it is requesting. The Slave device (Fig. 5) address is 8 bits. The four most significant bits of the Slave device address are fixed as 1010 for the IS24C128B. This device has three address bits (A2, A1, and A0), which allows up to eight IS24C128B devices to share the 2-wire bus. Upon receiving the Slave address, the device compares the three address bits with the hardwired A2, A1, and A0 input pins to determine if it is the appropriate Slave. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The IS24C128B monitors the SDA and SCL lines and will not respond until the Start condition is met. After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave (eg. IS24C128B) will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The selected IS24C128B then prepares for a Read or Write operation by monitoring the bus. Stop Condition WRITE OPERATION Start Condition The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition. Acknowledge (ACK) After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line. Reset The IS24C128B contains a reset function in case the 2-wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.) 6 Byte Write In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the two byte address that are to be written into the address pointer of the IS24C128B. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24C128B acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 IS24C128B Page Write The IS24C128B is capable of 64-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 63 more bytes. After the receipt of each data word, the IS24C128B responds immediately with an ACK on SDA line, and the six lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 64 words prior to issuing the Stop condition, the address counter will “roll over,” and the previously written data will be overwritten. Once all 64 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24C128B in a single Write cycle. All inputs are disabled until completion of the internal Write cycle. Acknowledge (ACK) Polling The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the IS24C128B initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the IS24C128B is still busy with the Write operation, no ACK will be returned. If the IS24C128B has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation. Read OPERATION Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to “1”. There are three Read operation options: current address read, random address read, and sequential read. generate a Stop condition so the IS24C128B discontinues transmission. If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read Diagram.) Random Address Read Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and word address of the location it wishes to read. After the IS24C128B acknowledges the word address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The IS24C128B then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 9. Random Address Read Diagram.) Sequential Read Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24C128B sends the initial byte sequence, the Master device now responds with an ACK indicating it requires additional data from the IS24C128B. The IS24C128B continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1, ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation. When the memory address boundary of 16383 (depending on the device) is reached, the address counter “rolls over” to address 0, and the IS24C128B continues to output data for each ACK received. (Refer to Figure 10. Sequential Read Operation Starting with a Random Address Read Diagram.) Current Address Read The IS24C128B contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the IS24C128B receives the Slave Device Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an ACK and transmit the 8-bit data word stored at address location n+1. The Master should not acknowledge the transfer but should Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 7 IS24C128B Figure 1. Typical System Bus Configuration Vcc SDA SCL Master Transmitter/ Receiver IS24C128B Figure 2. Output Acknowledge SCL from Master 1 8 9 Data Output from Transmitter tAA Data Output from Receiver tAA ACK STOP Condition SCL START Condition Figure 3. Start and Stop Conditions SDA 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 IS24C128B Figure 4. Data Validity Protocol Data Change SCL Data Stable Data Stable SDA Figure 5. Slave Address BIT 7 6 5 4 3 2 1 0 1 0 1 0 A2 A1 A0 R/W Figure 6. Byte Write SDA Bus Activity S T A R T Device Address M S B W R I T E Word Address Word Address A A A C * * C C K K K L M S * = Don't care bit S B B R/W S T O P Data A C K Figure 7. Page Write SDA Bus Activity S T A R T Device Address M S B W R I T E Word Address (n) Word Address (n) A A A C C * * C K K K L S B R/W Data (n+1) A C K Data (n+63) A C K A C K * = Don't care bit Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 Data (n) S T O P 9 IS24C128B Figure 8. Current Address Read SDA Bus Activity S T A R T R E A D Device Address S T O P Data A C K M S B L S B N O A C K R/W Figure 9. Random Address Read SDA Bus Activity S T A R T Device Address M S B W R I T E Word Address (n) A C * * K Word Address (n) A C K A C K L S B R/W S T A R T Device Address R E A D S T O P Data n A C K N O A C K * = Don't care bit DUMMY WRITE Figure 10. Sequential Read Device Address SDA Bus Activity R E A D Data Byte n A C K Data Byte n+2 A C K Data Byte n+X A C K N O R/W 10 Data Byte n+1 A C K S T O P A C K Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 IS24C128B Figure 11 DEEP SLEEP ENTRY/EXIT INITIATION SDA Bus Activity S T A R T W R I Device T Address E * Word Address(FFh) Word Address(FDh) A A A C C C K K K M L M S S S B B B R/W S T O P Data(5Ah) A C K * The slave does not provide an acknowledgement if the Deep Sleep Mode is enabled, and after stop, it begins to exit. Figure 12 DEEP SLEEP Verification SDA Bus Activity S T A R T R S E T A O D * P A C K Device Address M S B L S B R/W * The slave does not provide an acknowledgement if the Deep Sleep Mode is already enabled. This command does not affect Deep Sleep. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 11 IS24C128B ABSOLUTE MAXIMUM RATINGS(1) Symbol Vs Vp Tbias Tstg Iout Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value –0.5 to +6.5 –0.5 to Vcc +0.5 –55 to +125 –65 to +150 5 Unit V V °C °C mA Notes: 1. Stresses violating the conditions listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only. Functional operation of the device outside these conditions or those indicated in the operational sections of this specification is not implied. Exposure to these conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS Industrial (Ta = -40oC to +85oC) Symbol Parameter Vol1 Vol2 Vih Vil Ili Ilo Test Conditions Output Low Voltage Vcc = 1.8V, Iol = 0.15 mA Output Low Voltage Vcc = 2.5V, Iol = 2.1 mA Input High Voltage Input Low Voltage Input Leakage Current Vin = Vcc max. Output Leakage Current Min. Max. — 0.2 — 0.4 Vcc x 0.7 Vcc + 0.5 –0.3 Vcc x 0.3 — 3 — 3 Unit V V V V µA µA Notes: Vil min and Vih max are reference only and are not tested POWER SUPPLY CHARACTERISTICS Industrial (Ta = -40oC to +85oC) Symbol Parameter Icc1 Operating Current Icc2 Operating Current Isb1 Test Conditions Min. Max. Unit Read at 400 KHz (Vcc = 1.8V) — 3.0 mA Write at 400 KHz (Vcc = 1.8V) — 3.0 mA Standby Current Vcc = 1.8V — 15 µA Isb2 Standby Current Vcc = 2.5V — 20 µA Isb3 Standby Current Vcc = 5.0V — 25 µA CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vcc = 5.0V. 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 IS24C128B AC ELECTRICAL CHARACTERISTICS Industrial (Ta = -40oC to +85oC) Symbol fSCL T tLow tHigh tBUF tSU:STA tSU:STO tHD:STA tHD:STO tSU:DAT tHD:DAT tsu:wp thd:wp tDH tAA tR tF tWR Parameter(2) SCL Clock Frequency Noise Suppression Time(1) Clock Low Period Clock High Period Bus Free Time Before New Transmission(1) Start Condition Setup Time Stop Condition Setup Time Start Condition Hold Time Stop Condition Hold Time Data In Setup Time Data In Hold Time WP pin Setup Time WP pin Hold Time Data Out Hold Time (SCL Low to SDA Data Out Change) Clock to Output (SCL Low to SDA Data Out Valid) SCL and SDA Rise Time(1) (1) SCL and SDA Fall Time Write Cycle Time 1.8V ≤ Vcc < 2.5V 2.5V ≤ Vcc ≤ 5.5V(1) Min. Max. 0 400 — 50 1.2 — 0.6 — 1.2 — 0.6 — 0.6 — 0.6 — 0.6 — 100 — 0 — 0.6 — 1.2 — 50 — Min. Max. 0 1000 — 50 0.6 — 0.4 — 0.5 — 0.25 — 0.25 — 0.25 — 0.25 — 100 — 0 — 0.6 — 1.2 — 50 — 50 — — — 900 300 300 5 50 — — — 400 300 100 5 Unit KHz ns µs µs µs µs µs µs µs ns ns µs µs ns ns ns ns ms Notes: 1. This parameter is characterized but not 100% tested. 2. The timing is referenced to half Vcc level. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 13 IS24C128B AC WAVEFORMS Figure 13. Bus Timing tR tF tHIGH tLOW tSU:STO SCL tSU:STA tBUF tHD:DAT tHD:STA tSU:DAT SDAIN tAA tDH SDAOUT tSU:WP tHD:WP WP Figure 14. Write Cycle Timing SCL SDA 8th BIT ACK tWR WORD n STOP Condition 14 START Condition Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 IS24C128B ORDERING INFORMATION: Industrial Range: -40°C to +85°C, Lead-free* Voltage Range Part Number* Package Type* (8-pin) 1.8V to 5.5V IS24C128B-2GLI-TR 150-mil SOIC (JEDEC) IS24C128B-2ZLI-TR 3 x 4.4 mm TSSOP * 1. Contact ISSI Sales Representatives for availability and other package information. 2. The listed part numbers are packed in tape and reel “-TR” (4K per reel). UDFN/DFN is 5K per reel. 3. For tube/bulk packaging, if available, remove “-TR” at the end of the P/N. 4. Refer to ISSI website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable. 5. ISSI offers Industrial grade for Commercial applications (0oC to +70oC). Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 15 IS24C128B 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 IS24C128B Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 17