TI TXS0102DCUR

TXS0102
www.ti.com
SCES640C – JANUARY 2007 – REVISED MAY 2009
2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR
FOR OPEN-DRAIN AND PUSH-PULL APPLICATIONS
Check for Samples: TXS0102
FEATURES
1
•
•
2
•
•
•
•
•
•
•
No Direction-Control Signal Needed
Max Data Rates
– 24 Mbps (Push Pull)
– 2 Mbps (Open Drain)
Available in the Texas Instruments NanoFree™
Package
1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on
B port (VCCA ≤ VCCB)
VCC Isolation Feature – If Either VCC Input Is at
GND, Both Ports Are in the High-Impedance
State
No Power-Supply Sequencing Required –
Either VCCA or VCCB Can Be Ramped First
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– A Port
– 2500-V Human-Body Model (A114-B)
– 250-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)
– B Port
– 8-kV Human-Body Model (A114-B)
– 250-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)
TYPICAL LEVEL-SHIFTER
APPLICATIONS
•
•
•
I2C/SMBus
UART
GPIO
DCT OR DCU PACKAGE
(TOP VIEW)
B2
1
8
B1
GND
2
7
VCCB
VCCA
3
6
OE
A2
4
5
A1
YZP PACKAGE
(BOTTOM VIEW)
A2
D1
VCCA
GND
B2
A1
4 5
D2
C1
3 6
C2
OE
B1
2 7
B2
VCCB
A1
1 8
A2
B1
DESCRIPTION/ORDERING INFORMATION
This two-bit non-inverting translator is a bidirectional voltage-level translator and can be used to establish digital
switching compatibility between mixed-voltage systems. It uses two separate configurable power-supply rails,
with the A ports supporting operating voltages from 1.65 V to 3.6 V while it tracks the VCCA supply, and the B
ports supporting operating voltages from 2.3 V to 5.5 V while it tracks the VCCB supply. This allows the support of
both lower and higher logic signal levels while providing bidirectional translation capabilities between any of the
1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
When the output-enable (OE) input is low, all I/Os are placed in the high-impedance state, which significantly
reduces the power-supply quiescent current consumption.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree, NanoStar are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
TXS0102
SCES640C – JANUARY 2007 – REVISED MAY 2009
www.ti.com
Table 1. ORDERING INFORMATION
PACKAGE (1)
TA
(2)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
–40°C to 85°C
SSOP – DCT
VSSOP – DCU
(1)
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (3)
Reel of 3000
TXS0102YZPR
2H_
Reel of 3000
TXS0102DCTR
NFE_ _ _
Reel of 250
TXS0102DCTT
NFE _ _ _
Reel of 3000
TXS0102DCUR
NFE_
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DCT: The actual top-side marking has three additional characters that designate the year, month, and wafer fab/assembly site.
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
(3)
PIN DESCRIPTION
NO.
NAME
TYPE
FUNCTION
DCT,
DCU
YZP
1
A1
B2
I/O
2
B1
GND
GND
Ground
3
C1
VCCA
PWR
A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB
4
D1
A2
I/O
Input/output A. Referenced to VCCA.
5
D2
A1
I/O
Input/output A. Referenced to VCCA.
6
C2
OE
Input
Output enable (active High). Pull OE low to place all outputs in 3-state mode.
Referenced to VCCA.
7
B2
VCCB
PWR
B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V
8
A2
B1
I/O
Input/output B. Referenced to VCCB.
Input/output B. Referenced to VCCB.
TYPICAL OPERATING CIRCUIT
1.8 V
3.3 V
0.1 mF
0.1 mF
1.8 V
System
Controller
Data
2
VCCA
VCCB
OE
A1
A2
B1
B2
1 mF
3.3 V
System
Data
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TXS0102
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SCES640C – JANUARY 2007 – REVISED MAY 2009
ABSOLUTE MAXIMUM RATINGS (1)
over recommended operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA
Supply voltage range
–0.5
4.6
V
VCCB
Supply voltage range
–0.5
6.5
V
A port
–0.5
4.6
B port
–0.5
6.5
A port
–0.5
4.6
B port
–0.5
6.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
VI
Input voltage range (2)
VO
Voltage range applied to any output
in the high-impedance or power-off state (2)
VO
Voltage range applied to any output in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
(3)
Continuous current through VCCA, VCCB, or GND
qJA
Package thermal impedance (4)
Tstg
Storage temperature range
DCT package
220
DCU package
227
YZP package
(1)
(2)
(3)
(4)
VCCA
Supply voltage
VCCB
Supply voltage
°C/W
150
°C
(2)
VCCB
(3)
1.65 V to 1.95 V
A-port I/Os
High-level
input voltage
VIH
2.3 V to 3.6 V
B-port I/Os
OE input
2.3 V to 5.5 V
1.65 V to 3.6 V
2.3 V to 5.5 V
1.65 V to 3.6 V
2.3 V to 5.5 V
A-port I/Os
(4)
Low-level
input voltage
B-port I/Os
OE input
Δt/Δv
(1)
(2)
(3)
(4)
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCCA and VCCB are provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
VCCA
TA
V
102
–65
RECOMMENDED OPERATING CONDITIONS (1)
VIL
V
A-port I/Os, push-pull driving
Input transition
B-port I/Os, push-pull driving
rise or fall rate
Control input
MIN
MAX
1.65
3.6
V
2.3
5.5
V
VCCI – 0.2
VCCI
VCCI – 0.4
VCCI
VCCI – 0.4
VCCI
VCCA × 0.65
5.5
0
0.15
0
0.15
0
VCCA × 0.35
UNIT
V
V
10
1.65 V to 3.6 V
2.3 V to 5.5 V
Operating free-air temperature
10
ns/V
10
–40
85
°C
VCCI is the supply voltage associated with the input port.
VCCO is the supply voltage associated with the output port.
VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
The maximum VIL value is provided to ensure that a valid VOL is maintained. The VOL value is VIL plus the voltage drop across the
pass-gate transistor.
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TXS0102
SCES640C – JANUARY 2007 – REVISED MAY 2009
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ELECTRICAL CHARACTERISTICS (1)
(2) (3)
over recommended operating free-air temperature range (unless otherwise noted)
TEST
CONDITIONS
VCCA
VCCB
VOHA
IOH = –20 mA,
VIB ≥ VCCB – 0.4 V
1.65 V to 3.6 V
2.3 V to 5.5 V
VOLA
IOL = 1 mA,
VIB ≤ 0.15 V
1.65 V to 3.6 V
2.3 V to 5.5 V
VOHB
IOH = –20 mA,
VIA ≥ VCCA – 0.2 V
1.65 V to 3.6 V
2.3 V to 5.5 V
VOLB
IOL = 1 mA,
VIA ≤ 0.15 V
1.65 V to 3.6 V
2.3 V to 5.5 V
1.65 V to 3.6 V
2.3 V to 5.5 V
0V
0 to 5.5 V
PARAMETER
II
Ioff
IOZ
OE
A port
B port
VCCA × 0.67
UNIT
V
0.4
VCCB × 0.67
V
V
0.4
V
±1
±2
mA
±1
±2
mA
0V
±1
±2
mA
±1
±2
mA
1.65 V to VCCB
2.3 V to 5.5 V
2.4
3.6 V
0V
2.2
0V
5.5 V
–1
1.65 V to VCCB
2.3 V to 5.5 V
12
3.6 V
0V
–1
0V
5.5 V
1
1.65 V to VCCB
2.3 V to 5.5 V
OE
3.3 V
3.3 V
2.5
A or B port
3.3 V
3.3 V
10
VI = VO = open,
IO = 0
ICCA + ICCB
VI = VCCI or GND,
IO = 0
4
MIN MAX
2.3 V to 5.5 V
VI = VO = open,
IO = 0
(1)
(2)
(3)
TYP MAX
0 to 3.6 V
ICCB
Cio
MIN
–40°C to 85°C
1.65 V to 3.6 V
A or B port
ICCA
CI
TA = 25°C
A port
5
6
B port
6
7.5
mA
mA
14.4
mA
3.5
pF
pF
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
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SCES640C – JANUARY 2007 – REVISED MAY 2009
TIMING REQUIREMENTS
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
MIN
Data rate
tw
Pulse
duration
MAX
Push-pull driving
Open-drain driving
Push-pull driving
Open-drain driving
Data inputs
VCC = 3.3 V
± 0.3 V
MIN
VCC = 5 V
± 0.5 V
MAX
MIN
UNIT
MAX
21
22
24
2
2
2
47
45
41
500
500
500
Mbps
ns
TIMING REQUIREMENTS
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
MIN
Data rate
tw
Pulse
duration
Push-pull driving
Open-drain driving
Push-pull driving
Open-drain driving
Data inputs
VCC = 3.3 V
± 0.3 V
MAX
MIN
VCC = 5 V
± 0.5 V
MAX
MIN
UNIT
MAX
20
22
24
2
2
2
50
45
41
500
500
500
Mbps
ns
TIMING REQUIREMENTS
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
VCC = 3.3 V
± 0.3 V
MIN
Data rate
tw
Pulse duration
Push-pull driving
Open-drain driving
Push-pull driving
Open-drain driving
Data inputs
VCC = 5 V
± 0.5 V
MAX
MIN
UNIT
MAX
23
24
2
2
43
41
500
500
Mbps
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ns
5
TXS0102
SCES640C – JANUARY 2007 – REVISED MAY 2009
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCCB = 2.5 V
± 0.2 V
MIN
Push-pull driving
tPHL
A
B
tPLH
Open-drain driving
Push-pull driving
A
ten
OE
A or B
tdis
OE
A or B
tPLH
Open-drain driving
45
A-port rise time
trB
B-port rise time
tfA
A-port fall time
tfB
B-port fall time
tSK(O)
Channel-to-channel skew
Max data rate
8.8
260
1.9
Push-pull driving
5.3
175
MIN
9.6
36
208
4.4
27
36
140
1.2
198
4
0.5
27
200
50
40
200
ns
35
ns
3.2
9.5
2.3
9.3
2
7.6
Open-drain driving
38
165
30
132
22
95
Open-drain driving
Push-pull driving
4
10.8
2.7
9.1
2.7
7.6
34
145
23
106
10
58
2
5.9
1.9
6
1.7
13.3
Open-drain driving
4.4
6.9
4.3
6.4
4.2
6.1
Push-pull driving
2.9
13.8
2.8
16.2
2.8
16.2
Open-drain driving
6.9
13.8
7.5
16.2
7
16.2
0.7
Push-pull driving
Open-drain driving
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0.7
0.7
21
22
24
2
2
2
ns
102
Push-pull driving
Push-pull driving
ns
4.7
4.5
200
10
7.5
4.5
1.1
UNIT
MAX
6.8
2.6
7.1
5.3
45
MAX
VCCB = 5 V
± 0.5 V
5.4
2.4
4.4
Open-drain driving
trA
MIN
6.8
Push-pull driving
B
MAX
VCCB = 3.3 V
± 0.3 V
5.3
2.3
Open-drain driving
tPHL
6
TEST CONDITIONS
ns
ns
ns
ns
Mbps
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS0102
TXS0102
www.ti.com
SCES640C – JANUARY 2007 – REVISED MAY 2009
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCCB = 2.5 V
± 0.2 V
MIN
Push-pull driving
tPHL
A
B
tPLH
Open-drain driving
Push-pull driving
A
ten
OE
A or B
tdis
OE
A or B
tPLH
Open-drain driving
43
A-port rise time
trB
B-port rise time
tfA
A-port fall time
tfB
B-port fall time
tSK(O)
Channel-to-channel skew
Max data rate
250
1.8
Push-pull driving
4.7
170
MIN
6
36
206
4.2
27
37
140
1.2
190
4
1
27
200
50
40
200
ns
35
ns
2.8
7.4
2.6
6.6
1.8
5.6
Open-drain driving
34
149
28
121
24
89
Push-pull driving
3.2
8.3
2.9
7.2
2.4
6.1
Open-drain driving
35
151
24
112
12
64
Push-pull driving
1.9
5.7
1.9
5.5
1.8
5.3
Open-drain driving
4.4
6.9
4.3
6.2
4.2
5.8
Push-pull driving
2.2
7.8
2.4
6.7
2.6
6.6
Open-drain driving
5.1
8.8
5.4
9.4
5.4
10.4
Push-pull driving
Open-drain driving
0.7
0.7
20
22
24
2
2
2
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ns
103
Push-pull driving
0.7
ns
4.3
1.6
200
5.8
4.4
3.6
2.6
UNIT
MAX
3.8
2.1
4.1
2.5
44
MAX
VCCB = 5 V
± 0.5 V
3.7
2
3
Open-drain driving
trA
6.3
3.5
Push-pull driving
B
MIN
3.2
1.7
Open-drain driving
tPHL
MAX
VCCB = 3.3 V
± 0.3 V
ns
ns
ns
ns
ns
Mbps
7
TXS0102
SCES640C – JANUARY 2007 – REVISED MAY 2009
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCCB = 3.3 V
± 0.3 V
MIN
Push-pull driving
tPHL
A
B
tPLH
Open-drain driving
A
ten
OE
A or B
tdis
OE
A or B
tPLH
Open-drain driving
36
trA
A-port rise time
trB
B-port rise time
tfA
A-port fall time
tfB
B-port fall time
tSK(O)
Channel-to-channel skew
Max data rate
4.2
204
1
124
139
4.6
4.4
28
1
165
97
2.6
3
200
40
200
ns
35
ns
2.3
5.6
1.9
4.8
Open-drain driving
25
116
19
85
Push-pull driving
2.5
6.4
2.1
7.4
Open-drain driving
26
116
14
72
2
5.4
1.9
5
Open-drain driving
4.3
6.1
4.2
5.7
Push-pull driving
2.3
7.4
2.4
7.6
5
7.6
4.8
8.3
Open-drain driving
0.7
Push-pull driving
Open-drain driving
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0.7
23
24
2
2
ns
105
Push-pull driving
Push-pull driving
ns
3.3
2.5
3
UNIT
MAX
3.1
1.4
2.5
Push-pull driving
Open-drain driving
MIN
4.2
Push-pull driving
B
MAX
VCCB = 5 V
± 0.5 V
2.4
1.3
Push-pull driving
Open-drain driving
tPHL
8
TEST CONDITIONS
ns
ns
ns
ns
ns
Mbps
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS0102
TXS0102
www.ti.com
SCES640C – JANUARY 2007 – REVISED MAY 2009
PRINCIPLES OF OPERATION
Applications
The TXS0102 can be used to bridge the digital-switching compatibility gap between two voltage nodes to
successfully interface logic threshold levels found in electronic systems. It should be used in a point-to-point
topology for interfacing devices or systems operating at different interface voltages with one another. Its primary
target application use is for interfacing with open-drain drivers on the data I/Os such as I2C or 1-wire, where the
data is bidirectional and no control signal is available. The TXS0102 can also be used in applications where a
push-pull driver is connected to the data I/Os, but the TXB0102 might be a better option for such push-pull
applications.
Architecture
The TXS0102 architecture (see Figure 1) is an auto-direction-sensing based translator that does not require a
direction-control signal to control the direction of data flow from A to B or from B to A.
VCCA
VCCB
T1
One
Oneshot
shot
One
Oneshot
shot
T2
R1
10k
R2
10k
Gate Bias
A
B
N2
Figure 1. Architecture of a TXS01xx Cell
These two bidirectional channels independently determine the direction of data flow without a direction-control
signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is how this
auto-direction feature is realized.
The TXS0102 is part of TI's "Switch" type voltage translator family and employs two key circuits to enable this
voltage translation:
1) An N-channel pass-gate transistor topology that ties the A-port to the B-port
and
2) Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B
ports
For bidirectional voltage translation, pull-up resistors are included on the device for dc current sourcing capability.
The VGATE gate bias of the N-channel pass transistor is set at approximately one threshold voltage (VT) above
the VCC level of the low-voltage side. Data can flow in either direction without guidance from a control signal.
The O.S. rising-edge rate accelerator circuitry speeds up the output slew rate by monitoring the input edge for
transitions, helping maintain the data rate through the device. During a low-to-high signal rising edge, the O.S.
circuits turn on the PMOS transistors (T1, T2) to increase the current drive capability of the driver for
approximately 30 ns or 95% of the input edge, whichever occurs first. This edge-rate acceleration provides high
ac drive by bypassing the internal 10-kΩ pull-up resistors during the low-to-high transition to speed up the signal.
The output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase. To
minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to turn-off
before applying a signal in the opposite direction. The worst-case duration is equal to the minimum pulse-width
number provided in the Timing Requirements section of this data sheet.
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Input Driver Requirements
The continuous dc-current "sinking" capability is determined by the external system-level open-drain (or
push-pull) drivers that are interfaced to the TXS0102 I/O pins. Since the high bandwidth of these bidirectional I/O
circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a
modest dc-current "sourcing" capability of hundreds of micro-Amps, as determined by the internal 10-kΩ pullup
resistors.
The fall time (tfA, tfB) of a signal depends on the edge-rate and output impedance of the external device driving
TXS0102 data I/Os, as well as the capacitive loading on the data lines.
Similarly, the tPHL and max data rates also depend on the output impedance of the external driver. The values for
tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver is
less than 50 Ω.
Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TXS0102 output sees, so it is recommended that this lumped-load capacitance be
considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level
affects.
Power Up
During operation, ensure that VCCA ≤ VCCB at all times. The sequencing of each power supply will not damage
the device during the power up operation, so either power supply can be ramped up first.
Enable and Disable
The TXS0102 has an OE input that is used to disable the device by setting OE low, which places all I/Os in the
Hi-Z state. The disable time (tdis) indicates the delay between the time when OE goes low and when the outputs
are disabled (Hi-Z). The enable time (ten) indicates the amount of time the user must allow for the one-shot
circuitry to become operational after OE is taken high.
Pullup or Pulldown Resistors on I/O Lines
Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup
resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O
to VCCA or VCCB (in parallel with the internal 10-kΩ resistors). Adding lower value pull-up resistors will effect VOL
levels, however. The internal pull-ups of the TXS0102 are disabled when the OE pin is low.
10
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS0102
TXS0102
www.ti.com
SCES640C – JANUARY 2007 – REVISED MAY 2009
PARAMETER MEASUREMENT INFORMATION
VCCI
VCCO
VCCI
VCCO
DUT
IN
DUT
IN
OUT
OUT
1 MW
15 pF
1 MW
15 pF
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
AN OPEN-DRAIN DRIVER
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
A PUSH-PULL DRIVER
2 × VCCO
50 kW
From Output
Under Test
15 pF
S1
Open
50 kW
LOAD CIRCUIT FOR ENABLE/DISABLE
TIME MEASUREMENT
TEST
S1
tPZL/tPLZ
tPHZ/tPZH
2 × VCCO
Open
tw
VCCI
VCCI/2
Input
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VCCO/2
0.9 y VCCO
0.1 y VCCO
tr
VOH
VCCO/2
VOL
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VCCA/2
VCCO
VCCO/2
0.1 y VCCO
VOL
tPHZ
tPZH
VOH
0.9 y VCCO
VCCO/2
0V
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS0102
11
TXS0102
SCES640C – JANUARY 2007 – REVISED MAY 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 2. Load Circuit and Voltage Waveforms
12
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS0102
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TXS0102DCTR
ACTIVE
SM8
DCT
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TXS0102DCTRE4
ACTIVE
SM8
DCT
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TXS0102DCTT
ACTIVE
SM8
DCT
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TXS0102DCTTE4
ACTIVE
SM8
DCT
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TXS0102DCTTG4
ACTIVE
SM8
DCT
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TXS0102DCUR
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TXS0102DCURG4
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TXS0102DCUT
ACTIVE
US8
DCU
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TXS0102DCUTG4
ACTIVE
US8
DCU
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TXS0102YZPR
ACTIVE
DSBGA
YZP
8
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TXS0102DCUR
US8
DCU
8
3000
180.0
9.2
2.25
3.35
1.05
4.0
8.0
Q3
TXS0102YZPR
DSBGA
YZP
8
3000
180.0
8.4
1.02
2.02
0.63
4.0
8.0
Q1
TXS0102YZPR
DSBGA
YZP
8
3000
178.0
9.2
1.02
2.02
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXS0102DCUR
US8
DCU
8
3000
202.0
201.0
28.0
TXS0102YZPR
DSBGA
YZP
8
3000
220.0
220.0
34.0
TXS0102YZPR
DSBGA
YZP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
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• DALLAS, TEXAS 75265
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