KK4428 1К-byte EEPROM microcircuit with function of protection for writing and programmable secret code. Microcircuit KK4428 is designed to use in intellectual plastic cards. Sphere of application: medical insurance, excess control systems, member cards, smart cards. Features: 1024 x 8 - arrangement of EEPROM; Byte - directed addressing; Protection of memory writing; 1024 х 1 bit arrangement of memory protection ; Response for reset; Minimum 10000 cycles of erasure / writing ; Information storage time - 5 years ; Location of contact pads and serial interface in accordance with ISO 7816 standard; Data in memory can be changed only after introduction of correct 2-byte programmable secret code (PSC); Purpose of IC contact pads CP 01 02 03 04 05 Symbol I/O CLK RST Vcc GND Function Bidirectional data line (open drain ) clock rate input control input (reset ) supply voltage general KK4428 Block diagram Base memory EEPROM 1024x8 bit protcetion memory PROM 1024x1 bit High voltage multiplier Circuit of reset and holding Vcc Decoder of lines and column with ampliffers Programming control unit Secret logit unit Interface unit I/O GND RST CLK Graphical symbol of IC 02 CLK 03 RST EE PROM Operating temperature range Operating temperature range from -35°С to +100°С. <-> I/O 01 Vcc 04 GND 05 KK4428 Extreme modes Symbol Name of parameter Standard min max Measurement unit VСС Supply voltage 4,5 5,5 V VIH VIL Т Input voltage of high level Input voltage of low level Operating temperature range 3,5 0 -35 VСС 0,8 +100 V V °С Limiting modes Symbol Name of parameter VСС VIH VIL Tstg Supply voltage Input voltage of high level Input voltage of low level Storage temperature Standard min max -0,3 -0,3 -40 Measurement unit 6,0 6,0 +125 V В V °С They do not guarantee efficiency of ICs at limiting modes. After removal of limiting modes they guarantee efficiency in extreme mode. Static parameters TA = from -35 to +100°С Symbol Name of parameter measurement conditions Standard min max unit of measurement Input voltage of low level Input voltage of high level VСС=from 4,5 to 5,5V 0 0,8 V VСС=from 4,5 to 5,5V 3,5 VСС V IOL Output current of low level 0,5 - mА IOH Output leakage current of high level - 10 µА IIH Input current of high level (I/O,CLK,RST) consumption current VСС=from 4,5 to 5,5V VOL= 0,4V VСС=5,5V VOH=5,5V VСС=5,5V VIH=5,5V - 10 µА VСС=5,5V, VIL=0V, VIH=VCC - 10 mА VIL VIH IСС KK4428 Dynamic parameters VСС= from 4,5 to 5,5V, ТA = from -35 to +100°С Symbol td1 td2 td3 td4 td5 td6 tL tH tW tE tRE tR tF Name of parameter Standard min max setting up time (D/CLK) 4,0 - delay time (CLK/D) setting up time (CLK/RST) setting up time (RST/CLK) 6,0 - hold-in time (D/CLK) hold-in time (RST) CLK low level CLK high level writing time (fс=20 kHz) erasure time (fс=20 kHz) delay time Time of rise front (I/O, CLK, RST) Time of fall (I/O, CLK, RST) Unit of measurement 4,0 4,0 20,0 10,0 10,0 5,0 5,0 9,0 - 1,0 µs µs µs µs µs µs µs µs µs µs µs µs - 1,0 µs - Memory Memory of microcircuit consists of base memory with the structure of 1024 х 8 bit EEPROM and protection memory with the structure of 1024 х 1 bit PROM. Every byte of memory can be protected separately from erasure/writing by the way of programming the corresponding bit of protection memory. They programm Bit of protection only one time and it can not be erased. Also microcircuit has protection with programmable secret code (PSC), which controls excess to erasure/writing of memory. For this purpose the last three bytes of the base memory intended for error counter (one byte with the address 1021) and PSC (two byte with addresses 1022 and 1023). Without verification of PSC only reading of base memory from the address 0 to address 1021 is possible (storage range of PSC is zero notated) and error counter writing. After successful verification of PSC all base memory from address 0 to address 1023 is readable and available for operations of erasure/writing. This state of microcircuit retain to power supply switch off. After switching on of power supply the PSC verification procedure should be carried out again. After eight unsuccessful attempts to verify PSC, error counter blocks irreversibly any possibility to change contents of memory. KK4428 Response for reset Reset can be supplied at any time during microcircuit operates. After reset during 32-clock pulses to the line I/O, contents of first 4 bytes of memory are read. System of commands Base commands of introduction Base enter commands Byte l S0 SI S2 S3 S4 S5 A8 A9 1 0 0 0 1 1 address bits 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 8 and 9 0 1 1 1 0 0 Byte 2 A0-A7 address bits 0-7 Byte 3 D0-D7 input data Operation writing and erasure with protection bit input data writing and erasure without protection bit data compared writing of protection bit with data verification have no value reading of 9 bit, data with protection bit have no value reading of 8 bit, data without protection bit Commands of enter for PSC verification byte l S0 S1 0 1 1 0 1 0 S2 0 1 1 S3 0 1 1 S4 1 0 0 S5 1 0 0 A8 1 1 1 A9 1 1 1 byte 2 A0-A7 253 254 255 byte 3 D0-D7 mask bit byte 1 ПСК byte 2 ПСК operation writing of error counter verification of the first byte PSC verification of the second byte PSC In erased state memory cells shall be read as logic "1". After operation of writing memory cells shall be read as logic "0". There are three kind of operations of writing /erasure, that are implemented automatically by the microcircuit: -erasure and following writing (duration is 203 timing pulses CLK, f=20 kHz); -only writing, if no one of the 8 bit in addressed byte requires to be turned from "0" into "1 (duration is 103 timing pulses CLK, f=20 kHz); -only erasure - if there are no turns from "1" into "0" in addressed byte (duration is 103 timing pulses CLK, f=20 kHz). KK4428 Time diagrams RST CLK I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 S0 S1 S2 S3 S4 S5A8 A9 A0 A1A2 A3 A4 A5 A6 A7D0 D1D2 D3 D4 D5D6 D7 Byte 1 Control word Byte 2 Address Byte 3 Data Figure 1 - introduction of the command VCC RST CLK I/O 1 2 3 1 2 31 32 31 td6 RST td4 td4 td2 tH tL CLK td5 I/O Figure 2 - Reset and response for reset 32 KK4428 Removal of data or verification of PSC Data introduction tRE td3 tH td4 RST CLK 0 1 23 0 1 I/O td5 td2 tL td1` Stable data Figure 3 - Data introduction, removal of data and verification of programmable secret code Data introduction Programming RST CLK 0 1 23 S0 S1 99 tE E/W Active (internal signal) I/O 0 1 2 102 199 tW D7 Figure 4 - programming: erasure and writing 202 KK4428 Data introduction Programming RST CLK 0 1 23 E/W Active (internal signal) I/O S0 S1 0 1 2 99 102 Only erasure or only writing D7 Figure 5 - programming: erasure or writing Removal of data Data inproduction RST CLK 0 23 I/O A8 A9 D7 Start address 0 1 2 3 4 Start address 5 6 7 0 1 2 3 4 4 5 6 7 Start address +1 Start address +n Fictiv data Figure 6 - data byte reading: reading of 8 bit data D0-D7 KK4428 Data introduction Removal of data RST CLK 0 23 I/O A8 A9 D7 Start address 0 1 2 3 4 5 6 7 PB 0 Start address 1 2 3 5 6 7 PB Start address+1 Start address +n Fictive data Figure 7 - reading of 9 bit: D0-D7 data byte and PB protection byte Verific. Data introduction RST td4 CLK 0 7 0 I/O 7 0 A0 Control word 7 D0 D1 Address D7 Byte code Verification of byte completed Figure 8 - Verification of programmable secret code byte