TI SN54AS195

!"#!%$&'()*
SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995
• +Parallel-to-Serial, Serial-to-Parallel
D OR N PACKAGE
(TOP VIEW)
Conversions
• Parallel Synchronous Loading
,
• J and K Inputs to First Stage
• -Right Shift Only With Complementary
/
•
•
Outputs on Last Stage
Direct Overriding Clear
Options Include Plastic
.Package
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
6
CLR
J
K
A
B
C
D
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
QA
QB
QC
QD
QD
CLK
SH/LD
description
1
4-bit bidirectional universal
shift register features parallel
(A, B, C, D) inputs, parallel (QA, QB, Q0C, QD
1
1
1 , QD)
2This
outputs, J-K serial (J, K) inputs, shift/load control (SH/LD) input, and a direct overriding clear (CLR). The
registers have two modes of operation:
• Parallel (broadside) load
3
1
• Shift (in the direction QA toward QD)
Parallel loading is accomplished by applying the four bits of data and taking SH/LD low. The data is loaded into
4the
associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During
loading, serial data flow is inhibited.
3Shifting is accomplished synchronously when SH/LD
is high. Serial data for this mode is entered at the J-K
inputs. These inputs permit the first stage to perform as a J-K, D-, or T-type flip-flop as shown in the function
4table.
5
5
The SN74AS195 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
SERIAL
CLR
SH/LD
CLK
PARALLEL
J
K
A
B
C
D
QA
QB
QC
L
L
X
X
X
X
X
X
X
X
L
L
H
L
↑
X
X
a
b
c
d
a
bc
H
H
L
X
X
X
XX
X
QA0
QB0
H
H
↑
L
H
X
X
X
X
QA0
QA0
H
H
↑
L
L
X
X
X
X
L
H
H
↑
H
H
X
X
X
X
H
H
↑
H
L
X
X
X
X
QD
QD
L
H
d
d
QC0
QD0
QD0
QBn
QCn
QCn
QAn
QBn
QCn
QCn
H
QAn
QAN
QAn
QBn
QBn
QCn
QCn
QCn
QCn
798;:<>[email protected]?>ACB :ED<@[email protected] H I JCK LNM;OPG JQHRG [email protected] K WXH OYM;SZJ[I]\ VQ^C_ G [email protected];OPG JQHa`[email protected] W>b
;SO [email protected] K [email protected]`CG `CHV[[email protected]@K O JC`[email protected];_ @K H K\ I [email protected] M;LUO jLfb;O W;J7PO K W;JCSXK `C\[email protected] T>[email protected] IcG JQG T;[email protected]\ G JQK J[H [email protected]@\S;[email protected] H OPkNe WN`[email protected]@K SlLfSNH JCJCOQIH [email protected];[email protected]@[email protected]@M;S;[email protected]@B K;H [email protected] _ jmO K VCG H LfTXW>_ VCH `CO SW
Copyright  1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
nopqrnstu
qvwxy(wxzx{|~}yxor€!ox‚#|{nr€!n%ƒ„x…'y({|~†‡xny*|{
SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995
ˆ
logic symbol†
CLR
1
9
SH/LD
SRG4
R
M1 [SHIFT]
M2 [LOAD]
CLK
J
10
2
3
K
A
B
C
D
4
5
C3/1
1, 3J
15
1, 3K
QA
2, 3D
14
2, 3D
6
13
7
12
11
QB
QC
QD
QD
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
‰Š‹ŒŽ‰‘
Œ’“”•(“”–”—˜~™•”š‡ŠŽ›!œŠ”#˜—‰›!‰%ž”Ÿ •(—˜¡”‰•¢˜—
SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995
logic diagram (positive logic)
Serial Inputs
J
2
SH/ LD
CLK
CLR
Parallel Inputs
K
3
B
A
4
C
5
D
6
7
9
10
1
R
1R
R
1R
C1
R
1R
C1
1S
C1
1S
15
QA
R
1R
C1
1S
14
1S
13
QB
QC
12
QD
11
QD
Parallel Outputs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
£¤¥¦§£¨©ª
¦«¬­®(¬­¯­°±~²®­³¤§´!µ¤­¶#±°£§´!£%·„­¸'®(°±~¹‡­£®*±°
SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995
CLK
CLR
J
Serial
Inputs
K
SH/ LD
A
Parallel
Data
Inputs
H
L
H
L
B
C
D
QA
QB
Outputs
QC
QD
Clear
Serial Shift
Serial Shift
Load
Figure 1. Typical Clear, Shift, and Load Sequences
ºabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)»†
3Supply voltage, V0
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input
voltage,
V
I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. . . . . 7 5 V
¼Operating free-air
temperature range, T½A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C
3Storage temperature
5 to 70°C5
range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
¾¿ÀÁŽ¾ÃÄÅ
ÁÆÇÈÉ(ÇÈÊÈËÌ~ÍÉÈ·¿ŽÂÏ!пÈÑ#Ì˾ÂÏ!¾%ÒÈÓ É(ËÌÔȾɢÌË
SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
–2
mA
IOL
fclock
Low-level output current
20
mA
70
MHz
Õ tÖ w
Õ tsu
High-level input voltage
2
Clock frequency
CLK high
Setup time
Õ th
Hold time
TA
Operating free-air temperature
V
0
Pulse duration
Õ
4
CLR low
7.2
Data before CLK↑
3.5
SH/LD before CLK↑
8
CLR high before CLK↑
6
Data after CLK↑
1
SH/LD after CLK↑
0
V
ns
ns
ns
0
70
°C
×electrical
characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
Ø TEST CONDITIONS
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 2 mA
VOL
VCC = 4.5 V,
IOL = 20 mA
VCC = 5
5.5
5V
V,
VI = 7 V
5V
VCC = 5
5.5
V,
7V
VI = 2
2.7
VCC = 5
5.5
5V
V,
VI = 0
0.4
4V
VCC = 5.5 V,
VCC = 5.5 V
VO = 2.25 V
II
IIH
IIL
IO‡
ICCH
SH/LD
All others
SH/LD
All others
SH/LD
All others
MIN
Ø TYP†
MAX
UNIT
– 1.2
V
VCC – 2
V
0.35
0.5
0.2
0.1
40
20
–1
– 0.5
– 30
32
V
mA
µA
mA
–112
mA
51
mA
ICCL
VCC = 5.5 V
36
57
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
ÙÚÛÜÝÙÞßà
Üáâãä(âãåãæç~èäãéÚÝê!ëÚãì#çæÙÝê!Ù%í„ãî'ä(æç~ï‡ãÙä*çæ
SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995
ðswitching characteristics (see Figure 2)
PARAMETER
max
Õ tPLH
FROM
(INPUT)
Ø TO
(OUTPUT)
f
70
Õ tPHL
CLK
Õ tPHL
CLR
Õ tPLH
Ø
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX†
MIN
MAX
3
8.5
10.5
QD
4
8
QA thru QD
5
11.5
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303
MHz
2.5
Any Q
• DALLAS, TEXAS 75265
UNIT
ns
ns
ñòóôõŽñö÷ø
ôùúûü(úûýûþÿüû‡òŽõòû#ÿþñõ!ñ
û ü(þÿûñü¢ÿþ
SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
CL
(see Note A)
Ø Test
R1
Test
Point
From Output
Under Test
From Output
Under Test
RL
Test
Point
From Output
Under Test
Point
CL
(see Note A)
CL
(see Note A)
R2
LOAD CIRCUIT FOR
BI-STATE
Ø TOTEM-POLE
OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
1.3 V
3.5 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
1.3 V
1.3 V
t
Waveform 1
S1 Closed
(see Note B)
S1 Open
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
t
PZL
Waveform 2
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
0.3 V
w
h
1.3 V
1.3 V
t
0.3 V
t
su
Data
Input
3.5 V
High-Level
Pulse
1.3 V
t
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
0.3 V
PLZ
3.5 V
1.3 V
t
t
PHZ
PZH
VOL
0.3 V
VOH
1.3 V
3.5 V
1.3 V
Input
0.3 V
0V
t
1.3 V
t
0.3 V
PHL
PLH
VOH
In-Phase
Output
1.3 V
1.3 V
t
t
VOL
PLH
PHL
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
0CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
W
ARRANTED T O BE SUIT ABLE FOR USE IN LIFE-SUPPOR T DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA
TIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
0
In order to minimize risks associated with the customer’s applications, adequate design
safeguards
must be provided by the customer to minimize inherent or procedural hazards.
and operating
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
0Copyright  1998, Texas Instruments Incorporated