74AC11194
4–BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 – NOVEMBER 1989 – REVISED APRIL 1993
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DW OR N PACKAGE
Parallel-to-Serial, Serial-to-Parallel
Conversions
Left or Right Shifts
Parallel Synchronous Loading
Direct Overriding Clear
Temporary Data Latching Capability
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin VCC and GND Configurations to
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline Packages, and Standard
Plastic 300-mil DIPs
(TOP VIEW)
SR SER
QA
QB
GND
GND
GND
GND
QC
QD
SL SER
t
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
S0
S1
A
B
VCC
VCC
C
D
CLR
CLK
description
This bidirectional shift register features parallel outputs, right-shift and left-shift serial inputs,
operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of
operation:
Parallel (broadside) load
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Inhibit clocking (do nothing).
Synchronous parallel loading is accomplished by applying the 4 bits of data and taking both mode control inputs,
S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive
transition of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left
synchronously, and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when
both mode control inputs are low.
The 74AC11194 is characterized for operation from – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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POST OFFICE BOX 655303
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1
74AC11194
4–BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 – NOVEMBER 1989 – REVISED APRIL 1993
Function Table
OUTPUTS
INPUTS
CLEAR
MODE
S1
S0
CLOCK
SERIAL
PARALLEL
LEFT
RIGHT
A
B
C
D
QA
QB
QC
QD
L
X
X
X
X
X
X
X
X
X
L
L
L
L
H
X
X
L
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
H
H
↑
X
X
a
b
c
d
a
b
c
d
H
L
H
↑
X
H
X
X
X
X
H
QAn
QBn
QCn
H
L
H
↑
X
L
X
X
X
X
L
H
L
↑
H
X
X
X
X
X
QBn
QAn
QCn
QBn
QDn
QCn
H
H
H
L
↑
L
X
X
X
X
X
H
L
L
X
X
X
X
X
X
X
QBn
QAO
QCn
QBO
QDn
QCO
H
L
QDO
H = high level (steady state)
L = low level (steady state)
X = irrelevant (any input, including transitions)
↑ = transition from low to high level
a,b,c,d = the level of steady-state input at inputs A, B, C, or D, respectively.
QAO, QBO, QCO, QDO = the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were
established.
QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD respectively, before the most-recent ↑ transition of the clock.
timing clear, load, right-shift, inhibit, and clear sequences
CLK
Mode
Control
Inputs
S0
S1
CLR
Serial
Data
Inputs
Parallel
Data
Inputs
R
L
A
H
B
L
C
H
D
L
QA
QB
Outputs
QC
QD
Shift Right
CLR
2
Shift Left
Inhibit
CLR
Load
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•
74AC11194
4–BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 – NOVEMBER 1989 – REVISED APRIL 1993
logic symbol†
SRG4
12
CLR
R
20
S0
0
1
19
S1
11
CLK
M
C4
1
1
SR SER
3, 4D
10
SL SER
QB
8
3, 4D
13
D
QA
3
3, 4D
14
C
2
3, 4D
17
B
/2
1, 4D
18
A
0
3
QC
9
QD
2, 4D
logic diagram (positive logic)
Parallel Inputs
A
Mode
Control
Inputs
S0
S1
SR SER
CLK
CLR
19
B
17
18
C
D
14
13
20
10
1
1S
C1
1S
C1
1S
C1
1S
C1
1R
1R
1R
1R
R
R
R
R
SL SER
11
12
2
3
QA
8
QB
QC
9
QD
Parallel Outputs
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•
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74AC11194
4–BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 – NOVEMBER 1989 – REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
IOH
IOL
VI
VO
4
Low-level input voltage
MIN
NOM
MAX
3
5
5.5
V
3.15
3.85
0.9
1.35
V
1.65
VCC = 3 V
VCC = 4.5 V
Low-level output current
V
2.1
VCC = 4.5 V
VCC = 5.5 V
High-level output current
UNIT
–4
– 24
VCC = 5.5 V
VCC = 3 V
– 24
VCC = 4.5 V
VCC = 5.5 V
24
mA
12
mA
24
Input voltage
0
Output voltage
0
Dt/Dv
VCC
VCC
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
– 40
85
°C
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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V
V
74AC11194
4–BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 – NOVEMBER 1989 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = – 50 mA
VOH
IOH = – 4 mA
IOH = – 24 mA
IOH = – 75 mA{
IOL = 12 mA
IOL = 24 mA
II
ICC
Ci
IOL = 75 mA{
VI = VCC or GND
VI = VCC or GND,
VI = VCC or GND
TA = 25°C
TYP
MAX
MIN
3V
2.9
2.9
4.5 V
4.4
4.4
5.5 V
5.4
5.4
3V
2.58
2.48
4.5 V
3.94
3.8
5.5 V
4.94
4.8
5.5 V
IOL = 50 mA
VOL
MIN
UNIT
V
3.85
3V
0.1
0.1
4.5 V
0.1
0.1
5.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
5.5 V
0.36
0.44
5.5 V
IO = 0
MAX
V
1.65
5.5 V
± 0.1
±1
mA
5.5 V
8
80
mA
5V
4
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
PARAMETER
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK ↑
th
Hold time after CLK ↑
t
Recovery time
0
90
MIN
MAX
UNIT
0
90
MHz
CLK high
5.5
5.5
CLK low
5.5
5.5
CLR low
4.5
4.5
Select
5
5
Data
4
4
Select
1.5
1.5
Data
0.5
0.5
1
1
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•
ns
ns
ns
ns
5
74AC11194
4–BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 – NOVEMBER 1989 – REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
PARAMETER
fclock
tw
Clock frequency
0
Pulse duration
tsu
Setup time before CLK ↑
th
Hold time after CLK ↑
t
Recovery time
100
MIN
MAX
UNIT
0
100
MHz
CLK high
5
5
CLK low
5
5
CLR low
4.5
4.5
Select
4
4
Data
2.5
2.5
Select
1.5
1.5
1
1
1
1
Data
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
fmax
tPHL
tPLH
tPHL
TA = 25°C
MIN
TYP
MAX
TO
(OUTPUT)
CLK
Any Q
CLR
Any Q
MIN
MAX
90
UNIT
90
120
MHz
1
5.8
8.4
1
9.5
1
6.6
8.9
1
10.2
1.7
7.1
9.5
1.7
10.7
ns
MAX
UNIT
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
fmax
tPHL
tPLH
tPHL
TO
(OUTPUT)
CLK
Any Q
CLR
Any Q
TA = 25°C
MIN
TYP
MAX
MIN
100
130
100
0.8
3.9
6.2
0.8
6.8
1.1
4.4
6.6
1.1
7.7
1.5
4.6
7
1.5
7.8
MHz
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
6
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
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f = 1 MHz
TYP
UNIT
66
pF
74AC11194
4–BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 – NOVEMBER 1989 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
Timing Input
(see Note B)
From Output
Under Test
VCC
50%
0V
th
tsu
CL = 50 pF
(see Note A)
500 Ω
VCC
Data
Input
50%
50%
0V
SETUP AND HOLD TIMES
LOAD CIRCUIT
VCC
Input
(see Note B)
50%
50%
0V
VCC
High-Level
Input
50%
tPLH
50%
0V
In-Phase
Output
tw
Low-Level
Input
tPHL
50% VCC
VCC
50%
tPLH
tPHL
50%
0V
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
PROPAGATION DELAY TIMES
PULSE DURATION
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. For testing
fmax and pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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