ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com 14-BITS, 65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Check for Samples: ADS6142-HT FEATURES 1 • • • • • • • • • • • • • • SUPPORTS EXTREME TEMPERATURE APPLICATIONS • • • • • • • • APPLICATIONS • • • • • 802.16d/e Test and Measurement Instrumentation High Definition Video Medical Imaging Radar Systems 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 • Maximum Sample Rate: 65 MSPS 14-Bit Resolution with No Missing Codes 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off Parallel CMOS and Double Data Rate (DDR) LVDS Output Options Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400 mVPP Clock Duty Cycle Stabilizer Internal Reference with Support for External Reference No External Decoupling Required for References Programmable Output Clock Position and Drive Strength to Ease Data Capture 3.3-V Analog and 1.8-V to 3.3-V Digital Supply Down-Hole Drilling High Temperature Environment Wireless Communications Infrastructure Software Defined Radio Power Amplifier Linearization (1) Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Extreme (–40°C/210°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures. All devices are characterized and qualified for 1000 hours of continuous operating life at maximum rated temperature. Custom temperature ranges available DESCRIPTION The ADS6142 is a high performance and low power consumption 14-bit A/D converter with a sampling frequency of 65 MSPS. An internal high bandwidth sample and hold and a low jitter clock buffer help to achieve high SNR and high SFDR even at high input frequencies. The ADS6142 features coarse and fine gain options to improve SFDR performance at lower full-scale analog input ranges. The digital data outputs are either parallel CMOS or DDR (Double Data Rate) LVDS. Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, LVDS current, and internal termination programmability. The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some functions are configured using dedicated parallel pins so the device powers up to the desired state. The ADS6142 includes internal references while eliminating traditional reference pins and associated external decoupling. External reference mode is also supported. The ADS6142 is specified over the extreme temperature range (–40°C to 210°C). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. CLKP INP SHA INM VCM DRGND CLKOUTP CLOCK GEN 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 CLKM DRVDD AGND AVDD ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Digital Encoder and Serializer 14-Bit ADC Control Interface Reference CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M D12_D13_P D12_D13_M ADS6142 PDN SEN SDATA SCLK RESET LVDS MODE Table 1. ORDERING INFORMATION (1) (1) (2) 2 TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 210°C KGD (bare die) ADS6142SKGD1 NA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com BARE DIE INFORMATION DIE PAD SIZE DIE PAD COORDINATES DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION BOND PAD THICKNESS 70 x 70 µm See Table 2 11 mils Silicon with backgrind DRVSS Ti/Al-Cu/TiN 1100 nm DIE SIZE 2715 x 2460 µm 96.85 x 106.89 mils 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 0 0 Edge of Scribe Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 3 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Table 2. BOND PAD COORDINATES DESCRIPTION PAD NUMBER X MIN Y MIN X MAX Y MAX DRVDD 1 80.92 2065 150.92 2135 N/C 2 80.92 1984.5 150.92 2054.5 N/C 3 80.92 1904 150.92 1974 RESET 4 80.92 1823.5 150.92 1893.5 SCLK 5 80.92 1662.5 150.92 1732.5 SDATA 6 80.92 1582 150.92 1652 SEN 7 80.92 1501.5 150.92 1571.5 N/C AGND AGND AGND CLKP CLKP CLKM CLKM N/C N/C AGND AGND N/C INP INP INM INM N/C AGND AGND N/C AVDD AVDD VCM VCM N/C N/C N/C AVDD PDN N/C 4 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 N/C 8 80.92 1206.1 150.92 1276.1 9 80.92 1104.6 150.92 1174.6 10 80.92 1003.1 150.92 1073.1 11 80.92 901.6 150.92 971.6 12 80.92 800.1 150.92 870.1 13 80.92 698.6 150.92 768.6 14 80.92 597.1 150.92 667.1 15 80.92 495.6 150.92 565.6 464.1 16 80.92 394.1 150.92 17 80.92 292.6 150.92 362.6 18 262.5 80.92 332.5 150.92 19 358.365 80.92 428.365 150.92 20 454.23 80.92 524.23 150.92 21 550.095 80.92 620.095 150.92 22 645.96 80.92 715.96 150.92 23 741.825 80.92 811.825 150.92 24 837.69 80.92 907.69 150.92 25 933.555 80.92 1003.555 150.92 26 1029.42 80.92 1099.42 150.92 27 1125.285 80.92 1195.285 150.92 28 1221.15 80.92 1291.15 150.92 29 1317.015 80.92 1387.015 150.92 30 1412.88 80.92 1482.88 150.92 31 1508.745 80.92 1578.745 150.92 32 1604.61 80.92 1674.61 150.92 33 1700.475 80.92 1770.475 150.92 34 1796.34 80.92 1866.34 150.92 35 1892.205 80.92 1962.205 150.92 36 1988.07 80.92 2058.07 150.92 37 2083.935 80.92 2153.935 150.92 38 2179.8 80.92 2249.8 150.92 39 2404.08 455 2474.08 525 N/C 40 2404.08 535.5 2474.08 605.5 N/C 41 2404.08 616 2474.08 686 N/C 42 2404.08 696.5 2474.08 766.5 D0 43 2402.925 829.71 2472.925 899.71 N/C 44 2402.925 945.28 2472.925 1015.28 D1 45 2402.925 1060.85 2472.925 1130.85 D2 46 2402.925 1162.21 2472.925 1232.21 SUBST 47 2402.925 1277.78 2472.925 1347.78 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Table 2. BOND PAD COORDINATES (continued) DESCRIPTION PAD NUMBER X MIN Y MIN X MAX Y MAX D3 48 2402.925 1393.35 2472.925 1463.35 D4 49 2402.925 1494.71 2472.925 1564.71 SUBST 50 2402.925 1610.28 2472.925 1680.28 D5 51 2402.925 1725.85 2472.925 1795.85 D6 52 2402.925 1827.21 2472.925 1897.21 N/C 53 2402.925 1942.78 2472.925 2012.78 D7 54 2402.925 2058.35 2472.925 2128.35 OVR SUBST CLKOUT N/C SUBST N/C D8 SUBST D9 D10 SUBST D11 D12 SUBST D13 SUBST DRVDD 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 SUBST SUBST 55 2205 2229.08 2275 2299.08 56 2103.5 2229.08 2173.5 2299.08 57 1980.79 2227.925 2050.79 2297.925 58 1865.22 2227.925 1935.22 2297.925 59 1749.65 2227.925 1819.65 2297.925 60 1648.29 2227.925 1718.29 2297.925 61 1532.72 2227.925 1602.72 2297.925 62 1417.15 2227.925 1487.15 2297.925 63 1315.79 2227.925 1385.79 2297.925 64 1200.22 2227.925 1270.22 2297.925 65 1084.65 2227.925 1154.65 2297.925 66 983.29 2227.925 1053.29 2297.925 67 867.72 2227.925 937.72 2297.925 68 752.15 2227.925 822.15 2297.925 69 650.79 2227.925 720.79 2297.925 70 535.22 2227.925 605.22 2297.925 71 419.65 2227.925 489.65 2297.925 72 322 2229.08 392 2299.08 73 241.5 2229.08 311.5 2299.08 Substrate should be connected to DRVSS Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 5 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) VI VALUE UNIT Supply voltage range, AVDD –0.3 to 3.9 V Supply voltage range, DRVDD –0.3 to 3.9 V Voltage between AGND and DRGND –0.3 to 0.3 V Voltage between AVDD to DRVDD –0.3 to 3.3 V –0.3 to 2 V –0.3 to minimum ( 3.6, AVDD + 0.3) V Voltage applied to VCM pin (in external reference mode) Voltage applied to analog input pins, INP and INM –0.3 to (AVDD + 0.3) V TJ Operating junction temperature range -40 to 210 °C Tstg Storage temperature range –65 to 210 °C Voltage applied to analog input pins, CLKP and CLKM 6 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) TJ = -40°C to 125°C MIN TJ = 210°C NOM MAX MIN NOM MAX UNIT SUPPLIES AVDD DRVDD Analog supply voltage Output buffer supply voltage CMOS Interface LVDS Interface 3 3.3 3.6 3 3.3 3.6 V 1.65 1.8 to 3.3 3.6 1.65 1.8 to 3.3 3.6 V 3 3.3 3.6 3 3.3 3.6 V ANALOG INPUTS 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Differential input voltage range VIC 2 1.5 ± 0.1 Input common-mode voltage Voltage applied on VCM in external reference mode 1.45 1.5 2 Vpp 1.5 ± 0.1 1.55 1.45 1.5 V 1.55 V CLOCK INPUT Input clock sample rate, FS 1 Sine wave, ac-coupled Input clock amplitude differential (VCLKP – VCLKM) 0.4 LVPECL, ac-coupled LVDS, ac-coupled LVCMOS, ac-coupled Input Clock duty cycle 65 1.5 1 0.4 ± 0.8 ± 0.8 ± 0.35 ± 0.35 3.3 35% 65 MSPS 1.5 50% 65% 35% Vpp 3.3 50% 65% DIGITAL OUTPUTS Output buffer drive strength (1) For CLOAD ≤ 5 pF and DRVDD ≥ 2.2 V DEFAULT strength DEFAULT strength For CLOAD > 5 pF and DRVDD ≥ 2.2 V MAXIMUM strength MAXIMUM strength For DRVDD < 2.2 V MAXIMUM strength MAXIMUM strength 10 10 5 5 10 10 100 100 CMOS Interface, maximum buffer strength CLOAD Maximum external load LVDS Interface, without capacitance from each internal termination output pin to DRGND LVDS Interface, with internal termination RLOAD Differential load resistance (external) between the LVDS output pairs TJ Operating junction temperature range (1) -40 125 pF Ω 210 °C See Output Buffer Strength Programmability in the application section. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 7 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. TJ = -40°C to 125°C PARAMETER MIN RESOLUTION TYP TJ = 210°C MAX MIN TYP MAX UNIT 14 14 Bits 2 2 VPP >1 >1 MΩ ANALOG INPUT Differential input voltage range Differential input resistance (dc), see Figure 37 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Differential input capacitance, see Figure 38 7 7 450 300 MHz 92 95 μA Internal reference bottom voltage 1 1 V Internal reference top voltage 2 2 Analog input bandwidth Analog input common-mode current (per input pin of each ADC) pF REFERENCE VOLTAGES VREFB VREFT ΔVREF VCM Internal reference error (VREFT–VREFB) -30 Common-mode output voltage VCM Output current capability ±5 30 -55 ±5 1.5 1.5 4 4 V 55 mV V mA DC ACCURACY No missing codes EO Specified Offset error -11 Offset error temperature coefficient ±2 Specified 11 -13 0.04 ±10 13 0.06 mV mV/°C There are two sources of gain error – internal reference inaccuracy and channel gain error EGREF EGCHAN Gain error due to internal reference inaccuracy alone, (ΔVREF /2) % Gain error of channel alone -1 (1) Differential nonlinearity INL Integral nonlinearity 1 -1 ±0.3 Channel gain error temperature coefficient DNL 0.6 0.65 1 ±0.3 % FS % FS Δ%/°C 0.005 -0.95 0.5 2 -0.99 ±0.5 2.5 LSB -10 ±2 10 -18 ±6 18 LSB POWER SUPPLY IAVDD IDRVDD IDRVDD (1) (2) (3) 8 0.75 0.76 mA Digital supply current, CMOS interface, DRVDD = 1.8 V, No load capacitance, Fin= 2 MHz (2) Analog supply current 4 4 mA Digital supply current, LVDS interface, DRVDD = 3.3 V, with 100-Ω external termination 21 48 mA Total power, CMOS, DRVDD = 3.3 V (3) 418 450 422 500 mW Global power down 30 60 30 70 mW Specified by design and characterization; not tested in production. In CMOS mode, the DRVDD current scales with the sampling frequency and the load capacitance on the output pins (see Figure 30). The maximum DRVDD current depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance is 10 pF. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. PARAMETER TEST CONDITIONS TJ = -40°C to 125°C MIN TYP TJ = 210°C MAX MIN TYP 57.5 74 MAX UNIT DYNAMIC AC CHARACTERISTICS Fin = 10 MHz 74.7 Fin = 50 MHz Fin = 170 MHz 61.5 0 dB Gain 74.4 72.7 dBFS 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 SNR Signal-to-noise ratio, CMOS 74.4 Fin = 70 MHz Fin = 230 MHz 3.5 dB Coarse gain 71.8 0 dB Gain 71.7 65.5 3.5 dB Coarse gain 70.9 63 Fin = 10 MHz 75 Fin = 50 MHz SNR Signal-to-noise ratio, LVDS Fin = 170 MHz Fin = 230 MHz RMS output noise 74.6 Fin = 70 MHz 68 0 dB Gain 72.9 3.5 dB Coarse gain 72.1 0 dB Gain 3.5 dB Coarse gain 1.05 Fin = 10 MHz 74.6 60.5 ENOB Effective number of bits SFDR Spurious free dynamic range 56.5 71.5 0 dB Gain 70.6 56 3.5 dB Coarse gain 70.4 57 74.4 67 74.4 0 dB Gain 72.4 3.5 dB Coarse gain 71.9 0 dB Gain 70.5 3.5 dB Coarse gain 70.5 Fin = 70 MHz 10.5 12 Fin = 10 MHz 95 Fin = 50 MHz 89 Fin = 70 MHz Fin = 230 MHz 64 74 70 9.4 12 66 77 82 3.5 dB Coarse gain 84 0 dB Gain 79 58 3.5 dB Coarse gain 82 60 Bits dBc 93 Fin = 50 MHz 88 Fin = 70 MHz Fin = 230 MHz 78 dBFS 56 0 dB Gain Fin = 10 MHz THD Total harmonic distortion Fin = 170 MHz dBFS 74.9 Fin = 50 MHz Fin = 170 MHz LSB 74 3.5 dB Coarse gain Fin = 70 MHz Fin = 230 MHz 74.0 72.2 Fin = 50 MHz Fin = 170 MHz 60 0 dB Gain Fin = 10 MHz SINAD Signal-to-noise and distortion ratio LVDS dBFS 74.1 Fin = 70 MHz Fin = 230 MHz 75 71.2 Inputs tied to common-mode Fin = 170 MHz 62 72 Fin = 50 MHz SINAD Signal-to-noise and distortion ratio CMOS 74.6 72 85 0 dB Gain 80 3.5 dB Coarse gain 82 0 dB Gain 3.5 dB Coarse gain 66 75 dBc 76 56 78.5 59 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 9 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. PARAMETER TEST CONDITIONS TJ = -40°C to 125°C MIN Fin = 10 MHz TYP 73 93 0 dB Gain 86 66 76 3.5 dB Coarse gain 87 0 dB Gain 79 58 3.5 dB Coarse gain 81 60 Fin = 10 MHz Worst spur (other than HD2, HD3) 89 Fin = 70 MHz Fin = 230 MHz UNIT 95 Fin = 50 MHz Fin = 170 MHz MAX dBc 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Fin = 230 MHz HD3 Third harmonic distortion MIN 96 Fin = 70 MHz Fin = 170 MHz TJ = 210°C MAX 98 Fin = 50 MHz HD2 Second harmonic distortion TYP 75 86 70 84 0 dB Gain 82 3.5 dB Coarse gain 84 0 dB Gain 79 75 3.5 dB Coarse gain 82 74 Fin = 10 MHz 97 Fin = 50 MHz 96 Fin = 70 MHz 95 Fin = 170 MHz 91 dBc dBc Fin = 230 MHz 90 IMD 2-Tone intermodulation distortion F1 = 185 MHz, F2 = 190 MHz, Each tone at -7 dBFS 91 90 dBFS Input overload recovery Recovery to within 3% (of final value) for 6-dB overload with sine wave input 1 1 clock cycles PSRR AC Power supply rejection ratio For 100 mVpp signal on AVDD supply 49 48 dBc 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com DIGITAL CHARACTERISTICS The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1, AVDD = 3.3 V PARAMETER DIGITAL INPUTS PDN, SCLK, SDATA, and SEN TJ = -40°C to 125°C TEST CONDITIONS MIN TYP TJ = 210°C MAX MIN TYP MAX UNIT (1) High-level input voltage 2.4 2.4 0.8 0.8 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Low-level input voltage V V High-level input current 33 33 μA Low-level input current –33 –33 μA 4 4 pF High-level output voltage DRVDD DRVDD V Low-level output voltage 0 0 V 2 2 pF High-level output voltage 1375 1375 mV Low-level output voltage 1025 1025 mV 350 mV 1200 1200 mV 2 2 pF Input capacitance DIGITAL OUTPUTS CMOS INTERFACE, DRVDD = 1.8 to 3.3 V Output capacitance Output capacitance inside the device, from each output to ground DIGITAL OUTPUTS LVDS INTERFACE, DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω (2) |VOD| Output differential voltage VOS Output offset voltage, single-ended Common-mode voltage of OUTP, OUTM Output capacitance Output capacitance inside the device, from either output to ground (1) (2) 225 350 225 SCLK and SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins, analog voltage needs to be applied as per Table 3 & Table 4 IO Refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 11 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 125°C or 210°C as indicated, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data sheet. PARAMETER TEST CONDITIONS TJ = -40°C to 125°C MIN TYP TJ = 210°C MAX MIN TYP MAX UNIT ta Aperture delay 1.5 ns tj Aperture jitter 150 fs rms 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Wake-up time (to valid data) From global power down 15 μs From standby 15 μs CMOS 100 ns LVDS 200 From output buffer disable Latency 9 ns clock cycles DDR LVDS MODE (4), DRVDD = 3.3 V tsu Data setup time (5) Data valid (6) to zero-cross of CLKOUTP 5.8 5.6 ns th Data hold time (5) Zero-cross of CLKOUTP to data becoming invalid (6) 1.3 1.5 ns tPDI Clock propagation delay Input clock rising edge zero-cross to output clock rising edge zero-cross 6.2 7.2 ns LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTP-CLKOUTM), 10 ≤ Fs ≤ 125 MSPS 46% 46% tr tf Data rise time, Data fall time Rise time measured from –50 mV to 50 mV, Fall time measured from 50 mV to –50 mV, 1 ≤ Fs ≤ 125 MSPS 112 116 ps tCLKRISE tCLKFALL Output clock rise time, Output clock fall time Rise time measured from –50 mV to 50 mV, Fall time measured from 50 mV to –50 mV, 1 ≤ Fs ≤ 125 MSPS 112 116 ps 8 9 ns PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.3 V, default output buffer drive strength (7) (8) tsu Data setup time (5) Data valid to 50% of CLKOUT rising edge th Data hold time (5) 50% of CLKOUT rising edge to data becoming invalid (8) 6.5 6.8 ns tPDI Clock propagation delay Input clock rising edge zero-cross to 50% of CLKOUT rising edge 7.3 8.3 ns Output clock duty cycle Duty cycle of output clock (CLKOUT), 10 ≤ Fs ≤ 125 MSPS 42% 42% tr tf Data rise time, Data fall time Rise time measured from 20% to 80% of DRVDD, Fall time measured from 80% to 20% of DRVDD, 1 ≤ Fs ≤ 125 MSPS 1.9 2.1 ns tCLKRISE tCLKFALL Output clock rise time, Output clock fall time Rise time measured from 20% to 80% of DRVDD, Fall time measured from 80% to 20% of DRVDD, 1 ≤ Fs ≤ 125 MSPS 1.9 2.1 ns (1) (2) (3) (4) (5) (6) (7) (8) 12 Timing parameters are specified by design and not tested in production. CL is the Effective external single-ended load capacitance between each output pin and ground. IO Refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to a logic high of +100 mV and logic low of –100 mV. For DRVDD < 2.2 V, it is recommended to use an external clock for data capture and NOT the device output clock signal (CLKOUT). See Parallel CMOS interface in the application section. Data valid refers to a logic high of 2 V (1.7 V) and logic low of 0.8 V (0.7 V) for DRVDD = 3.3 V (2.5 V). Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com ADD6142-HT Operating Life Derating Chart 10000000.00 1000000.00 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Estimated Life (Hours) 100000000.00 100000.00 10000.00 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 Continuous TJ (°C) (1) See data sheet for absolute maximum and minimum recommended operating conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). (3) The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wearout for the specific device process and design characteristics. Figure 1. ADS6142-HT Operating Life Derating Chart Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 13 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com N+4 N+3 N+2 N+12 N+11 N+10 N+1 Sample N N+9 Input Signal ta CLKP Input Clock 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 CLKM CLKOUTM CLKOUTP tsu 9 Clock Cycles DDR LVDS Output Data DXP, DXM O O E E – Even Bits D0,D2,D4,D6,D8,D10,D12 O – Odd Bits D1,D3,D5,D7,D9,D11,D13 E O O E N–8 N–9 O E N–7 E O N–6 O E N–5 E O E N N–1 tPDI th O O E E N+2 N+1 tPDI CLKOUT tsu Parallel CMOS 9 Clock Cycles Output Data D0–D13 N–8 N–9 N–7 N–6 N–5 N–1 N th N+1 N+2 Figure 2. Latency Input Clock CLKM CLKM Input Clock CLKP CLKP tPDI tPDI Output Clock CLKOUTM Output Clock CLKOUTP CLKOUT tsu th tsu th th tsu Output Data Pair (1) (2) Dn Dn_Dn+1_P, Dn_Dn+1_M Dn (1) Dn+1 Output Data Dn Dn (1) – Bits D0, D2, D4, D6, D8, D10, D12 (1) Dn+1 – Bits D1, D3, D5, D7, D9, D11, D13 Figure 3. LVDS Mode Timing 14 (2) Dn – Bits D0–D13 Figure 4. CMOS Mode Timing Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com DEVICE PROGRAMMING MODES The ADS6142 has several features that can be easily configured using either parallel interface control or serial interface programming. USING SERIAL INTERFACE PROGRAMMING ONLY To program using the serial interface, the internal registers must first be reset to their default values, and the RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of the ADC. The registers are reset either by applying a pulse on the RESET pin or by a high setting on the <RST> bit (D4 in register 0x00). The Serial Interface section describes register programming and register reset in more detail. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 USING PARALLEL INTERFACE CONTROL ONLY To control the device using the parallel interface, keep RESET tied high (AVDD). Now SEN, SCLK, SDATA, and PDN function as parallel interface control pins. These pins can be used to directly control certain modes of the ADC by connecting them to the correct voltage levels (as described in Table 3 to Table 5). There is no need to apply a reset pulse. Frequently used functions are controlled in this mode — standby, selection between LVDS/CMOS output format, internal/external reference, and 2s complement/straight binary output format. AVDD (5/8) AVDD 3R (5/8) AVDD GND 2R AVDD (3/8) AVDD (3/8) AVDD 3R To Parallel Pin (SCLK, SDATA, SEN) GND Figure 5. Simple Scheme to Configure Parallel Pins DESCRIPTION OF PARALLEL PINS Table 3. SCLK (Analog Control Pin) SCLK 0 DESCRIPTION Internal reference and 0 dB gain (full-scale = 2 VPP) (3/8) AVDD External reference and 0 dB gain (full-scale = 2 VPP) (5/8) AVDD External reference and 3.5 dB coarse gain (full-scale = 1.34 VPP) AVDD Internal reference and 3.5 dB coarse gain (full-scale = 1.34 VPP) Table 4. SEN (Analog Control Pin) SEN DESCRIPTION 0 2s Complement format and DDR LVDS interface (3/8) AVDD Straight binary format and DDR LVDS interface (5/8) AVDD Straight binary and parallel CMOS interface AVDD 2s Complement format and parallel CMOS interface Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 15 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Table 5. SDATA, PDN (Digital Control Pins) SDATA PDN Low Low DESCRIPTION Normal operation Low High (AVDD) High (AVDD) Low High (AVDD) High (AVDD) Standby - only the ADC is powered down Output buffers are powered down, fast wake-up time Global power down. ADC, internal reference, and output buffers are powered down, slow wake-up time SERIAL INTERFACE 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET (of width greater than 10 ns). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in multiples of 16-bit words within a single active SEN pulse. The first 5 bits form the register address and the remaining 11 bits form the register data. The interface can work with a SCLK frequency from 20 MHz down to very low speeds (a few hertz) and also with a non-50% SCLK duty cycle. REGISTER ADDRESS SDATA A4 A3 A2 A1 REGISTER DATA A0 D10 D9 D8 D7 D6 D5 D4 tDSU tSCLK SCLK D3 D2 D1 D0 tDH tSLOADH SEN RESET tSLOADS Figure 6. Serial Interface Timing Diagram REGISTER INITIALIZATION After power-up, the internal registers must be reset to their default values. This is done in one of two ways: 1. Either through a hardware reset by applying a high-going pulse on the RESET pin (width greater than 10 ns) as shown in Figure 6. OR 2. By applying a software reset. Using the serial interface, set the <RST> bit (D4 in register 0x00) to high. This initializes the internal registers to their default values and then self-resets the <RST> bit to low. In this case the RESET pin is kept low. 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com SERIAL INTERFACE TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 210°C, AVDD = DRVDD = 3.3 V (unless otherwise noted) MIN TYP MAX UNIT > DC 20 MHz fSCLK SCLK Frequency = 1/tSCLK tSLOADS SEN to SCLK Setup time 25 ns tSLOADH SCLK to SEN Hold time 25 ns tDSU SDATA Setup time 25 ns tDH SDATA Hold time 25 ns 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 RESET TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN t1 Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active t2 Reset pulse width t3 tPO TYP MAX UNIT 5 ms Pulse width of active RESET signal 10 ns Register write delay Delay from RESET disable to SEN active 25 Power-up time Delay from power-up of AVDD and DRVDD to output stable 6.5 ns ms Power Supply AVDD, DRVDD t1 RESET t2 t3 SEN NOTE: A high-going pulse on the RESET pin is required in serial interface mode in the case of initialization through a hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure 7. Reset Timing Diagram Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 17 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com SERIAL REGISTER MAP Table 6 gives a summary of all the modes that can be programmed through the serial interface. Table 6. Summary of Functions Supported by Serial Interface (1) REGISTER ADDRESS IN HEX D9 D8 00 <COARSE GAIN> Coarse gain <LVDS CMOS> LVDS or CMOS Output interface 0 0 <REF> Internal or external Reference 04 <DATAOUT POSN> Output data position control <CLKOUT EDGE> Output clock edge control <CLKOUT POSN> Output clock position control 0 0 09 Bit-wise or Byte-wise control 0 0 0 0 0A <DATA FORMAT> 2s Complemen t or straight binary 0 0 0E 0F 18 D7 D6 D5 D4 D3 D2 D1 D0 <RST> Software reset 0 <PDN CLKOUT> Output clock buffer powered down 0 <STBY> ADC Power down 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 D10 <PDN OBUF> Output buffers powered down 0C (1) (2) REGISTER FUNCTIONS A4 - A0 0B (2) <TEST PATTERNS> <CUSTOM LOW> Custom pattern lower 9 bits <FINE GAIN> Fine gain 0 to 6dB 0 0 LVDS Termination LVDS Internal termination control for output data and clock 0 0 0 0 0 <DRIVE STRENGTH> CMOS output buffer drive strength control <CUSTOM HIGH> Custom pattern upper 5 bits <LVDS CURRENT> LVDS Current control 0 0 <CURRENT DOUBLE> LVDS current double 0 0 The unused bits in each register (shown by blank cells in above table) must be programmed as ‘0’. Multiple functions in a register can be programmed in a single write operation. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com DESCRIPTION OF SERIAL REGISTERS Each register function is explained in detail. Table 7. A4–A0 (hex) 00 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 <PDN OBUF> Output buffers powered down <COARSE GAIN> Coarse gain <LVDS CMOS> LVDS or CMOS Output interface 0 0 <REF> Internal or external reference <RST> Software reset 0 <PDN CLKOUT> Output clock buffer powered down 0 <STBY> ADC Power down 0 1 D2 0 1 D4 1 D5 0 1 D8 0 1 D9 0 1 D10 0 1 <STBY> Power down modes 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 D0 Normal operation Device enters standby mode where only ADC is powered down. <PDN CLKOUT> Power down modes Output clock is active (on CLKOUT pin) Output clock buffer is powered down and becomes three-stated. Data outputs are unaffected. <RST> Software reset applied - resets all internal registers and the bit self-clears to 0. <REF> Reference selection Internal reference enabled External reference enabled <LVDS CMOS> Output Interface selection Parallel CMOS interface DDR LVDS Interface <COARSE GAIN> Gain programming 0 dB Coarse gain 3.5 dB Coarse gain <PDN OBUF> Power down modes Output data and clock buffers enabled Output data and clock buffers disabled Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 19 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Table 8. A4–A0 (hex) 04 D8 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 <DATAOUT POSN> Output data position control <CLKOUT EDGE> Output Clock edge control <CLKOUT POSN> Output clock position control 0 0 0 0 0 0 0 0 <CLKOUT POSN> Output clock position control Default output clock position after reset. The setup/hold timings for this clock position are specified in the timing specifications table. 1 Output clock shifted (delayed) by 400 ps D9 0 1 D10 0 1 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 0 <CLKOUT EDGE> Use rising edge to capture data Use falling edge to capture data <DATAOUT_POSN> Default position (after reset) Data transition delayed by half clock cycle with respect to default position Table 9. A4–A0 (hex) 09 D10 0 1 20 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit-wise or Byte-wise control 0 0 0 0 0 0 0 0 0 0 Bit-wise or byte-wise selection (DDR LVDS mode only) Bit-wise sequence - Even data bits (D0, D2, D4,..D12) are output at the rising edge of CLKOUTP and odd data bits (D1, D3, D5,..D13) at the falling edge of CLKOUTP Byte-wise sequence - Lower 7 data bits (D0-D7) are output at the rising edge of CLKOUTP and upper 7 data bits (D8-D13) at the falling edge of CLKOUTP Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Table 10. A4–A0 (hex) 0A D7-D5 D10 D9 D8 <DF> 2s Complement or straight binary 0 0 001 All zeros - <D13:D0> = 0x0000 010 All ones - <D13:D0> = 0x3FFF 101 110 111 D10 0 1 D5 <TEST PATTERNS> D4 D3 D2 D1 D0 0 0 0 0 0 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Normal operation - <D13:D0> = ADC output 100 D6 Test patterns 000 011 D7 Toggle pattern - <D13:D0> toggles between 0x2AAA and 0x1555 Digital ramp - <D13:D0> increments from 0x0000 to 0x3FFF by one code every cycle Custom pattern - <D13:D0> = contents of CUSTOM PATTERN registers Unused Unused <DATA FORMAT> 2s Complement Straight binary Table 11. A4–A0 (hex) 0B D10 D9 D8 D7 D6 D5 D4 D3 D2 <CUSTOM LOW> Lower 9 bits of custom pattern D1 D0 0 0 D1 D0 Table 12. A4–A0 (hex) 0C Reg 0B D10-D2 Reg 0C D4-D0 D10-D8 000 001 010 011 D10 D9 D8 <FINE GAIN> Fine gain 0 to 6dB D7 D6 D5 0 0 0 D4 D3 D2 <CUSTOM HIGH> Upper 5 bits of custom pattern <CUSTOM LOW> - Specifies lower 9 bits of custom pattern <CUSTOM HIGH> - Specifies upper 5 bits of custom pattern <FINE GAIN> Gain programming 0 dB Gain 1 dB Gain 2 dB Gain 3 dB Gain 100 4 dB Gain 101 5 dB Gain 110 6 dB Gain 111 Unused Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 21 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Table 13. A4–A0 (hex) D10 0E 0 D1-D0 D0 1 D1 0 1 D3-D2 00 01 10 11 D9-D4 D9-D7 000 001 010 011 100 101 110 111 D6-D4 000 001 010 011 100 22 D8 D7 D6 D5 D4 <LVDS TERMINATION> LVDS Internal termination control for output data and clock D3 D2 <LVDS CURRENT> LVDS Current control D1 D0 <CURRENT DOUBLE> LVDS Current double <CURRENT DOUBLE> LVDS current programming LVDS Data buffer current control Default current, set by <LVDS_CURR> 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 0 D9 2x LVDS Current set by <LVDS_CURR> LVDS Clock buffer current control Default current, set by <LVDS_CURR> 2x LVDS Current set by <LVDS_CURR> <LVDS CURRENT> LVDS current programming 3.5 mA 2.5 mA 4.5 mA 1.75 mA LVDS internal termination <DATA TERM> Internal termination for LVDS output data bits No internal termination 300 Ω 185 Ω 115 Ω 150 Ω 100 Ω 80 Ω 65 Ω <CLKOUT TERM> Internal termination for LVDS output clock No internal termination 300 Ω 185 Ω 115 Ω 150 Ω 101 100 Ω 110 80 Ω 111 65 Ω Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Table 14. A4–A0 (hex) D10 D9 D8 0F 0 0 0 D7-D4 D7 D6 D5 D4 <DRIVE STRENGTH> CMOS Output buffer drive strength control D3 D2 D1 D0 0 0 0 0 <DRIVE STRENGTH> Output buffer drive strength controls 0101 WEAKER than default drive 0000 DEFAULT drive strength 1111 STRONGER than default drive strength (recommended for load capacitances > 5 pF) 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 1010 MAXIMUM drive strength (recommended for load capacitances > 5 pF) Other Do not use combinations Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 23 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 0 SFDR = 83 dBc SINAD = 71.2 dBFS SNR = 71.9 dBFS THD = 79.8 dBc −20 Amplitude − dB −40 −60 −80 −100 −120 −60 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Amplitude − dB −40 fIN1 = 190 MHz, –7 dBFS fIN2 = 185 MHz, –7 dBFS 2-Tone IMD = –88 dBFS SFDR = –92 dBFS −20 −80 −100 −120 −140 −140 −160 −160 0 10 20 30 f − Frequency − MHz 0 10 Figure 8. SNR vs INPUT FREQUENCY 74 92 88 84 80 76 Gain = 0 dB 72 Gain = 0 dB 72 Gain = 3.5 dB SNR − dBFS SFDR − dBc G058 76 96 70 Gain = 3.5 dB 68 66 68 64 64 60 62 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 G060 Figure 11. SFDR vs INPUT FREQUENCY (LVDS interface) 100 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G059 Figure 10. SNR vs INPUT FREQUENCY (LVDS interface) 76 96 74 92 Gain = 0 dB 88 72 Gain = 3.5 dB 84 80 76 SNR − dBFS SFDR − dBc 30 Figure 9. SFDR vs INPUT FREQUENCY 100 20 f − Frequency − MHz G057 Gain = 0 dB 72 70 Gain = 3.5 dB 68 66 68 64 64 60 62 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 G061 Figure 12. 24 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G062 Figure 13. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS 95 76 Input adjusted to get −1dBFS input Input adjusted to get −1dBFS input 74 90 3 dB SINAD − dBFS 6 dB 80 1 dB 0 dB 75 5 dB 2 dB 70 0 dB 1 dB 72 70 68 3 dB 66 4 dB 64 4 dB 65 5 dB 62 60 100 200 300 400 fIN − Input Frequency − MHz 500 0 100 200 G063 Figure 14. fIN = 70.1 MHz DRVDD = 3.3 V 79 104 78 86 84 82 80 3.0 77 76 SNR 75 SNR − dBFS SFDR − dBc 88 74 73 3.1 3.2 3.3 3.4 3.5 fIN = 10.1 MHz AVDD = 3.3 V 75 100 74 98 72 94 71 2.0 2.2 2.4 2.6 76 70 SNR SFDR 100 72 90 66 64 62 fIN = 70 MHz -55 25 125 3.4 70 3.6 G066 210 110 74 70 74 72 3.2 PERFORMANCE vs INPUT AMPLITUDE 76 68 78 3.0 Figure 17. 60 SFDR − dBc, dBFS 80 2.8 DRVDD − Supply Voltage − V G065 SNR- - dBFs SFDR - - dBc 82 73 SFDR 96 PERFORMANCE vs TEMPERATURE 84 76 SNR Figure 16. 86 77 102 92 1.8 72 3.6 AVDD − Supply Voltage − V 88 G064 PERFORMANCE vs DRVDD SFDR 90 500 106 80 SFDR − dBc 92 400 Figure 15. PERFORMANCE vs AVDD 94 300 fIN − Input Frequency − MHz SNR − dBFS 0 96 6 dB 90 SFDR (dBFS) 85 80 80 75 SNR (dBFS) 70 70 60 65 SNR − dBFS 60 2 dB 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 SFDR − dBc 85 SFDR (dBc) 50 60 40 30 −60 55 fIN = 20.1 MHz −50 T - Temperature - °C −40 −30 −20 −10 50 0 Input Amplitude − dBFS Figure 18. G068 Figure 19. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 25 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs CLOCK AMPLITUDE fIN = 20.1 MHz 79 SFDR 90 SNR 75 74 82 80 0.5 86 1.0 1.5 2.0 2.5 82 73 78 72 73 74 72 3.0 70 Input Clock Amplitude − VPP 30 35 40 45 70 65 70 G070 PERFORMANCE IN EXTERNAL REFERENCE MODE 95 82 fIN = 20.1 MHz External Reference Mode 93 20 15 5 0 SFDR − dBc Occurence − % 60 80 SFDR 25 10 91 78 89 76 SNR 87 85 1.30 8202 8203 8204 8205 8206 8207 8208 8209 8210 8211 Output Code 1.35 G071 Figure 22. 26 55 Figure 21. RMS (LSB) = 1.041 30 50 Input Clock Duty Cycle − % G069 OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE 35 71 fIN = 10.1 MHz Figure 20. 40 74 SNR 1.40 1.45 1.50 1.55 VVCM − VCM Voltage − V 1.60 SNR − dBFS 84 75 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 76 86 76 90 77 88 77 SFDR 94 78 SFDR − dBc 92 SNR − dBFS 94 SFDR − dBc PERFORMANCE vs INPUT CLOCK DUTY CYCLE 98 80 SNR − dBFS 96 74 1.65 72 1.70 G072 Figure 23. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS - LOW SAMPLING FREQUENCIES All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FS = 40 MSPS SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 100 76 96 74 Gain = 0 dB 72 84 SNR − dBFS 88 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 SFDR − dBc 92 Gain = 3.5 dB 80 76 72 Gain = 3.5 dB 68 66 Gain = 0 dB 68 70 64 64 60 62 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G073 Figure 24. G074 Figure 25. FS = 25 MSPS SFDR vs INPUT FREQUENCY 100 SNR vs INPUT FREQUENCY 76 74 90 SNR − dBFS SFDR − dBc 72 Gain = 3.5 dB 80 70 Gain = 0 dB 68 Gain = 3.5 dB 66 Gain = 0 dB 60 70 64 50 62 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 G075 Figure 26. 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G076 Figure 27. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 27 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com COMMON PLOTS All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) POWER DISSIPATION vs SAMPLING FREQUENCY (DDR LVDS and CMOS) COMMON-MODE REJECTION RATIO vs FREQUENCY 0.8 0.7 PD − Power Dissipation − W 0 −10 −20 −40 −50 −60 −70 −80 0.6 0.5 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 CMRR − dBc −30 fIN = 2.5 MHz CL = 5 pF LVDS 0.4 0.3 CMOS 0.2 0.1 −90 0.0 −100 0 50 100 150 200 250 0 300 f − Frequency − MHz 25 50 75 100 fS − Sampling Frequency − MSPS G077 Figure 28. 125 G078 Figure 29. DRVDD current vs SAMPLING FREQUENCY ACROSS LOAD CAPACITANCE (CMOS) 30 1.8 V, No Load DRVDD Current − mA 25 1.8 V, 5 pF 20 3.3 V, No Load 3.3 V, 5 pF 15 3.3 V, 10 pF 10 5 0 0 25 50 75 100 fS − Sampling Frequency − MSPS 125 G079 Figure 30. 28 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Contour Plots Across Input and Sampling Frequencies 125 120 90 72 78 81 66 69 84 84 63 100 75 81 87 90 84 90 87 70 72 78 90 87 80 66 60 69 81 63 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 fS - Sampling Frequency - MSPS 110 75 84 84 87 78 60 75 84 50 90 69 72 66 40 93 30 25 10 50 78 81 84 150 100 75 63 200 250 300 400 350 60 450 500 fIN - Input Frequency - MHz 60 80 75 70 65 85 90 95 SFDR - dBc M0049-15 Figure 31. SFDR Contour (no gain, Fs = 2 VPP) 125 120 84 87 87 87 84 75 78 81 fS - Sampling Frequency - MSPS 110 69 87 100 72 66 90 75 90 90 80 90 87 70 60 78 81 87 93 84 69 90 75 81 93 72 66 78 50 90 90 40 30 25 10 87 84 93 93 50 100 150 81 78 75 200 250 72 300 69 350 400 63 450 500 fIN - Input Frequency - MHz 60 70 65 75 80 85 90 SFDR - dBc 95 M0049-16 Figure 32. SFDR Contour (with 3.5 dB coarse gain, FS = 1.34 VPP) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 29 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Contour Plots Across Input and Sampling Frequencies (continued) 125 120 66 74 70 90 71 72 73 100 74 68 69 67 80 71 70 70 73 72 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 fS - Sampling Frequency - MSPS 110 67 68 69 60 50 40 71 75 68 69 70 30 25 10 50 72 73 74 150 100 70 71 200 250 69 300 67 66 68 400 350 450 65 64 500 fIN - Input Frequency - MHz 64 70 68 66 72 74 SNR - dBFS M0048-15 Figure 33. SNR Contour (no gain, FS = 2 VPP) 125 120 68 69 70 72 67 66 fS - Sampling Frequency - MSPS 110 100 71 73 67 90 72 80 70 68 69 70 73 60 71 68 50 69 70 72 40 73 30 25 10 50 71 100 150 70 200 250 67 68 69 300 66 350 400 450 65 64 500 fIN - Input Frequency - MHz 64 66 68 70 72 SNR - dBFS 74 M0048-16 Figure 34. SNR Contour (with 3.5 dB coarse gain, FS = 1.34 VPP) 30 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS6142 is a low power, 14-bit pipeline ADC in a CMOS process with a 65 MSPS sampling frequency. This device is based on switched capacitor technology and run off a single 3.3-V supply. The conversion process is initiated by the rising edge of the external input clock. Once the signal is captured by the input sample and hold, the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 9 clock cycles. The output is available as 14-bit data, in DDR LVDS or CMOS and coded in either straight offset binary or binary 2s complement format. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 ANALOG INPUT The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in Figure 35. This differential topology results in good ac-performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V available on the VCM pin. For a full-scale differential input, each input pin (INP, INM) has to swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2VPP differential input swing. The maximum swing is determined by the internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal). Sampling Switch Lpkg »1 nH Sampling Capacitor RCR Filter INP Cbond »1 pF 25 W 50 W Resr 200 W 3.2 pF Lpkg »1 nH Ron 15 W Cpar2 1 pF Csamp 4.0 pF Ron 10 W Cpar1 0.8 pF 50 W Ron 15 W 25 W Csamp 4.0 pF INM Cbond »1 pF Resr 200 W Sampling Capacitor Cpar2 1 pF Sampling Switch Figure 35. Input Stage The input sampling circuit has a high 3dB bandwidth that extends up to 300 MHz (measured from the input pins to the voltage across the sampling capacitors). Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 31 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com 1 0 Magnitude − dB −1 −2 −3 −4 −5 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 −6 −7 0 100 200 300 400 500 600 fIN − Input Frequency − MHz G080 Figure 36. ADC Analog Input Bandwidth Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even-order harmonic rejection. A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. It is also necessary to present low impedance (< 50 Ω) for the common-mode switching currents. For example, this is achieved by using two resistors from each input terminated to the common-mode voltage (VCM). In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance (Zin) must be considered. Over a wide frequency range, the input impedance can be approximated by a parallel combination of Rin and Cin (Zin = Rin||Cin). R − Resistance − kΩ 100 10 1 0.1 0.01 0 100 200 300 400 500 f − Frequency − MHz 600 G083 Figure 37. ADC Input Resistance, Rin 32 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com 9 8 C − Capacitance − pF 7 6 5 4 3 2 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 1 0 0 100 200 300 400 500 f − Frequency − MHz 600 G084 Figure 38. ADC Input Capacitance, Cin Using RF-Transformer Based Drive Circuits Figure 39 shows a configuration using a single 1:1 turn ratio transformer (for example, Coilcraft WBC1-1) that can be used for low input frequencies (about 100 MHz). The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for the ADC common-mode switching current. TF_ADC 0.1 mF 5W INP 0.1 mF 25 W 25 W 5W INM 1 :1 VCM Figure 39. Single Transformer Drive Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 40 shows an example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the dotted box in Figure 40) may be required between the two transformers to improve the balance between the P and M sides. The center point of this termination must be connected to ground. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 33 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com 5W 0 .1mF INP 50 W 50 W 0 .1mF 50 W 50 W 5W INM 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 1:1 1:1 VCM Figure 40. Two Transformer Drive Circuit REFERENCE The ADS6142 has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the integration of the requisite reference capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the converter is controlled in the external reference mode as explained below. The internal or external reference modes can be selected by programming the serial interface register bit <REF> (Table 7). INTREF VCM INTERNAL REFERENCE 1 kW 4 kW INTREF EXTREF REFM REFP Figure 41. Reference Section Internal Reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5 V nominal) is output on the VCM pin, which can be used to externally bias the analog input pins. 34 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com External Reference When the device is in external reference mode, VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given by Equation 1. Full−scale differential input pp + (Voltage forced on VCM) 1.33 (1) In this mode, the 1.5-V common-mode voltage to bias the input pins has to be generated externally. There is no change in performance compared to internal reference mode. COARSE GAIN AND PROGRAMMABLE FINE GAIN 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The ADS6142 includes gain settings that can be used to improve SFDR performance (compared to 0 dB gain mode). The gain settings are 3.5 dB coarse gain and 0 dB to 6 dB programmable fine gain. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 15. The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The fine gain is programmable in 1 dB steps from 0 dB to 6 dB. With fine gain, SFDR improvement is also achieved, but at the expense of SNR (there is about 1 dB SNR degradation for every 1 dB of fine gain). So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get the best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the SFDR improvement is significant with marginal degradation in SINAD. The gains can be programmed using the register bits <COARSE GAIN> (see Table 7) and <FINE GAIN> (see Table 12). Note that the default gain after reset is 0 dB. Table 15. Full-Scale Range Across Gains GAIN, dB TYPE FULL-SCALE RANGE, VPP 0 Default after reset 2.00 3.5 Coarse setting (fixed) 1.34 1 1.78 2 1.59 3 4 Fine gain (programmable) 1.42 1.26 5 1.12 6 1.00 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 35 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com CLOCK INPUT The clock inputs of the ADS6142 can be driven differentially (SINE, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between configurations. The common-mode voltage of the clock inputs is set to VCM using internal 5-kΩ resistors as shown in Figure 42. This allows the use of transformer-coupled drive circuits for the sine wave clock, or ac-coupling for the LVPECL, LVDS clock sources (see Figure 44 and Figure 45). For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with 0.1-μF capacitors, as shown in Figure 44. A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 45. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 For high input frequency sampling, a clock source with very low jitter is recommended. Band-pass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. Clock Buffer Lpkg » 1 nH CLKP 10 W Cbond » 1 pF Ceq Ceq 5 kW Resr » 100 W VCM 6 pF 5 kW Lpkg » 1 nH CLKM 10 W Cbond » 1 pF Resr » 100 W Ceq » 1 to 3 pF, equivalent input capacitance of clock buffer Figure 42. Internal Clock Buffer 36 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com 1000 Impedance (Magnitude) − Ω 900 800 700 600 500 400 300 200 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 100 0 0 25 50 75 100 125 Clock Frequency − MHz G082 Figure 43. Clock Buffer Input Impedance 0.1 mF CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM ADS6142 Figure 44. Differential Clock Driving Circuit 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM ADS6142 Figure 45. Single-Ended Clock Driving Circuit Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 37 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com POWER-DOWN MODES The ADS6142 has four power-down modes – global power down, standby, output buffer disable, and input clock stopped. These modes can be set using the serial interface or using the parallel interface (pins SDATA and PDN). Table 16. Power-Down Modes POWER-DOWN MODES Normal operation PARALLEL INTERFACE SDATA PDN Low Low SERIAL INTERFACE REGISTER BIT (Table 7) TOTAL POWER, mW 417 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 <PDN OBUF>=0 and <STBY>=0 WAKE-UP TIME (to valid data) - Standby Low High <PDN OBUF>=0 and <STBY>=1 72 Slow (15 μs) Output buffer disable High Low <PDN OBUF>=1 and <STBY>=0 408 Fast (200 ns) Global power down High High <PDN OBUF>=1 and <STBY>=1 30 Slow (15 μs) Global Power Down In this mode, the A/D converter, internal references, and the output buffers are powered down and the total power dissipation reduces to about 30 mW. The output buffers are in a high-impedance state. The wake-up time from the global power down to output data becoming valid in normal mode is a maximum of 50 μs. Note that after coming out of global power down, optimum performance is achieved after the internal reference voltages have stabilized (about 1 ms). Standby Only the A/D converter is powered down and total power dissipation is approximately 72 mW. The wake-up time from standby to output data becoming valid is a maximum of 50 μs. Output Buffer Disable The data output buffers can be disabled, reducing total power to about 408 mW. With the buffers disabled, the outputs are in a high-impedance state. The wake-up time from this mode to data becoming valid in normal mode is a maximum of 500 ns in LVDS mode and 200 ns in CMOS mode. Input Clock Stop The converter enters this mode when the input clock frequency falls below 1 MSPS. Power dissipation is approximately 120 mW, and the wake-up time from this mode to data becoming valid in normal mode is a maximum of 50 μs. Power Supply Sequence During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated inside the device. Externally, they can be driven from separate supplies or from a single supply. 38 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com DIGITAL OUTPUT INTERFACE The ADS6142 outputs 14 data bits together with an output clock. The output interface is either parallel CMOS or DDR LVDS voltage levels and can be selected using the serial register bit <LVDS CMOS> or parallel pin SEN. Parallel CMOS Interface In CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V (typical). Each data bit is output on a separate pin as a CMOS voltage level, every clock cycle. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 For DRVDD ≥ 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed (125 MSPS). It is recommended to minimize the load capacitance seen by the data and clock output pins by using short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them. For DRVDD < 2.2 V, it is recommended to use an external clock (for example, input clock delayed to get desired setup/hold times). Output Clock Position Programmability There is an option to shift (delay) the output clock position so that the setup time increases by 400 ps (typical, with respect to the default timings specified). This may be useful if the receiver needs more setup time, especially at high sampling frequencies. This can be programmed using the serial interface register bit <CLKOUT_POSN> (Table 8). Output Buffer Strength Programmability Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this, the ADS6142 CMOS output buffers are designed with a controlled drive strength for the best SNR. The default drive strength also ensures a wide data stable window for load capacitances up to 5 pF and a DRVDD supply voltage ≥ 2.2 V. To ensure a wide data stable window for load capacitances > 5 pF, there is an option to increase the drive strength using the serial interface (<DRIVE STRENGTH>, see Table 14). Note that for a DRVDD supply voltage < 2.2 V, it is recommended to use the maximum drive strength (for any value of load capacitance). CMOS Mode Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital current due to CMOS output switching = CL × DRVDD x (N x FAVG) where CL = load capacitance, N × FAVG = average number of output bits switching (2) Figure 30 shows the current with various load capacitances across sampling frequencies with a 2-MHz analog input frequency. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 39 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Pins OVR CLKOUT D0 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 D1 CMOS Output Buffers D2 D3 D4 D5 D6 14 bit ADC data D7 D8 D9 D10 D11 D12 D13 ADS614X Figure 46. CMOS Output Buffers 40 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com DDR LVDS Interface The LVDS interface works only with a 3.3-V DRVDD supply. In this mode, the 14 data bits and the output clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output on each LVDS differential pair every clock cycle (DDR - Double Data Rate, see Figure 47 ). So, there are 7 LVDS output pairs for the 14 data bits and 1 LVDS output pair for the output clock. LVDS Buffer Current Programmability 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to 2.5 mA, 4.5 mA, and 1.75 mA (register bits <LVDS CURRENT>, see Table 13). In addition, there is a current double mode, where this current is doubled for the data and output clock buffers (register bits <CURRENT DOUBLE>, see Table 13). Pins CLKOUTP Output Clock CLKOUTM D0_D1_P Data bits D0, D1 LVDS Buffers D0_D1_M D2_D3_P Data bits D2, D3 D2_D3_M D4_D5_P Data bits D4, D5 D4_D5_M 14-Bit ADC Data D6_D7_P Data bits D6, D7 D6_D7_M D8_D9_P Data bits D8, D9 D8_D9_M D10_D11_P Data bits D10, D11 D10_D11_M D12_D13_P Data bits D12, D13 D12_D13_M ADS614x Figure 47. DDR LVDS Outputs Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 41 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the rising edge of CLKOUTP and the odd data bits D1, D3, D5, D7, D9, D11, and D13 are output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 14 data bits (see Figure 48). CLKOUTM CLKOUTP D0 D1 D0 D1 D2_D3_P, D2_D3_M D2 D3 D2 D3 D4_D5_P, D4_D5_M D4 D5 D4 D5 D6_D7_P, D6_D7_M D6 D7 D6 D7 D8_D9_P, D8_D9_M D8 D9 D8 D9 D10_D11_P, D10_D11_M D10 D11 D10 D11 D12_D13_P, D12_D13_M D12 D13 D12 D13 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 D0_D1_P, D0_D1_M Sample N Sample N+1 Figure 48. DDR LVDS Interface LVDS Buffer Internal Termination An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially terminated inside the device. The termination resistances available are – 300 Ω, 185 Ω, and 150 Ω (nominal with ±20% variation). Any combination of these three terminations can be programmed; the effective termination is the parallel combination of the selected resistances. This results in eight effective terminations from open (no termination) to 65 Ω. The internal termination helps to absorb any reflections coming from the receiver end, improving the signal integrity. With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved (compared to no internal termination). The voltage swing can be restored by using the LVDS current double mode. Figure 49 and Figure 50 compare the LVDS eye diagrams without and with internal termination (100 Ω). With internal termination, the eye looks clean even with 10-pF load capacitance (from each output pin to ground). The termination is programmed using register bits <DATA TERM> and <CLKOUT TERM> (see Table 13). 42 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Figure 49. LVDS Eye Diagram - No Internal Termination 5-pF Load Capacitance Blue Trace - Output Clock (CLKOUT) Pink Trace - Output Data Figure 50. LVDS Eye Diagram with 100-Ω Internal Termination 10-pF Load Capacitance Blue Trace - Output Clock (CLKOUT) Pink Trace - Output Data Output Data Format Two output data formats are supported – 2s complement and offset binary. They can be selected using the parallel control pin SEN or the serial interface register bit <DATA FORMAT> (see Table 10). Output Timings The tables below show the timings at lower sampling frequencies. Table 17. Timing Characteristics at Lower Sampling Frequencies Fs, MSPS tsu DATA SETUP TIME, ns MIN TYP th DATA HOLD TIME, ns MAX MIN TYP (1) (2) tPDI CLOCK PROPAGATION DELAY, ns MAX MIN TYP MAX CMOS INTERFACE, DRVDD = 2.5 V to 3.3 V 40 20 10 12.8 11.2 25 23 50 48 6.5 DDR LVDS INTERFACE, DRVDD = 3.3 V 40 20 10 (1) (2) 10.8 1.7 5.8 23 1.7 6.5 48 1.7 6.5 Timing parameters are specified by design and not tested in production. Timings are specified with default output buffer drive strength and CL= 5 pF. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 43 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the EVM User Guide (SLWU028) for details on layout and grounding. Supply Decoupling 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 As the ADS6142 already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power supply noise, so the optimum number of capacitors would depend on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being routed to DRVDD. Exposed Thermal Pad It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271). 44 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Offset Error The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 45 ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com Signal-to-Noise Ratio SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. P SNR + 10Log 10 s PN (3) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. Ps SINAD + 10Log 10 PN ) PD (4) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Effective Number of Bits (ENOB) The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization noise. ENOB + SINAD * 1.76 6.02 (5) Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). P THD + 10Log 10 s PN (6) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. DC Power Supply Rejection Ratio (DC PSRR) The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. 46 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT ADS6142-HT SLWS234 – DECEMBER 2011 www.ti.com AC Power Supply Rejection Ratio (AC PSRR) AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ΔVSUP is the change in the supply voltage and ΔVOUT is the resultant change in the ADC output code (referred to the input), then DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (7) Common-Mode Rejection Ratio (CMRR) 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ΔVcm is the change in the input common-mode voltage and ΔVOUT is the resultant change in the ADC output code (referred to the input), then DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (8) Voltage Overload Recovery The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A 6-dBFS sine wave at Nyquist frequency is used as the test stimulus. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS6142-HT 47 PACKAGE OPTION ADDENDUM www.ti.com 24-Dec-2011 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 PACKAGING INFORMATION Orderable Device ADS6142SKGD1 Status (1) Package Type Package Drawing ACTIVE (1) XCEPT KGD Pins Package Qty 0 80 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) N / A for Pkg Type The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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