® ® ADS-931 16-Bit, 1MHz Sampling A/D Converters INNOVATION and EXCELLENCE FEATURES • • • • • • • • • 16-bit resolution 1MHz sampling rate Functionally complete No missing codes over full military temperature range Edge-triggered ±5V supplies, 1.85 Watts Small, 40-pin, ceramic TDIP 87dB SNR, –89dB THD Ideal for both time and frequency-domain applications INPUT/OUTPUT CONNECTIONS GENERAL DESCRIPTION PIN FUNCTION PIN FUNCTION The low-cost ADS-931 is a 16-bit, 1MHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-931 has been optimized to achieve a signal-to-noise ratio (SNR) of 87dB and a total harmonic distortion (THD) of –89dB. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +3.2V REF. OUT UNIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST DIGITAL GROUND FIFO/DIR FIFO READ FSTAT1 FSTAT2 START CONVERT BIT 16 (LSB) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NO CONNECTION NO CONNECTION +5V ANALOG SUPPLY –5V SUPPLY ANALOG GROUND COMP. BITS OUTPUT ENABLE OVERFLOW EOC +5V DIGITAL SUPPLY DIGITAL GROUND BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 Packaged in a 40-pin TDIP, the functionally complete ADS-931 contains a fast-settling sample-hold amplifier, a subranging (twopass) A/D converter, an internal reference, timing/control logic, and error-correction circuitry. Digital input and output levels are TTL. The ADS-931 only requires the rising edge of the start convert pulse to operate. Requiring only ±5V supplies, the ADS-931 dissipates 1.85 Watts. The device is offered with a bipolar (±2.75V) analog input range or a unipolar (0 to –5.5V) input range. Models are available for use in either commercial (0 to +70°C) or military (–55 to +125°C) operating temperature ranges. A proprietary, auto-calibrating, error-correcting circuit enables the device to achieve specified performance over the full military temperature range. Typical applications include medical imaging, radar, sonar, communications and instrumentation. 10 FSTAT1 11 FSTAT2 GAIN ADJUST 6 GAIN ADJUST CKT. 8 FIFO/DIR 9 FIFO/READ 29 BIT 1 (MSB) ANALOG GROUND 4, 36 DIGITAL GROUND 7, 30 +5V DIGITAL SUPPLY 31 –5V SUPPLY 37 +5V ANALOG SUPPLY 38 NO CONNECTION OFFSET ADJUST 5 OFFSET ADJUST CKT. UNIPOLAR 2 39, 40 ANALOG INPUT 3 S/H 27 BIT 2 26 BIT 3 25 BIT 4 3-STATE OUTPUT REGISTER POWER and GROUNDING CUSTOM GATE ARRAY PRECISION +3.2V REFERENCE 2-PASS ANALOG-TO-DIGITAL CONVERTER 28 BIT 1 (MSB) +3.2V REF. OUT 1 24 BIT 5 23 BIT 6 22 BIT 7 21 BIT 8 20 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 13 BIT 16 (LSB) OFFSET ADJUST 5 START CONVERT 12 EOC 32 TIMING AND CONTROL LOGIC 34 OUTPUT ENABLE 33 OVERFLOW COMP. BITS 35 Figure 1. ADS-931 Functional Block Diagram DATEL, Inc., Mansfield, MA 02048 (USA) • Tel: (508)339-3000, (800)233-2756 Fax: (508)339-6356 • E-mail:[email protected] • Internet: www.datel.com ® ® ADS-931 ABSOLUTE MAXIMUM RATINGS PARAMETERS +5V Supply (Pins 31, 38) –5V Supply (Pin 37) Digital Inputs (Pins 8, 9, 12, 34, 35) Analog Input (Pin 3) Bipolar Unipolar Lead Temperature (10 seconds) PHYSICAL/ENVIRONMENTAL LIMITS UNITS 0 to +6 0 to –6 –0.3 to +VDD +0.3 Volts Volts Volts Volts Volts Volts °C ±5 –10 to +5 +300 PARAMETERS MIN. TYP. MAX. UNITS 0 –55 — — +70 +125 °C °C — — – 65 4 18 — — — +150 °C/Watt °C/Watt °C Operating Temp. Range, Case ADS-931MC ADS-931MM Thermal Impedance θjc θca Storage Temperature Range Package Type Weight 40-pin, metal-sealed, ceramic TDIP 0.56 ounces (16 grams) FUNCTIONAL SPECIFICATIONS (TA = +25°C, ±VCC = ±5V, +VDD = +5V, 1MHz sampling rate, and a minimum 3 minute warm-up ➀ unless otherwise specified.) +25°C ANALOG INPUTS Input Voltage Ranges Unipolar Bipolar Input Resistance (pin 3) Input Resistance (pin 2) Input Capacitance 0 to +70°C MIN. TYP. MAX. — — — — — 0 to –5.5 ±2.75 685 400 10 — — — — 15 +2.0 — — — 40 — — — — 100 — — –0.95 — — — — 16 MIN. –55 to +125°C TYP. MAX. — — — — — 0 to –5.5 ±2.75 685 426 10 — — — — 15 — +0.8 +20 –20 — +2.0 — — — 40 — — — — 100 16 ±1 ±0.5 ±0.1 ±0.1 ±0.1 ±0.1 — — — +1.0 ±0.3 ±0.2 ±0.3 ±0.3 — — — –0.95 — — — — 16 — — –91 –91 –85 –85 — — –89 –87 84 83 MIN. TYP. MAX. UNITS — — — — — 0 to –5.5 ±2.75 685 426 10 — — — — 15 Volts Volts Ω Ω pF — +0.8 +20 –20 — +2.0 — — — 40 — — — — 100 — +0.8 +20 –20 — Volts Volts µA µA ns 16 ±1.5 ±0.5 ±0.15 ±0.2 ±0.2 ±0.15 — — — +1.0 ±0.5 ±0.4 ±0.5 ±0.5 — — — –0.95 — — — — 16 16 ±2 ±0.5 ±0.5 ±0.5 ±0.4 ±0.5 — — — +1.5 ±0.8 ±0.9 ±0.9 ±0.9 — Bits LSB LSB %FSR %FSR %FSR % Bits — — –91 –91 –85 –85 — — –90 –90 –83 –83 dB dB –83 –80 — — –89 –87 –83 –80 — — –87 –85 –81 –79 dB dB 87 86 — — 84 83 87 86 — — 82 80 86 84 — — dB dB 80 79 — 85 84 82 — — — 80 79 — 85 84 82 — — — 77 76 — 83 82 82 — — — dB dB µVrms — –89 — — –89 — — –89 — dB — — 4.8 4.1 — — — — 4.8 4.1 — — — — 4.8 4.1 — — MHz MHz — — — — 90 ±51 +8 5 — — — — — — — — 90 ±51 +8 5 — — — — — — — — 90 ±51 +8 5 — — — — dB V/µs ns ps rms 700 725 — 700 725 — 700 725 — ns DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" ➁ Start Convert Positive Pulse Width ➂ STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 250kHz 250kHz to 500kHz Total Harmonic Distortion (–0.5dB) dc to 250kHz 250kHz to 500kHz Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 250kHz 250kHz to 500kHz Signal-to-Noise Ratio ➃ (& distortion, –0.5dB) dc to 250kHz 250kHz to 500MHz Noise Two-Tone Intermodulation Distortion (fin = 98kHz, 240kHz, fs = 1MHz, –0.5dB) Input Bandwidth (–3dB) Small Signal (–20dB input) Large Signal (–0.5dB input) Feedthrough Rejection (fin = 480kHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to ±0.001%FSR, 5.5V step) 2 ® ® ADS-931 DYNAMIC PERFORMANCE (Cont.) Overvoltage Recovery Time ➄ A/D Conversion Rate MIN. +25°C TYP. MAX. MIN. 0 TO +70°C TYP. — 1 — — 1000 — — 1 — — 3.15 — — +3.2 ±30 5 3.25 — — 3.15 — — +3.2 ±30 5 +2.4 — — — — — — — — +0.4 –4 +4 +2.4 — — — — — — — — — +4.75 –4.75 +5.0 –5.0 +5.25 –5.25 +4.75 –4.75 +5.0 –5.0 +5.25 –5.25 +4.9 –4.9 — –140 — — +225 –135 1.85 — 260 — 2.0 ±0.07 — –140 — — +225 –135 1.85 — 260 — 2.0 ±0.07 — –140 — — –55 TO +125°C TYP. MAX. MAX. MIN. UNITS 1000 — — 1 — — 3.25 — — 3.15 — — +3.2 ±30 5 3.25 — — Volts ppm/°C mA — +0.4 –4 +4 +2.4 — — — — — — — — +0.4 –4 +4 Volts Volts mA mA 20 ns +5.0 –5.0 +5.25 –5.25 Volts Volts +225 –135 1.85 — 260 — 2.0 ±0.07 mA mA Watts %FSR/%V 1000 — ns MHz ANALOG OUTPUT Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Delay, Falling Edge of Enable to Output Data Valid Output Coding 20 — — 20 — — Straight Binary, Complementary Binary, Complementary Offset Binary, Complementary Two's Complement, Offset Binary, Two's Complement POWER REQUIREMENTS Power +5V –5V Power +5V –5V Power Power Supply Ranges ➅ Supply Supply Supply Currents Supply Supply Dissipation Supply Rejection Footnotes: ➃ Effective bits is equal to: ➀ All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warm-up periods. The device must be continuously converting during this time. There is a slight degradation in performance when operating the device in the unipolar mode. (SNR + Distortion) – 1.76 + Full Scale Amplitude 20 log Actual Input Amplitude 6.02 ➁ When COMP. BITS (pin 35) is low, logic loading "0" will be –350µA. ➄ This is the time required before the A/D output data is valid once the analog input is back within the specified range. This time is only guaranteed if the input does not exceed ±4.75V (bipolar) or +2 to –7.5V (unipolar). ➂ A 1MHz clock with a positive pulse width is used for all production testing. See Timing Diagram for more details. 40ns < Start Pulse < 175ns or 280ns < Start Pulse < 460ns ➅ The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for –55°C operation only. The minimum limits are +4.75V and –4.75V when operating at +125°C. TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-931 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (4, 7, 30 and 36) directly to a large analog ground plane beneath the package. 3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the ADS-931 (see Tables 2a and 2b). When this pin has a TTL logic "0" applied, it complements the ADS931’s B1-B16 & B1 outputs. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. Bypass all power supplies and the +3.2V reference output to ground with 4.7µF tantalum capacitors in parallel with 0.1µF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). 2. The ADS-931 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warm-up. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. Data from both the interrupted and subsequent conversions will be invalid. 3 ® ® ADS-931 When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of the FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the rising edge of EOC to the falling edge of EOC). 7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1’s or when the input equals or exceeds the voltage that produces all 0’s. When COMP BITS is activated, the above conditions are reversed. If the output three-state register has been enabled (logic "0" applied to pin 34), data from the first conversion will appear at the output of the ADS-931. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. 8. When configuring the ADS-931 for the unipolar mode, Pin 1 (+3.2V REF.) should be connected to Pin 2 (Unipolar) through a non-inverting op-amp. For precision DC applications an OP07 type amplifier is recommended, while AC applications requiring the lowest level of harmonic distortion should consider the AD9631. When configuring the ADS-931 for the bipolar mode, Pin 2 (Unipolar) should be physically disconnected from the surrounding circuitry. This will help prevent noise from coupling into the A/D. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. After the 15th rising edge brings the 16th data word to the FIFO output, the subsequent falling edge on READ will update the status outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating that the FIFO is empty. INTERNAL FIFO OPERATION The ADS-931 contains an internal, user-initiated, 18-bit, 16-word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and overflow bits. Pins 8 (FIFO/DIR) and 9 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2). If a read command is issued after the FIFO empties, the last word (the 16th conversion) will remain present at the outputs. When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 8 has a logic "0" applied, the FIFO is transparent and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-931 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-931’s digital data path. At any time, the FIFO can be reset to an empty state by putting the ADS-931 into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs change 40ns after applying the control signals. FIFO Write and Read Modes Monitor the status of the data in the FIFO by reading the two status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11). FIFO Reset Feature FIFO Status, FSTAT1 and FSTAT2 Once the FIFO has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO. CONTENTS Empty (0 words) <half full (<8 words) half-full or more (≥8 words) Full (16 words) FSTAT1 0 0 1 1 FSTAT2 1 0 0 1 Table 1. FIFO Delays DELAY PIN TRANSITION Direct mode to FIFO enabled 8 FIFO enabled to direct mode 8 FIFO READ to output data valid 9 0 FIFO READ to status update when changing from <half full (1 word) to empty 9 1 FIFO READ to status update when changing from ≥half full (8 words) to <half full (7 words) 9 0 FIFO READ to status update when changing from full (16 words) to ≥half full (15 words) 9 0 Falling edge of EOC to status update when writing first word into empty FIFO 32 1 Falling edge of EOC to status update when changing FIFO from <half full (7 words) to ≥half full (8 words) 32 1 Falling edge of EOC to status update when filling FIFO with 16th word 32 1 0 1 4 MIN. TYP. MAX. UNITS – 10 20 ns 0 1 – 10 20 ns – – 40 ns 0 – – 20 ns 1 – – 110 ns – – 190 ns 0 – – 190 ns 0 – – 110 ns 0 – – 28 ns 1 1 ® ® ADS-931 CALIBRATION PROCEDURE for operation without gain adjustment. Connect the converter per Figure 2. Any offset/gain calibration procedures should not be implemented until the device is fully warmed up. To avoid interaction, adjust offset before gain. The ranges of adjustment for the circuits in Figure 2 are guaranteed to compensate for the ADS-931’s initial accuracy errors and may not be able to compensate for additional system errors. Zero/Offset Adjust Procedure 1. Apply a train of pulses to the START CONVERT input (pin 12) so that the converter is continuously converting. 2. For unipolar or bipolar zero/offset adjust, apply –42µV to the ANALOG INPUT (pin 3). A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This is accomplished by connecting LED's to the digital outputs and performing adjustments until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. 3. For bipolar inputs, adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (complementary offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binary). For unipolar inputs, adjust the offset potentiometers until all output bits are 0's and the LSB flickers between 0 and 1 with Pin 35 tied high (straight binary) or until all bits are 1's and the LSB flickers between 0 and 1 with pin 35 tied low (complementary binary). For the ADS-931, offset adjusting is normally accomplished when the analog input is 0 minus ½ LSB (–42µV). See Table 2b for the proper bipolar output coding. Gain adjusting is accomplished when the analog input is at nominal full scale minus 1½ LSB's (+2.749874V). 4. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the trimpot until the output code flickers between all 0’s and all 1’s. Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without zero/offset adjustment. Connect pin 6 to pin 4 Table 2a. Setting Output Coding Selection (Pin 35) OUTPUT FORMAT Gain Adjust Procedure PIN 35 LOGIC LEVEL Complementary Offset Binary 1 Offset Binary 0 Complementary Two’s Complement (Using MSB, pin 29) 1 Two’s Complement (Using MSB, pin 29) 0 Straight Binary Complimentary Binary 1 0 1. Apply +2.749874V to the ANALOG INPUT (pin 3). 2. For bipolar inputs, adjust the gain potentiometer until all output bits are 0’s and the LSB flickers between a 1 and 0 with pin 35 tied high (complementary offset binary) or until all output bits are 1’s and the LSB flickers between a 1 and 0 with pin 35 tied low (offset binary). 3. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the gain trimpot until the output code flickers equally between 0111 1111 1111 1111 and 0111 1111 1111 1110. 20kΩ +5V 20kΩ –5V +5V 6 GAIN ADJUST +5V 31 4.7µF 0.1µF + 4.7µF –5V 4.7µF 0.1µF 5 OFFSET ADJUST 33 OVERFLOW 32 EOC 29 BIT 1 (MSB) 28 BIT 1 (MSB) +5V DIGITAL DIGITAL 7, 30 GROUND 38 + +5V 0.1µF –5V +5V ANALOG ANALOG 4, 36 GROUND 37 –5V 34 ENABLE 8 FIFO/DIR 10 FSTAT1 2 UNIPOLAR 11 FSTAT2 1 +3.2V REF. OUT 27 26 25 24 BIT2 BIT 3 BIT 4 BIT 5 23 22 21 20 BIT 6 BIT 7 BIT 8 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 13 BIT 16 (LSB) ADS-931 CONNECT for UNIPOLAR MODE ANALOG INPUT 3 FIFO READ 9 6.8µF START CONVERT 12 COMP. BITS 35 0.1µF 4.7µF Figure 2. Bipolar Connection Diagram 5 +5V ® ® ADS-931 THERMAL REQUIREMENTS underneath the package. Devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70°C and –55 to +125°C. All room-temperature (TA = +25°C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of DATEL's HS Series heat sinks. See Ordering Information for the assigned part number. See page 1-183 of the DATEL Data Acquisition Components Catalog for more information on the HS Series. Request DATEL Application Note AN-8, "Heat Sinks for DIP Data Converters," or contact DATEL directly, for additional information. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically insulating, thermally-conductive "pads" may be installed N N+1 N+3 N+2 START CONVERT 100ns typ. Acquisition Time 730ns typ. 20ns typ. Hold INTERNAL S/H 270ns typ. 60ns typ. 55ns typ. EOC 280ns typ. Conversion Time 20ns typ. OUTPUT DATA 940ns typ. Data N-4 Valid Data N-2 Valid Data N-3 Valid 60ns typ. Invalid Data Data N-1 Valid Invalid Data Notes: 1. Scale is approximately 50ns per division. fs = 1MHz. 2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data from the first conversion to appear at the output of the A/D. 3. The start convert positive pulse width must be between either 40 and 175nsec or 280 and 460nsec (when sampling at 1MHz) to ensure proper operation. For sampling rates lower than 1MHz, the start pulse can be wider than 460nsec, however a minimum pulse width low of 40nsec should be maintained. A 1MHz clock with a 100nsec positive pulse width is used for all production testing. Figure 3. ADS-931 Timing Diagram 0 –10 Amplitude Relative to Full Scale (dB) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 0 50 100 150 200 250 300 350 400 Frequency (kHz) (fs = 1MHz, fin = 480kHz, Vin = –0.5dB, 16,384-point FFT) Figure 4. FFT Analysis of ADS-931 6 450 500 A G N D + 1 5 V 1 2 O P T IO N 3 A N A L O G 7 A M P L IF IE R + A R 1 4 2 1 A G N D 1 5 V C 2 2 .2 µ F 3 1 0 1 2 1 4 U 1 9 7 4 H C T 7 4 1 1 2 4 .1 u F X 1 7 2 8 1 M H Z 1 1 1 4 S G 9 2 3 2 C 6 2 .2 µ F 1 F IF 3 .3 K D G N D C 1 0 3 3 p F 1 8 R D 1 0 1 1 1 2 S T A R T C O N V E R T 7 J 1 1 2 3 R 6 2 2 1 L 1 1 2 5 0 1 2 6 2 3 2 1 1 9 1 7 1 5 1 3 1 1 9 7 5 3 1 2 2 2 0 1 8 1 6 1 4 1 2 1 0 8 6 4 2 D G N D C 7 2 5 2 4 1 1 5 V + 5 V A S G 2 2 2 2 1 S G 4 2 1 A B 1 5 1 4 A B 1 4 1 5 A B 1 3 1 6 A B 1 2 1 7 A B 1 1 1 8 A B 1 0 1 9 A B 9 2 0 L 3 D G N D 2 2 1 4 0 N C 3 9 3 A G N D 3 6 A G N D C O M P 3 5 C O M P E N A B L E 3 4 E N A B L E O F 3 3 O F E O C 3 2 E O C + 5 V D 3 1 D G N D 3 0 F S T A T 2 M S B 2 8 A B 1 B 1 5 B 2 2 7 A B 2 B 1 1 B 1 0 B 3 2 6 A B 3 B 4 2 5 A B 4 B 5 2 4 A B 5 B 6 2 3 A B 6 B 7 2 2 A B 7 B 8 B 9 2 3 U 5 1 0 9 1 2 E O C 1 7 4 H C 8 6 8 U 5 G A IN A D J 2 .2 µ F 1 2 + 5 V A R 4 2 2 0 K 3 1 -5 V A 1 2 + 5 V A R 5 7 4 H C 8 6 2 0 K 3 -5 V A D G N D B 1 (M S B ) 8 B 6 7 1 4 A B 4 6 A B 5 5 A B 6 4 A B 7 3 A B 8 2 U 3 1 8 1 6 1 7 1 9 1 1 B 2 B 7 B 3 B 8 B 4 3 4 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 B 9 B 7 B 1 0 B 8 B 1 1 1 8 1 7 1 6 1 5 1 2 B 1 6 (L S B ) A B 1 5 8 1 3 B 1 5 A B 1 4 7 1 4 B 1 4 A B 1 3 6 1 5 B 1 3 A B 1 2 5 1 6 B 1 2 A B 1 1 4 3 2 U 4 A B 1 0 A B 9 F S T 2 1 A G N D B 1 0 1 9 B 9 E O C D G N D D G N D D G N D D G N D E N A B L E 1 0 9 8 7 6 5 4 C O M P L IM N C R E A D F IF /D IR F S T 1 3 2 D G N D D G N D 1 1 S T A R T C O N V F S T 2 1 1 2 3 J 2 E N A B L E 1 2 3 J 3 C O M P L IM 1 2 3 J 4 R E A D 1 2 3 J 5 F IF O /D IR C O M P + 5 V D D G N D 1 3 B 1 6 (L S B ) B 1 1 1 8 (M S B ) D G N D 1 2 B 1 5 D G N D 9 1 7 2 C 2 1 2 .2 µ F O V R F L W 1 4 B 1 2 B 1 4 1 0 1 P 1 B 6 D G N D A B 1 6 B 1 B 3 3 B 5 1 2 0 1 A G N D D G N D B 1 3 C 1 7 .1 µ F C 1 2 2 .2 µ F R D F IF D G N D 1 4 1 1 U 5 7 D G N D F S T 1 C 8 .1 µ F 1 2 D G N D Figure 5. ADS-931 Evaluation Board Schematic. ADS-931 O F F S E T A D J 1 3 (M S B ) B 1 B B 4 1 5 2 C 1 4 2 .2 µ F 2 + 5 V A -5 V A O V R F L W 1 3 + 5 V F + 5 V F 1 A G N D B 2 1 0 1 C 2 0 .1 µ F B 5 1 1 + 5 V A 2 0 µ H 1 A G N D D G N D + 5 V D 2 D G N D 1 2 B 1 (M S B ) + 5 V F 7 4 H C 8 6 2 L 4 C 1 3 A G N D 1 6 S T A R T C O N V U 5 5 C 1 9 .1 µ F 1 2 0 A B 3 D G N D A B 8 2 1 C 1 8 .1 µ F 2 9 A B 1 A B 2 2 .2 µ F 2 2 4 C 1 6 .1 µ F D G N D L S B B 1 2 1 + 5 V D 2 9 1 + 5 V A -5 V A B 3 -5 V A M S B B 1 3 1 8 2 1 7 1 1 + 5 V A S T A R T C O N B 1 4 U 2 + 5 V D 1 6 1 9 + 5 V F 3 7 U 6 1 5 2 5 V A 7 4 H C 8 6 5 V A 2 0 µ H C 1 1 1 D G N D + 5 V D 2 0 µ H A G N D 1 S G 3 1 1 3 F S T A T 1 N C 2 .2 µ F 2 1 1 2 C 9 P 2 S G 1 L 2 D G N D 5 V A + 1 5 V + 5 V F 2 .2 µ F 2 + 5 V D 1 2 0 µ H A B 1 6 R E A D 5 4 3 8 F IF O /D IR 9 D G N D D G N D D G N D 6 N .C . + 5 V A G A IN 7 1 1 5 V + 3 .2 V R E F O F F S E T 6 1 4 3 A G N D A G N D R 3 2 4 A N A IN 6 2 A R 2 2 1 5 5 7 4 H C T 7 4 3 + 5 V F 1 2 U 1 2 D G N D D G N D 1 4 C 5 1 8 1 3 7 S G 5 1 3 7 D G N D 6 U U T 1 8 ® A G N D 2 + 7 D G N D 1 0 1 2 + 1 5 V O P 0 7 + 5 V F + 5 V F 2 0 9 2 2 .2 µ F A G N D 2 1 A G N D A G N D 2 .2 µ F 1 C 1 5 .1 µ F C 2 2 C 4 2 1 S G 8 2 B 1 1 C 3 .1 µ F 5 V A IN P U T B 2 2 C 1 2 .2 µ F 2 6 + 5 V F + 5 V A S G 7 7 4 H C T 5 7 3 1 7 4 H C T 5 7 3 R 2 2 7 4 H C T 5 7 3 1 ® R 1 2 ® ® ADS-931 Table 2a. Setting Output Coding Selection (Pin 35) OUTPUT FORMAT PIN 35 LOGIC LEVEL Complementary Offset Binary 1 Offset Binary 0 Complementary Two’s Complement (Using MSB, pin 29) 1 Two’s Complement (Using MSB, pin 29) 0 Straight Binary Complimentary Binary 1 0 Table 2b. Output Coding STRAIGHT BINARY UNIPOLAR SCALE –FS+1 LSB –FS +1 1/2 LSB –7/8 FS –3/4 FS –1/2 FS –1/2FS–1/2LSB –1/4 FS –1/8 FS –1 LSB –1/2 LSB 0 INPUT RANGE 0 to –5.5V MSB –5.499916 –5.499874 –4.812500 –4.125000 –2.750000 –2.749958 –1.375000 –0.687500 –0.000084 –0.000042 0.000000 1111 1111 LSB "1" to 1110 0000 1100 0000 1000 0000 0111 1111 0100 0000 0010 0000 0000 0000 LSB "0" to 0000 0000 COMP. BINARY OUTPUT CODING LSB 1111 "0" 0000 0000 0000 1111 0000 0000 0000 "1" 0000 1111 0000 0000 0000 1111 0000 0000 0001 0000 MSB LSB 0000 0000 0000 LSB "0" to "1" 0001 1111 1111 0011 1111 1111 0111 1111 1111 1000 000 000 1011 1111 1111 1101 1111 1111 1111 1111 1111 LSB "1" to "0" 1111 1111 1111 OFFSET BINARY MSB 0000 0111 1111 1111 1111 0000 1111 1111 1110 0110 0100 0000 1111 1100 1010 1000 1111 1000 COMP. OFF. BIN. LSB 1111 1111 LSB "1" to "0" 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 LSB "0" to "1" 0000 0000 MSB 1111 1000 0000 0000 0000 1111 0000 0000 0001 1001 1011 1111 0000 0011 0101 0111 0000 0111 TWO'S COMP. Table 3. Input Connections Input Range 0 to –5.5V ±2.75V Input Pin Pin 3 Pin 3 8 Connect Pin 1 To Pin 2 Pin 2 is No Connect LSB 0000 0000 LSB "0" to "1" 1111 1111 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 1111 1111 LSB "1" to "0" 1111 1111 0000 1111 1111 1111 0000 1111 1111 1110 1111 COMP. TWO'S COMP. INPUT RANGE ±2.75V +2.749916 +2.749874 +2.062500 +1.375000 0.000000 –0.000084 –1.375000 –2.062500 –2.749916 –2.749958 –2.750000 BIPOLAR SCALE +FS –1 LSB +FS –1 1/2 LSB +3/4 FS +1/2 FS 0 –1 LSB –1/2 FS –3/4 FS –FS +1 LSB –FS + 1/2 LSB –FS ® ® ADS-931 0.71 DNL (LSB's) Number of Occurrences 2147 0.00 –0.56 0 65,536 Codes 0 Digital Output Code Figure 5. ADS-931 Histogram and Differential Nonlinearity 4530 4000 3000 2000 1000 0 Digital Output Code Figure 6. ADS-931 Grounded Input Histogram This histogram represents the typical peak-to-peak noise (including quantization noise) associated with the ADS-931. 9 65,536 ® ® ADS-931 MECHANICAL DIMENSIONS INCHES (mm) 2.12/2.07 (53.85/52.58) 40 Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) 21 Lead Material: Kovar alloy 1.11/1.08 (28.20/27.43) 1 Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 20 0.100 TYP. (2.540) 1.900 ±0.008 (48.260) 0.245 MAX. (6.223) PIN 1 INDEX ( ON TOP) 0.200/0.175 (5.080/4.445) 0.015/0.009 (0.381/0.229) 0.210 MAX. (5.334) 0.018 ±0.002 (0.457) 0.900 ±0.010 (22.86) 0.110/0.090 (2.794/2.286) 0.110/0.090 (2.794/2.286 SEATING PLANE 0.035/0.015 (0.889/0.381) 0.045/0.035 (1.143/0.889) ORDERING INFORMATION MODEL OPERATING TEMP. RANGE ACCESSORIES ADS-931MC ADS-931MM 0 to +70°C –55 to +125°C ADS-B931 HS-40 Evaluation Board (without ADS-931) Heat Sink for all ADS-931 models Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL. ® ® INNOVATION and EXCELLENCE ISO 9001 R DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com E-mail:[email protected] Data Sheet Fax Back: (508) 261-2857 E G I S T E R E D DS-0307 9/97 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01 DATEL GmbH München, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.