® ® ADS-933 16-Bit, 3MHz Sampling A/D Converters INNOVATION and EXCELLENCE PRELIMINARY PRODUCT DATA FEATURES • • • • • • • • • 16-bit resolution 3MHz sampling rate Functionally complete No missing codes over full military temperature range Edge-triggered ±5V supplies, 1.85 Watts Small, 40-pin, ceramic TDIP 85dB SNR, –84dB THD Ideal for both time and frequency-domain applications INPUT/OUTPUT CONNECTIONS PIN GENERAL DESCRIPTION The low-cost ADS-933 is a 16-bit, 3MHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-933 has been optimized to achieve a signal-to-noise ratio (SNR) of 85dB and a total harmonic distortion (THD) of –84dB. Packaged in a 40-pin TDIP, the functionally complete ADS-933 contains a fast-settling sample-hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing/control logic, and error-correction circuitry. Digital input and output levels are TTL. The ADS-933 only requires the rising edge of the start convert pulse to operate. Requiring only ±5V supplies, the ADS-933 dissipates 1.85 Watts. The device is offered with a bipolar (±2.75V) analog input range and a unipolar 0 to –5.5V input range. Models are available for use in either commercial (0 to +70°C) or military (– 55 to +125°C) operating temperature ranges. A proprietary, autocalibrating, error-correcting circuit enables the device to achieve specified performance over the full military temperature range. Typical applications include medical imaging, radar, sonar, communications and instrumentation. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FUNCTION PIN FUNCTION +3.2V REF. OUT UNIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST DIGITAL GROUND FIFO/DIR FIFO READ FSTAT1 FSTAT2 START CONVERT BIT 16 (LSB) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NO CONNECTION NO CONNECTION +5V ANALOG SUPPLY –5V SUPPLY ANALOG GROUND COMP. BITS OUTPUT ENABLE OVERFLOW EOC +5V DIGITAL SUPPLY DIGITAL GROUND BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 10 FSTAT1 11 FSTAT2 GAIN ADJUST 6 GAIN ADJUST CKT. 8 FIFO/DIR 9 FIFO/READ 29 BIT 1 (MSB) +5V ANALOG SUPPLY 38 +5V DIGITAL SUPPLY 31 –5V SUPPLY 37 ANALOG GROUND 4, 36 DIGITAL GROUND 7, 30 NO CONNECTION 39, 40 OFFSET ADJUST 5 OFFSET ADJUST CKT. UNIPOLAR 2 ANALOG INPUT 3 S/H 26 BIT 3 25 BIT 4 3-STATE OUTPUT REGISTER POWER AND GROUNDING 27 BIT 2 CUSTOM GATE ARRAY PRECISION +3.2V REFERENCE 2-PASS ANALOG-TO-DIGITAL CONVERTER 28 BIT 1 (MSB) +3.2V REF. OUT 1 24 BIT 5 23 BIT 6 22 BIT 7 21 BIT 8 20 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 OFFSET ADJUST 5 START CONVERT 12 EOC 32 13 BIT 16 (LSB) TIMING AND CONTROL LOGIC 34 OUTPUT ENABLE 33 OVERFLOW COMP. BITS 35 Figure 1. ADS-933 Functional Block Diagram DATEL, Inc., Mansfield, MA 02048 (USA) • Tel: (508)339-3000, (800)233-2765 Fax: (508) 339-6356 • E-mail: [email protected] • Internet: www.datel.com ® ® ADS-933 ABSOLUTE MAXIMUM RATINGS PARAMETERS PHYSICAL/ENVIRONMENTAL LIMITS UNITS +5V Supply (Pins 31, 38) 0 to +6 –5V Supply (Pin 37) 0 to –6 Digital Inputs (Pins 8, 9, 12, 34, 35) –0.3 to +VDD +0.3 Analog Input (Pin 3) ±5 Lead Temperature (10 seconds) +300 PARAMETERS Volts Volts Volts Volts °C MIN. TYP. MAX. UNITS 0 –55 — — +70 +125 °C °C — — –65 4 18 — — — +150 °C/Watt °C/Watt °C Operating Temp. Range, Case ADS-933MC ADS-933MM Thermal Impedance θjc θca Storage Temperature Range Package Type Weight FUNCTIONAL SPECIFICATIONS 40-pin, metal-sealed, ceramic TDIP 0.56 ounces (16 grams) (TA = +25°C, ±VCC = ±5V, +VDD = +5V, 3MHz sampling rate, and a minimum 3 minute warm-up ➀ unless otherwise specified.) +25°C ANALOG INPUT Input Voltage Range Unipolar Bipolar Input Resistance Pin 3 Input ResistancePin 2 Input Capacitance 0 to +70°C MIN. TYP. MAX. — — 655 418 — 0 to –5.5 ±2.75 687 426 10 — — — — 15 +2.0 — — — 20 — — — — 50 — — –0.95 — — MIN. –55 to +125°C TYP. MAX. — — 655 418 — 0 to –5.5 ±2.75 687 426 10 — — — — 15 — +0.8 +20 –20 — +2.0 — — — 20 — — — — 50 16 ±1 ±0.5 ±0.15 ±0.1 — — +1.0 ±0.3 ±0.2 — — –0.95 — — — — 16 ±0.1 ±0.15 — ±0.2 ±0.3 — — — — –84 — — MIN. TYP. MAX. UNITS — — 655 418 — 0 to –5.5 ±2.75 687 426 10 — — — — 15 Volts Volts Ω Ω pF — +0.8 +20 –20 — +2.0 — — — 20 — — — — 50 — +0.8 +20 –20 — Volts Volts µA µA ns 16 ±1.5 ±0.5 ±0.3 ±0.2 — — +1.0 ±0.5 ±0.4 — — –0.95 — — 16 ±2 ±0.5 ±0.5 ±0.4 — — +1.5 ±0.8 ±0.6 Bits LSB LSB %FSR %FSR — — 16 ±0.2 ±0.3 — ±0.4 ±0.5 — — — 16 ±0.4 ±0.5 — ±0.6 ±0.8 — %FSR % Bits 81 80 — — –86 –84 — — — — –86 –84 — — dB dB –84 –83 80 80 — — –84 –83 — — — — –84 –83 — — dB dB 81 81 85 85 — — — — 85 85 — — — — 85 85 — — dB dB 78 78 — 82 81 80 — — — — — — 82 81 80 — — — — — — 82 81 80 — — — dB dB µVrms — –87 — — –87 — — –87 — dB — — 9.8 10.2 — — — — 9.8 10.2 — — — — 9.8 10.2 — — MHz MHz — — — — 90 ±120 +8 3 — — — — — — — — 90 ±120 +8 3 — — — — — — — — 90 ±120 +8 3 — — — — dB V/µs ns psrms — 180 — — 180 — — 180 — ns DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" ➁ Start Convert Positive Pulse Width ➂ STATIC PERFORMANCE Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) (Unipolar offset spec same as Bipolar zero) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 500kHz 500kHz to 1MHz Total Harmonic Distortion (–0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio ➃ (& distortion, –0.5dB) dc to 500kHz 500kHz to 1MHz Noise Two-Tone Intermodulation Distortion (fin = 200kHz, 240kHz, fs = 3MHz, –0.5dB) Input Bandwidth (–3dB) Small Signal (–20dB input) Large Signal (–0.5dB input) Feedthrough Rejection (fin = 1MHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to ±0.001%FSR, 5.5V step) 2 ® ® ADS-933 DYNAMIC PERFORMANCE (Cont.) MIN. +25°C TYP. MAX. MIN. 0 TO +70°C TYP. MAX. –55 TO +125°C MIN. TYP. MAX. — 3 — — 333 — — 3 — — 333 — — 3 — — 333 — ns MHz 3.15 — — +3.2 ±30 5 — — — — — — +3.2 ±30 5 — — — — — — +3.2 ±30 5 — — — Volts ppm/°C mA UNITS ANALOG OUTPUT Overvoltage Recovery Time ➄ A/D Conversion Rate Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Output Coding +2.4 — — — — — +2.4 — — +2.4 — — — +0.4 — — +0.4 — — +0.4 — –4 — — –4 — — –4 — +4 — — +4 — — +4 Offset Binary / Complementary Offset Binary / Two's Complement / Complementary Two's Complement Volts Volts mA mA POWER REQUIREMENTS Power Supply Ranges ⑥ +5V Supply –5V Supply Power Supply Currents +5V Supply –5V Supply Power Dissipation Power Supply Rejection +4.75 –4.75 +5.0 –5.0 +5.25 –5.25 +4.75 –4.75 +5.0 –5.0 +5.25 –5.25 +4.9 –4.9 +5.0 –5.0 +5.25 –5.25 Volts Volts — –140 — — +220 –150 1.85 — 260 — 2.0 ±0.07 — –140 — — +220 –150 1.85 — 260 — 2.0 ±0.07 — –140 — — +220 –150 1.85 — 260 — 2.0 ±0.07 mA mA Watts %FSR/%V Footnotes: ➃ Effective bits is equal to: ➀ All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warm-up periods. The device must be continuously converting during this time. (SNR + Distortion) – 1.76 + Full Scale Amplitude 20 log Actual Input Amplitude 6.02 ➁ When COMP. BITS (pin 35) is low, logic loading "0" will be –350µA. ➄ This is the time required before the A/D output data is valid once the analog input is back within the specified range. ➂ A 3MHz clock with a 50nsec positive pulse width is used for all production testing. See Timing Diagram for more details. ➅ The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for –55°C operation only. The minimum limits are +4.75V and –4.75V when operating at +125°C. TECHNICAL NOTES 3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the ADS-933. See Tables 2a and 2b. When this pin has a TTL logic "0" applied, it complements all of the ADS-933’s digital outputs. 1. Obtaining fully specified performance from the ADS-933 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (2, 4, 7, 30 and 36) directly to a large analog ground plane beneath the package. When pin 35 has a logic "1" applied, the output coding is complementary offset binary. Applying a logic "0" to pin 35 changes the coding to offset binary. Using the MSB output (pin 29) instead of the MSB output (pin 28) changes the respective output codings to complementary two's complement and two's complement. Bypass all power supplies and the +3.2V reference output to ground with 4.7µF tantalum capacitors in parallel with 0.1µF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. 2. The ADS-933 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warm-up. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). 3 ® ® ADS-933 FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. Data from both the interrupted and subsequent conversions will be invalid. If the output three-state register has been enabled (logic "0" applied to pin 34), data from the first conversion will appear at the output of the ADS-933. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the rising edge of EOC to the falling edge of EOC). Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. After the 15th rising edge brings the 16th data word to the FIFO output, the subsequent falling edge on READ will update the status outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating that the FIFO is empty. 7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1’s or when the input equals or exceeds the voltage that produces all 0’s. When COMP BITS is activated, the above conditions are reversed. INTERNAL FIFO OPERATION The ADS-933 contains an internal, user-initiated, 18-bit, 16word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and overflow bits. Pins 8 (FIFO/ DIR) and 9 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2). If a read command is issued after the FIFO empties, the last word (the 16th conversion) will remain present at the outputs. When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 8 has a logic "0" applied, the FIFO is transparent and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-933 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-933’s digital data path. FIFO Reset Feature At any time, the FIFO can be reset to an empty state by putting the ADS-933 into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs change 40ns after applying the control signals. FIFO Write and Read Modes FIFO Status, FSTAT1 and FSTAT2 Once the FIFO has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO. Monitor the status of the data in the FIFO by reading the two status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11). CONTENTS Empty (0 words) <half full (<8 words) half-full or more (≥8 words) Full (16 words) When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of the FSTAT1 0 0 1 1 FSTAT2 1 0 0 1 Table 1. FIFO Delays DELAY PIN TRANSITION Direct mode to FIFO enabled 8 FIFO enabled to direct mode 8 0 1 FIFO READ to output data valid 9 0 FIFO READ to status update when changing from <half full (1 word) to empty 9 1 FIFO READ to status update when changing from ≥half full (8 words) to <half full (7 words) 9 0 FIFO READ to status update when changing from full (16 words) to ≥half full (15 words) 9 0 Falling edge of EOC to status update when writing first word into empty FIFO 32 1 Falling edge of EOC to status update when changing FIFO from <half full (7 words) to ≥half full (8 words) 32 1 Falling edge of EOC to status update when filling FIFO with 16th word 32 1 4 MIN. TYP. MAX. UNITS – 10 20 ns 0 1 – 10 20 ns – – 40 ns 0 – – 20 ns 1 – – 110 ns – – 190 ns 0 – – 190 ns 0 – – 110 ns 0 – – 28 ns 1 1 ® ® ADS-933 CALIBRATION PROCEDURE Connect the converter per Figure 2. Any offset/gain calibration procedures should not be implemented until the device is fully warmed up. To avoid interaction, adjust offset before gain. The ranges of adjustment for the circuits in Figure 2 are guaranteed to compensate for the ADS-933’s initial accuracy errors and may not be able to compensate for additional system errors. LED's to the digital outputs and performing adjustments until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. For the ADS-933, offset adjusting is normally accomplished when the analog input is 0 minus ½ LSB (–42µV). See Table 2b for the proper bipolar output coding. A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This is accomplished by connecting 20kΩ –5V +5V –5V 6 GAIN ADJUST 31 4.7µF 38 0.1µF –5V 4.7µF 0.1µF +5V DIGITAL +5V ANALOG 37 –5V 34 ENABLE ADS-933 8 FIFO/DIR 10 FSTAT1 11 FSTAT2 1 0.1µF 33 32 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ANALOG 2, 4, 36 GROUND + 4.7µF 5 OFFSET ADJUST DIGITAL 7, 30 GROUND + +5V 0.1µF Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without zero/offset adjustment. Connect pin 6 to pin 4 for operation without gain adjustment. 20kΩ +5V +5V Gain adjusting is accomplished when the analog input is at nominal full scale minus 1½ LSB's (+2.749874V). ANALOG INPUT 3 FIFO READ 9 Zero/Offset Adjust Procedure OVERFLOW EOC BIT 1 (MSB) BIT 1 (MSB) BIT2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 BIT 15 BIT 16 (LSB) 1. Apply a train of pulses to the START CONVERT input (pin 12) so that the converter is continuously converting. 2. For zero/offset adjust, apply –42µV to the ANALOG INPUT (pin 3). 3. Adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (complementary offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binary). 4. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the trimpot until the output code flickers between all 0’s and all 1’s. +5V +3.2V REF. OUT Gain Adjust Procedure START CONVERT 12 4.7µF 1. For gain adjust, apply +2.749874V to the ANALOG INPUT (pin 3). COMP. BITS 35 Figure 2. Connection Diagram 2. Adjust the gain potentiometer until all output bits are 0’s and the LSB flickers between a 1 and 0 with pin 35 tied high (complementary offset binary) or until all output bits are 1’s and the LSB flickers between a 1 and 0 with pin 35 tied low (offset binary). Table 2a. Setting Output Coding Selection (Pin 35) OUTPUT FORMAT PIN 35 LOGIC LEVEL Complementary Offset Binary 1 Offset Binary 0 Complementary Two’s Complement (Using MSB, pin 29) 1 Two’s Complement (Using MSB, pin 29) 0 3. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the gain trimpot until the output code flickers equally between 0111 1111 1111 1111 and 0111 1111 1111 1110. 4. To confirm proper operation of the device, vary the applied input voltage to obtain the output coding listed in Table 2b. Table 2b. Output Coding OUTPUT CODING MSB LSB MSB 1111 1111 1111 LSB "1" to "0" 1110 0000 0000 1100 0000 0000 1000 0000 0000 0111 1111 1111 0100 0000 0000 0010 0000 0000 0000 0000 0000 LSB "0" to "1" 0000 0000 0000 1111 0000 0000 0000 0000 LSB "0" to "1" 0001 1111 1111 1111 0011 1111 1111 1111 0111 1111 1111 1111 1000 000 000 0000 1011 1111 1111 1111 1101 1111 1111 1111 1111 1111 1111 1110 LSB "1" to "0" 1111 1111 1111 1111 0111 1111 1111 1111 LSB "1" to "0" 0110 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1100 0000 0000 0000 1010 0000 0000 0000 1000 0000 0000 0001 LSB "0" to "1" 1000 0000 0000 0000 1000 0000 0000 0000 LSB "0" to "1" 1001 1111 1111 1111 1011 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0011 1111 1111 1111 0101 1111 1111 1111 0111 1111 1111 1110 LSB "1" to "0" 0111 1111 1111 1111 COMP. OFF. BIN. TWO'S COMP. COMP. TWO'S COMP. 0000 0000 0000 1111 0000 0000 0001 0000 OFFSET BINARY LSB MSB LSB 5 MSB LSB INPUT RANGE ±2.75V BIPOLAR SCALE +2.749916 +2.749874 +2.062500 +1.375000 0.000000 –0.000084 –1.375000 –2.062500 –2.749916 –2.749958 –2.750000 +FS –1 LSB +FS –1 1/2 LSB +3/4 FS +1/2 FS 0 –1 LSB –1/2 FS –3/4 FS –FS +1 LSB –FS + 1/2 LSB –FS ® ® ADS-933 THERMAL REQUIREMENTS underneath the package. Devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70°C and –55 to +125°C. All room-temperature (TA = +25°C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of DATEL's HS Series heat sinks. See Ordering Information for the assigned part number. See page 1-183 of the DATEL Data Acquisition Components Catalog for more information on the HS Series. Request DATEL Application Note AN-8, "Heat Sinks for DIP Data Converters," or contact DATEL directly, for additional information. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically insulating, thermally-conductive "pads" may be installed N N+1 START CONVERT N+2 N+4 N+3 N+5 50ns typ. Acquisition Time 170ns typ. 20ns typ. INTERNAL S/H Hold 161ns typ. Conversion Time 178ns typ. 53ns typ. EOC 265ns typ. 20ns typ. OUTPUT DATA Data N-4 Valid Data N-3 Valid Data N-2 Valid Data N-1 Valid Data N Valid Invalid Data 68ns typ. Notes: 1. Scale is approximately 50ns per division. fs = 3MHz. 2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data from the first conversion to appear at the output of the A/D. 3. The start convert positive pulse width must be between either 20 and 60nsec or 200 and 310nsec (when sampling at 3MHz) to ensure proper operation. For sampling rates lower than 3MHz, the start pulse can be wider than 310nsec, however a minimum pulse width low of 20nsec should be maintained. A 3MHz clock with a 50nsec positive pulse width is used for all production testing. Figure 3. ADS-933 Timing Diagram 6 7 3MHZ X1 13 8 14 8 9 14 B1 1 C9 2.2µF DGND R3 20mH L3 20mH L2 ADS-933 EVALUATION BOARD SG4 AGND C13 2.2µF 20mH AGND C11 2.2µF L1 1 SG5 OFFSET ADJUST +5VA –5VA +5VD +5VF 2 AGND AGND C2 2.2µF AGND 20mH 3.3k C7 2.2µF DGND +15V DGND +5VA –15V –5VA +5VD 2 6 5 C10 1 33pF 2 1 74HCT74 U1 4 +5VF 6 SG3 25 23 21 19 17 15 13 11 9 7 5 3 1 J1 3 2 3 2 1 DGND DGND C6 2.2µF +5VF 4 7 C1 2.2µF L4 P2 0.1µF C5 AR1 R2 SG2 SG1 26 24 22 20 18 16 14 12 10 8 6 4 2 50 R6 3 2 DGND START CONVERT 7 1 AGND DGND 7 74HCT74 U1 DGND 11 12 10 2 AGND +5VF B2 ANALOG INPUT AMPLIFIER OPTION AGND R1 3 1 –5VA R4 20k +5VA DGND SG9 RD FIF 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B9 B10 B11 B12 B13 B14 B15 LSB START FSTAT2 FSTAT1 READ FIFO/DIR DGND GAIN OFFSET AGND ANA IN AGND +3.2VREF AGND C3 0.1µF –5VA DGND U6 UUT 38 39 40 COMP AGND 21 22 23 24 25 26 27 28 29 30 31 32 33 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 +5VD COMP –5VA +5VA DGND C15 0.1µF 12 13 11 FST1 7 74HC86 U5 14 74HC86 8 U5 FST2 DGND +5VF 9 10 74HC86 1 3 U5 EOC 2 B8 B7 B6 B5 B4 B3 B2 MSB MSB DGND +5VD EOC OF 34 35 36 -5VA 37 +5VA NC NC ENABLE C4 2.2µF +5VF AB2 AB1 C16 0.1µF AB8 C8 0.1µF +5VF AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 DGND DGND C17 0.1µF +5VF AB7 AB6 AB5 AB4 DGND AB3 +5VF 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 11 20 11 20 11 20 U3 U4 1 10 1 10 1 U2 10 Figure 5. ADS-933 Evaluation Board Schematic. 3 GAIN ADJUST +5VA 1 R5 20k 2 74HC86 4 6 START U5 CONVERT 5 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 –15V –5VA +15V +5VA SG6 SG8 SG7 74HCT573 74HCT573 74HCT573 DGND 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 B9 B10 B11 B12 B13 B14 B15 +5VD FIF RD DGND COMP START B16 (LSB) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1(MSB) AGND 19 13 15 17 1 3 5 7 9 FST2 FST1 1 2 3 1 2 3 J5 J4 1 2 3 J3 FIFO/DIR READ COMPLIM ENABLE FIF/DIR N.C. READ AGND DGND C21 2.2µF +5VA C12 2.2µF COMPLIM ENABLE DGND DGND DGND 1 2 3 J2 2 4 6 8 10 DGND DGND 21 DGND 23 25 12 11 14 16 18 EOC 27 DGND 29 31 OVRFLW 33 B1B MSB P1 20 22 24 26 28 30 32 –5VA AGND C14 2.2µF +5VD DGND 34 C20 0.1µF +5VA C19 0.1µF –5VA AGND 0.1µF 0.1µF DGND C18 0.1µF +5VD B16 (LSB) DGND B8 B7 B6 B5 B4 B3 B2 B1 (MSB) DGND 19 B1B MSB 18 OVRFLW 17 16 15 14 13 12 ® ® ADS-933 ® ® ADS-933 MECHANICAL DIMENSIONS INCHES (mm) 2.12/2.07 (53.85/52.58) 40 Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) 21 Lead Material: Kovar alloy 1.11/1.08 (28.20/27.43) 1 Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 20 0.100 TYP. (2.540) 1.900 ±0.008 (48.260) 0.245 MAX. (6.223) PIN 1 INDEX ( ON TOP) 0.200/0.175 (5.080/4.445) 0.015/0.009 (0.381/0.229) 0.210 MAX. (5.334) 0.018 ±0.002 (0.457) 0.900 ±0.010 (22.86) 0.110/0.090 (2.794/2.286) 0.110/0.090 (2.794/2.286 SEATING PLANE 0.035/0.015 (0.889/0.381) 0.045/0.035 (1.143/0.889) ORDERING INFORMATION MODEL OPERATING TEMP. RANGE ANALOG INPUT ADS-933MC ADS-933MM 0 to +70°C –55 to +125°C Bipolar (±2.75V) Bipolar (±2.75V) ACCESSORIES ADS-B933 HS-40 Evaluation Board (without ADS-933) Heat Sink for all ADS-933 models Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL. ® ® INNOVATION and EXCELLENCE ISO 9001 R E G I S T E R E D DS-0367P DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com E-mail: [email protected] Data sheet fax back: (508) 261-2857 05/97 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 DATEL GmbH München, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.