www.murata-ps.com ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter PRELIMINARY PRODUCT OVERVIEW The ADSQ-1410 is a quad 10MSPS sampling A/D optimized for applications where low noise performance and the ability to convert full-scale step input signals at a 10 MHz conversion rate are required. With excellent dynamic performance up to Nyquist frequencies, the ADSQ-1410 is also an ideal choice for multi-channel, frequency domain applications. This functionally complete quad A/D uses a single rising edge triggered Start Convert signal to control the conversion cycles of all four A/D’s. The digital CMOS outputs are multiplexed into pairs providing two parallel, 3-state output buses. Four indepen- FEATURES dent Enable Control pins offer individual output data and overflow/underflow selection. A 2.5V precision internal reference, along with individual analog input range selection pins, provides ideal tracking over temperature while allowing each channel to be independently configured for an analog input range of ±1V to ±2.5V. Available in both surface-mount and through-hole packages, the ADSQ-1410 requires only ±5V for internal analog supplies and 2V to 5V supply for logic outputs. Typical power dissipation is 2.7 Watts. Common applications include medical imaging, radar, sonar, communications and instrumentation. FUNCTIONAL BLOCK DIAGRAM Quad 14-bit resolution; 10 MSPS sampling rate Individual channel selectable ±1V to ±2.5V input range Individual channel offset and gain adjustment capabilities Functionally complete; low cost Low noise: 0.5 LSB RMS; no missing codes Excellent dynamic performance: SNR 80db 2V to 5V CMOS logic outputs with overflow/ underflow; 3-latency delays Rising edge-triggered; Individual channel enable / Hi-z outputs ±5V and +2VDD to +5VDD logic output supplies 66-pin SMT or TDIP package 20 Overflow_AB 66 B1 (MSB) AB +5V 4, 10, 25, 30 -5V 5, 11 64 B3 AB 63 B4 AB Offset Adj A 3 52 EN A Input A 1 62 B5 AB 61 B6 AB 3-State Register Sub-Ranging A/D A SGND A 2 60 B7 AB 59 B8 AB Range A 13 58 B9 AB 57 B10 AB Offset Adj B 31 Sub-Ranging A/D B Input B 33 56 B11 AB 3-State Register 55 B12 AB SGND B 32 54 B13 AB 48 EN B Range B 17 53 B14 (LSB) AB 51 EN C Offset Adj C 9 Sub-Ranging A/D C Input C 7 21 Overflow_CD 3-State Register 47 B1 (MSB) CD 46 B2 CD SGND C 8 45 B3 CD Range C 15 44 B4 CD Developed for image processing applications Ideal for both time and frequency domain applications 65 B2 AB +VDD 19, 22 Sub-Ranging A/D D Offset Adj D 26 43 B5 CD 3-State Register 42 B6 CD Input D 28 41 B7 CD 49 EN D SGND D 27 40 B8 CD 39 B9 CD Range D 16 38 B10 CD Timing and Control +2.5V REF 14 50 START CONV 2.5V REF 37 B11 CD 36 B12 CD 35 B13 CD AGND 6, 12, 24, 29 OGND 18, 23 34 B14 (LSB) CD For full details go to www.murata-ps.com/rohs www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 1 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter ABSOLUTE MAXIMUM RATINGS Parameters Min. Typ. Max. Units +5VA Supply (Pin 4,10,25,30) 0 – +5.5 Volts –5VA Supply (Pin 5,11) 0 – –5.5 Volts +VDD (Pins 19,22) 0 – +7V Volts Digital Input (Pin 48,49,50,51,52) –0.3 – +VDD +0.5 Volts Analog Input (Pin 1,7,13,15,16,17,28) –5 – +5 Volts Lead Temperature soldering 10sec – – 300 °C FUNCTIONAL SPECIFICATIONS (TA = +25°C, VCC = +5V, +VDD = +3.3V, VEE = –5V, 10MSPS sampling rate, VIN = ±2.5V and a minimum 1 minute warmup unless otherwise specified.) Analog Input Min. Typ. Max. Units Input Voltage Range ±1 – ±2.5 Volts Input Impedence – 470 – Ω Input Capacitance – 2 7 pF +2.4 0.5 2.1 1.6 – – +VDD – +0.8 Volts Volts Volts Volts Volts – – – – +10 –10 uA uA Digital Inputs Logic Levels Logic 1 START CONV Logic 1 ENABLE VDD 2V Logic 1 ENABLE VDD 3.3V Logic 1 ENABLE VDD 5.0V Logic 0 Logic Loading Logic 1 Logic 0 Performance Differential Nonlinearity (fin = 975kHz) +25°C 0 to 70°C Extended temperature range –0.99 –0.99 TBD ±0.5 ±0.5 TBD – – – LSB LSB LSB Integral Nonlinearity +25°C 0 to 70°C Extended temperature range – – – ±2.5 ±3.0 TBD – – – LSB LSB LSB Guaranteed No Missing Codes 0 to 70°C Resolution Zero Error +25°C 0 to 70°C Extended temperature range Gain Error +25°C 0 to 70°C Extended temperature range 14 Bits – – – – – – 0.3 0.3 TBD 0.6 TBD TBD – – – – – – %FSR %FSR %FSR %FSR %FSR %FSR Output Output Coding Logic Level Logic 1 (–4mA) +VDD = +3.3V Logic 0 (4mA) +VDD = +3.3V Logic Loading 1 +VDD = +3.3V Logic Loading 0 +VDD = +3.3V – – – – – +0.5 -4 +4 2.495 2.495 – +2.5 +2.5 – 2.505 2.505 5 Volts Volts mA Dynamic Performance Min. Typ. Max. Units – – – -89.5 -88.5 -87.6 – – – db db db – – – -81.3 -81 -78 – – – db db db – – – 74.8 74.8 74.6 – – – db db db – – – 80.4 80.2 79.6 – – – db db db – – – 74.6 74.6 74.4 – – – db db db – – – 78.2 78 77 – – – db db db – – – -94.9 -92.1 -91.2 – – – db db db – – – -85.5 -85 -80 – – – db db db Input Bandwidth Small Signal (–20dB input) Large Signal (–3dB input) – – 33.5 8.5 – – MHz MHz Aperture Delay Time – 1 – ns Aperture Uncertainty – 4 – ps rms S/H Acquisition Time, (to ±0.003% FSR) – TBD – ns – -130 – dB – – 121 150 – – μVrms μVrms – – 0.99 0.5 – – LSB LSB Total Harmonic Distortion (–0.5dB) RANGE pin voltage = 1V 500kHz 1MHz to 5MHz RANGE pin voltage = 2.5V 500kHz 1MHz to 5MHz Signal-to-Noise Ratio (w/o distortion, –0.5dB) RANGE pin voltage = 1V 500kHz 1MHz to 5MHz RANGE pin voltage = 2.5V 500kHz 1MHz to 5MHz Signal-to-Noise Ratio (distortion, –0.5dB) RANGE pin voltage = 1V 500kHz 1MHz to 5MHz RANGE pin voltage = 2.5V 500kHz 1MHz to 5MHz Spurious Free Dynamic Range RANGE pin voltage = 1V 500kHz 1MHz to 5MHz RANGE pin voltage = 2.5V 500kHz 1MHz to 5MHz Feedthrough Rejection Channel under test Fin = 4.85MHz Other 3 channels Fin = 2.45MHz Offset Binary +2.9 – – – Internal Reference Voltage +25°C 0 to 70°C External Current Volts Volts mA mA www.murata-ps.com Noise RANGE pin voltage = 1V RANGE pin voltage = 2.5V (grounded input) RANGE pin voltage = 1V RANGE pin voltage = 2.5V Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 2 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter FUNCTIONAL SPECIFICATIONS, CONT. Power Requirements The fine gain adjustment range is equivalent to the amount of change induced at the RANGE pin. With the desired Fine Gain Adjustment (as a percent of full scale) and the maximum voltage expected from the Fine Gain Adjust circuitry known, and we select a value for R1 that minimizes the amount of current draw from Vref (typically 1kΩ range), we can then calculate the value for R3 to be: Power Supply Ranges +5VEE Supply –5VCC Supply +VDD Supply +4.75 –5.25 +2V +5.0 –5.0 +3.3 +5.25 –4.75 +5V Volts Volts Volts Power Supply Currents +5V Supply –5V Supply +VDD Supply – – – 390 140 12 430 155 20 mA mA mA Power Dissipation – 2.7 3.1 Watt Power Supply Rejection (5%) @25°C – – ±0.01 %FSR/%V Operating Temperature Range ADSQ-1410 ADSQ-1410EX 0 TBD – – +70 TBD °C °C Eq. 2: Storage Temperature –65 – +125 °C Where: RANGE is the unadjusted RANGE pin voltage Environmental Package Type Weight PCB R3 = R1 Vtrim Vref % 100 Where: Vtrim = the maximum Fine Gain Adjust voltage % = the percentage of desired trim range as a % of full scale Eq. 1: Defining RANGE as the unadjusted RANGE pin voltage (R3 tied to GND or Fine Gain Adjust = 0V), we can determine the value of R2 using the following equation: R2 = R1 R3 Range R3 Vref – Range (R1 + R3) 66-Pin, SMT, TDIP 23 grams FR-4 RoHS TG 170°C UL94-VO Plastic Shell Nylon 46, 30% GFR, Stanyl, UL94-VO Pins 0.020 Sq. Au Plate Phosphor Bronze For example: Using the circuit shown, a ± 1V output DAC is used to adjust the gain of a channel with an analog input range of ±2.0V by ± 5%. Resistor R1 is selected to be 1k Ohm. From Eq. 1: R3 = (1k x 1.0) / (2.0 x 0.05) = 8k Ohm. For an analog input range of ±2.0V the unadjusted RANGE voltage must be +2.0V. From Eq. 2: R2 = (1k x 8k x 2.0) / (8k x 2.5 - 2.0(1k +8k)) = 8k. Typical for all channels TECHNICAL NOTES The ADSQ-1410 is a designed to function as four-independent sampling A/D converters each with a selectable analog input range of ±1 to ±2.5 Volts and with independent offset and gain capabilities. Each channel of the ADSQ-1410 operates from its independent +5V supplies and analog grounds (AGND & SGND). Channels A&B share a common -5V, +VDD and OGND_AB (output ground), similarly channels C&D share -5V, +VDD and OGND_CD. This separation of channels along with strategically placed ground connections within the ADSQ-1410 provide the excellent channelto-channel isolation performance. For optimal performance PCB layout and high-speed / high resolution design practices should be observed. See Layout Considerations. RANGE & FINE GAIN ADJUSTMENT: The ADSQ-1410 allows the full-scale range of each individual channel to be adjusted from 2Vpp to 5Vpp. The ADSQ-1410 provides a precision +2.5V reference voltage that can be used with a resistor divider network to set each channel's desired full-scale range. The voltage applied to each individual RANGE pin will set the full-scale input of that channel to be: FS = 2 x RANGE pin voltage. Fine Gain adjustment can be attained with precision changes to the high impedance RANGE pins using a resistor divider network in conjunction with a DAC or adjustable voltage source as shown in the Gain Adjust figure. Setting the RANGE voltage and providing the proper amount of gain adjustment can be calculated using the following equations as referred to the circuitry shown in the Gain Adjust figure. www.murata-ps.com R2 Fine Gain Adjust R3 Channel A A/D Range Select (FS = 2 x VRANGE) RANGE_A R1 +2.5V REF +2.5V REF ADSQ-1410 Range / Gain Adjust OFFSET ADJUSTMENT Offset adjustment is accomplished by applying a ± voltage to the OFFSET ADJ circuitry as seen in the Input Stage figure. Offset adjustment calculations can be determined using the following equations. It should be noted that the factory trims that are required in several of the converter’s input stages will slightly alter the tolerance of the offset adjustment calculations. For Eq. 3 the number of desired codes of adjustment are inserted to determine the necessary voltage at the OFFSET ADJ pin. For example with RANGE voltage = 2.5 volts and ±78 codes of adjustment desired corresponds to ±1V at the OFFSET ADJ pin. Voffset = 2 Range (Codes) 0.0238 Where: RANGE = the RANGE pin voltage Codes = Desired offset adjustment range Eq. 3: Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 3 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter For applications that require small full scale input ranges less sensitivity may be required for offset adjustment. In this case an external series resistor can be added with the internal 20.5kΩ resistor on the OFFSET ADJ pin. In this case the Offset Voltage can be calculated by: Eq. 4: Typical for AB & CD Output Bus EN_A Voffset = 2 Range (Codes) 487.9 (Rexternal + 20500) A/D_ A Buffer_A AB Output Bus & Overflow Where: RANGE = the RANGE pin voltage Codes = Desired offset adjustment range Rexternal = External Offset series resistor (pins 54-66 & 20) A/D_ B Buffer_B EN_B 20.5k 470 OFFSET ADJ Output Block Diagram 470 To A/D Input Section VIN ±2.5V Parameter SGND ADSQ-1410 Quad Input Stage Symbol Min Start Conv Period tc 100 Start Conv Pulse High tch 45 Start Conv Pulse Low tcl 45 Output Delay tod 13 Typ Max Unit 1x106 ns ns ns 18 27 ns Table 1. Digital Output And Timing DIGITAL OUTPUT AND TIMING The ADSQ-1410 is configured such that the output bits and overflow for channels A&B are multiplexed on the AB Output Bus (pins 54 - 66 & 20) and channels C&D are similarly multiplexed on the CD Output Bus (pins 34-47 & 21). See the Output Block Diagram figure. The output drivers are designed to conveniently operate from VDD = +2V to +5V and are capable of sinking and sourcing up to 4mA of current. However, switching large drive currents can cause glitches on the supplies that could couple into and create disturbances on an ongoing A/D conversion affecting the SINAD and SNR performance. Applications where high drive current is required may require additional supply voltage bypassing or external digital buffers. The EN_ pins are used to select the appropriate output data. EN_ control pins are active LO (HI= high-z). Caution must be exercised to assure that both channels on the same bus are not enabled at the same time. Each data bus of the ADSQ-1410 is capable of providing data throughput at a 20MHz rate. See Enable and Disable timing diagrams and table. Input logic levels for EN_ pins are dictated by +VDD supply voltage; logic level for START_CONV is a function of +5V supply. See Functional Specifications: Digital Inputs. N N+1 ANALOG INPUT tC t CH N+2 t CL START CONV t OD DATA OUTPUT Data N-1 Data N Symbol Typ Max Hi-Z to Active HI t-pZH 6.6ns 10.6ns Hi-Z to Active LO t-pZL 6.6ns 10.6ns Active HI to Hi-Z t-pHZ 7.8ns 11.5ns Active LO to Hi-Z t-pLZ 7.8ns 11.5ns Data N-3 Data N-2 (Enable Pin = LO) ADSQ-1410 Timing Diagram Parameter Table 2. Enable and Disable Times NOTE: Outputs are enabled when ENABLE pins = LO (Hi-Z = HI). Caution must be taken to assure that shared outputs are not enabled at the same time. www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 4 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter VCC 50% VCC 50% VCC ENABLE 0V ➀ Output waveform 1 S1 at VCC t PZL t PZL –VCC 50% VCC VOL +0.3V VOL t PZH VOH +0.3V ➁ Output waveform 1 S1 at GND 50% VCC V OH –0V Voltage Waveforms Enable and Disable Times Low- and High-Level Enabling Enable and Disable Times ➀ Waveform 1 is for an output with internal conditions such that the output is active LO and Hi-Z is pulled 3.3VD through 1k resistor ➁ Waveform 2 is for an output with internal conditions such that the output is active LO and Hi-Z is pulled GND through 1k resistor 18ns typ (tod) START CONVERT ➀ N-2 N-3 DATA The START CONV command of the ADSQ-1410 is buffered internally prior to being distributed to each A/D convert. The multi-stage architecture of the internal A/D’s uses both the rising and falling edges of each START CONV pulse in the conversion process and therefore requires START CONV commands that maintain a minimum of 45ns for both the high and the low times. At 10MHz clock rate this would require a 50% (±5% )duty cycle. Due to the analog pipeline architecture of the A/D section a Start Convert period that exceeds 1ms will allow internal sample and holds to discharge the held voltages thereby affecting output integrity. Consequently a minimum Start convert rate of 1 kHz is specified. Clock jitter (aperture jitter) will result in a variation of time interval between successive A/D conversions which can adversely affect the signal to noise ratio performance. Low jitter crystal oscillators provide clock signals at a 50% duty cycle making ideal START CONV sources. Input logic levels for EN_ pins are dictated by +VDD supply voltage; logic level for START_CONV is a function of +5V supply. See Functional Specifications: Digital Inputs. Layout Considerations Although the ADSQ-1410 functions in both the analog and digital realms, in regards to layout it should be treated as an analog component. Grounding is critical in any high-speed, high resolution data acquisition system. As such a multilayer PCB is recommended to allow ground planes as well as isolation of digital and analog signals. Ground planes will significantly reduce impedance and minimize signal return loops. In addition, the power and ground planes can be arranged so as to provide inherent distributed capacitance within the PCB. 50ns typ. N Start Convert Considerations N-1 EN A 30ns The AGND, SGND and OGND grounds should all be connected to a common ground plane directly beneath the ADSQ-1410. Although using a common plane beneath the A/D, it may be beneficial to design notches or “keep-outs” in the ground plane so as to steer ground currents away from critical signal sensitive areas in the ground plane. 30ns Each channel of the quad A/D operates from its own supply voltages. Bypassing from each of these supplies should be done as close to the respective power and associated ground pins as possible. Bypass ceramic capacitor values of 1uF and 0.1uF are recommended in most application. EN B DATA A or B OUT or (C or D OUT) DATA-A N-3 DATA-B N-3 DATA-A N-2 DATA-B N-2 DATA-A N-1 6.6ns 7.8ns ➀ Assuming single channel OUTPUT ENABLED Enable Timing Diagram Overflow 1 0 0 0 0 0 0 0 0 1 Output Coding MSB LSB Input Range ±2.5V Bipolar Scale 11 11 11 11 10 01 00 00 00 00 +2.499847 +2.499695 +1.875000 +1.250000 ±0.000000 –1.250000 –1.875000 –2.499848 –2.500000 –2.500153 +FS – 1/2LSB +FS – 1LSB 3/4 FS +1/2 FS 0 –1/2 FS –3/4 FS –FS +1LSB –FS –FS –1/2LSB 1111 1111 1100 0000 0000 0000 1000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0001 0000 0000 In order to prevent digital switching noise from being coupled into sensitive analog signal paths, the layout designer should assure that digital signals do not run parallel with signal traces. For ease of layout the ADSQ1410 is designed with all Digital Outputs and START CONVERT one side of the package and signal pins on the other. The +2.5V REF pin is used in conjunction with external components to set the RANGE of each channel. Care should be exercised to assure that the Reference voltage and its associated divided down voltage applied to the RANGE pins are bypassed properly and not subject to noise pickup from digital paths. Typical Application Connection Diagram The ADSQ-1410 is a functionally complete quad A/D and as such requires little externally circuitry for operation. The figure (connection diagram) shows the typical circuit connections with channels A, B, C operating with a ±2.5V input range and channel D operating with a gain adjustable input range less than ±2.5V. Table 3. Output Coding www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 5 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter +5V -5V_CD -5V_AB +VDD 20 Overflow_AB 66 B1 (MSB) AB 4,10,25,30 11 5 65 B2 AB 19,22 64 B3 AB 1 Input A 2 3 ±V Input A 63 B4 AB SGND A 62 B5 AB Offset Adj A 61 B6 AB 60 B7 AB Input B ±V 33 Input B 59 B8 AB 32 SGND B 58 B9 AB 31 Offset Adj B 57 B10 AB 56 B11 AB Input C 55 B12 AB ADSQ-1410 7 Input C 8 SGND C 9 Offset Adj C 54 B13 AB 53 B14 (LSB) AB ±V Input D 21 Overflow _CD 28 Input D 27 SGND D 26 Offset Adj D 47 B1 (MSB) CD 46 B2 CD ±V 14 +2.5 VREF 13 RANGE A 17 RANGE B 45 B3 CD 44 B4 CD 43 B5 CD 15 42 B6 CD 41 B7 CD 40 B8 CD RANGE C RANGE D Channel D 16 Fine Gain Adjust AGND 6,12, OGND 18, 23 ENA ENB ENC END START CONV 52 48 51 49 50 24,29 R1 39 B9 CD 38 B10 CD 37 B11 CD 36 B12 CD ±V R3 35 B13 CD R2 * Diagram shown with channels A thru C input full scale range equal to ±2.5V with no gain adjustment. Channel D input range set to < ±2.5V with fine gain adjustment. 34 B14 (LSB) CD Connection Diagram www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 6 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter PIN FUNCTIONS PIN FUNCTIONS, CONT. Pin Number Name Description 1, 7, 28, 33 2, 8, 27, 32 3, 9, 26, 31 4, 10, 25, 30 5, 11 6, 12, 24, 29 13 14 15 16 17 18, 23 19, 22 34-47 21 48 49 50 51 52 53-66 20 Signal Input for Respective Channel Signal Ground for Respective Channel Offset Adjust for Respective Channel +5V Analog Supply for Respective Channel -5V Analog Supply for Respective Channel Analog Ground for Respective Channel Channel A Range Adjustment +2.5V Reference Output Voltage Channel C Range Adjustment Channel D Range Adjustment Channel B Range Adjustment Digital Ground for Respective Channel Output Supply for Respective Channel Data Output Bits for Channels C&D Overflow/Underflow for Channels C&D Output Enable Channel B Output Enable Channel D Start Convert for all Channels Output Enable Channel C Output Enable Channel A Data Output Bits for Channels A&B Overflow/Underflow for Channels A&B INPUT (A, C, D, B) SGND (A, C, D, B) OFFSET ADJ (A, C, D, B) +5V (A, C, D, B) -5V (A, C, D, B) AGND (AB, CD) RANGE_A +2.5V REF Range_C Range D Range B OGND_AB +VDD (AB, CD) DATA OUT_CD Overflow_CD EN_B EN_D START CONV EN_C EN_A DATA OUT_AB Overflow_AB Table 3. Pin Function Description INPUT (A, C, D, B) - Pins 1, 7, 28, 33: Analog Input Signal for respective channels. SGND (A, C, D, B) - Pins 2, 8, 27, 32: Signal ground for respective channels. SGND connected to AGND and DGND at strategic locations within the ADSQ-1410. OFFSET ADJ (A, C, D, B) - Pins 3, 9, 26, 31: Provides independent offset adjustment for each channel. Designed for ± voltages applied to OFFSET ADJ pin; leave floating or tied to GND for non-adjustment applications. Applying -1V reduces output by approx. 76 codes; applying +1.0V increases output by approx. 76 codes with RANGE = 2.5V. +5V (A, C, D, B) - Pins 4, 10, 25, 30: Individual +5V analog supply pins for each channel. Bypass to respective AGND pins with 1uF and 0.1uF ceramic capacitors. -5V (AB, CD) - Pins 5, 11: Individual -5V analog supply pins for each channel. Bypass to respective AGND pins with 1uF and 0.1uF ceramic capacitors. AGND (A, C, D, B) - Pins 6, 12, 24, 29: Analog ground (+5V and -5V returns) for respective channels. AGND connected to SGND and DGND at strategic locations within the ADSQ-1410. RANGE (A, B, C, D) - Pin 13, 15, 16, 17: Used with +2.5V REF to select the respective channel's full scale input range and fine gain adjustment. See Range and Calibration section. +2.5V REF - Pin 14: Precision +2.5V output voltage used with RANGE to select full scale input range for all channels. See Range and Calibration section. Bypass to AGND Plane. www.murata-ps.com +VDD (AB, CD) - Pins 19, 22: Supply voltage for digital circuitry. Channels AB share common supply pin, channels CD share common supply pin. Bypass to respective OGND pins with 1uF and 0.1uF ceramic capacitors. OGND (AB, CD) - Pins 18, 23: Output ground (OGND_AB and OGND_CD returns) for associated channels. OGND is connected to AGND and other OGND at strategic locations within the ADSQ-1410. DATA_OUT_CD – Pins 34 – 47: Digital data from channels C&D are buffered internally, with the capability of selecting between active and High-Z states, and brought out on the DATA_OUT_CD pins. Selection between C or D is controlled by EN_C and EN_D control pins. DATA OUT employs the offset binary coding format and is powered from +VDD_CD supply. OVERFLOW_CD - Pin 21: Overflow is a digital output that is multiplexed onto the output data bus in the same manner as the data bits and is enabled or inactive (High-Z) along with the corresponding) data outputs (same latency delay via the respective EN control pin. The signal is LO when the data is within the valid input range of the corresponding A/D converter and HI when the input signal is: +FS-1/2LSB <input> -FS-1/2LSB. EN_C - Pin 51: Control pin for channel C output data. The data output for channel C is buffered internally with the capability to select between active and High-Z states. The channel C data output shares pins with channel D (DATA_OUT_CD). Caution must be exercised to assure that channel C and channel D are not enabled at the same time. A LO enables the corresponding channel's output data; a HI places the channel into a High-Z state. EN_D - Pin 49: Control pin for channel D output data. The data output for channel D is buffered internally with the capability to select between active and High-Z states. The channel D data output shares pins with channel C (DATA_OUT_CD). Caution must be exercised to assure that channel D and channel C are not enabled at the same time. DATA_OUT_AB – Pins 53 – 66: Digital data from channels A&B are buffered internally, with the capability of selecting between active and High-Z states, and brought out on the DATA_OUT_AB pins. Selection between A or B is controlled by EN_A and EN_B control pins. DATA OUT employs the offset binary coding format and is powered from +VDD_AB supply. A LO enables the corresponding channel's output data; a HI places the channel into a High-Z state. OVERFLOW_AB - Pin 20: Overflow is a digital output that is multiplexed onto the output data bus in the same manner as the data bits and is enabled or inactive (High-Z) along with the corresponding) data outputs (same latency delay via the respective EN control pin. The signal is LO when the data is within the valid input range of the corresponding A/D converter and HI when the input signal is: +FS-1/2LSB <input> -FS-1/2LSB. EN_A - Pin 52: Control pin for channel A output data. The data output for channel A is buffered internally with the capability to select between active and High-Z states. The channel A data output shares pins with channel B (DATA_OUT_AB). Caution must be exercised to assure that channel A and channel B are not enabled at the same time. A LO enables the corresponding channel's output data; a HI places the channel into a High-Z state. EN_B - Pin 48: Control pin for channel B output data. The data output for channel B is buffered internally with the capability to select between active and High-Z states. The channel B data output shares pins with channel A (DATA_OUT_AB). Caution must be exercised to assure that channel B and channel A are not enabled at the same time. A LO enables the corresponding channel's output data; a HI places the channel into a High-Z state. Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 7 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter SPECIFICATION DEFINITIONS Typical Performance Curves and Plots Total Harmonic Distortion (THD): Ratio of total RMS harmonic power to RMS fundamental power Dynamic DNL Fs: 4.85 MHz Fs: 10MHz Range Voltage: 2.5V THD = 10 X log (RMS of all harmonics/RMS of fundamental) SNR With Distortion (SINAD): Ratio of RMS power present in output, excluding fundamental: to the RMS fundamental power SINAD = 10 X log (fundamental RMS / RMS of remaining output); expressed in db SNR without Distortion (SNR): Ratio of RMS power present in output, excluding fundamental and harmonics: to the RMS power of the fundamental SNR = 10 X log (fundamental RMS / RMS of power present in output, excluding fundamental and harmonics, to the fundamental; expressed in db 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 Spurious Free Dynamic Range (SFDR): Difference between fundamental peak value and the value of highest spike present in the output (harmonic or spur). SFRD = Fundamental (dB) – Highest Spur (dB) ; expressed in db PSSR: Survo-loop is employed applying an input voltage that forces output codes to FS-1LSB. One supply voltage is changed to the specified limits and any change in input voltage recorded. The change in input voltage is divided by the full scale voltage and then divided by percent change in power supplies. The resulting units are % / %. Zero Error: Survo-loop is employed applying an input voltage that forces output codes to: Unipolar devices - LSB on half of the time and all other bits off. Bipolar devices - MSB on, the LSB on half the time and all other bits off. Grounded Input Histogram 16384 points RANGE pin = 2.5V 80% 70% 60% 50% 40% 30% 20% The input voltage is compared to 0V. The result is = Input voltage - 0.5 LSB. 10% 0% Offset Error: Survo-loop is employed applying an input voltage that forces output codes to LSB on half of the time, and all other bits off. 8193 The input voltage is compared to 0V for unipolar devices, and -0.5 X full scale for bipolar devices. The result is this difference - 0.5 LSBs. Full Scale Absolute Accuracy: Survo-loop is employed applying an input voltage that forces output codes to LSB on half of the time and all other bits on. The input voltage is compared to full scale for unipolar devices, and 0.5 X full scale for bipolar devices. The result is this difference + 1.5 LSBs. Gain Error: The result is the difference between the Offset Error result and the Full Scale Absolute Accuracy result. Dynamic DNL Min: An AC signal is input to the device. 2n x 128 (2.1e6 for 14 bit converter) samples are taken, and the number of times each code appears is recorded. The data is normalized using ideal sine wave values. The result is the most negative and most positive numbers in the array. 8194 More Grounded Input Histogram 16384 points RANGE pin = 1V 50.00% 40.00% 30.00% 20.00% 10.00% Grounded Input RMS Noise: Input to the device is tied to Signal Ground. 2n x 128 (2.1e6 for 14 bit converter) samples are taken and stored in an array. The result is the RMS value of this array. www.murata-ps.com 0.00% 8196 8197 8198 8199 8200 8201 8202 8203 More Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 8 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter Typical Performance Curves and Plots FFT 16384 points Fs: 480 kHz Fs: 10MHz Range pin voltage: 2.5V 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 FFT 16384 points Fs: 480 kHz Fs: 10MHz Range pin voltage: 1V 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 FFT 16384 points Fs: 975 kHz Fs: 10MHz Range pin voltage: 2.5V FFT 16384 points Fs: 975 kHz Fs: 10MHz Range pin voltage: 1V 0 -10 -20 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 FFT 16384 points Fs: 2.45 MHz Fs: 10MHz Range pin voltage: 2.5V 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 FFT 16384 points Fs: 2.45 MHz Fs: 10MHz Range pin voltage: 1V 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 9 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter Typical Performance Curves and Plots FFT 16384 points Fs: 4.85 MHz Fs: 10MHz Range pin voltage: 2.5V FFT 16384 points Fs: 4.85 MHz Fs: 10MHz Range pin voltage: 1V 0 -10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 Cross-talk SNR 4.85MHz Input Frequency on Channel under Test 2.42MHz Input Frequency on other 3 Channels Cross-talk SINAD 4.85MHz Input Frequency on Channel under Test 2.42MHz Input Frequency on other 3 Channels 78.00 81.00 80.50 77.00 80.00 76.00 79.50 75.00 79.00 78.50 74.00 78.00 73.00 77.50 72.00 77.00 71.00 76.50 ADSQ CH_D with 2.42MHz on A,B,C ADSQ CH_D Stand Alone ADSQ CH_C with 2.42MHz on A,B,D ADSQ CH_C Stand Alone ADSQ CH_B with 2.42MHz on A,C,D Cross-talk Grounded Input Histogram Test Channel tied to GND – Other 3 Channels with 2.45 MHz FS Input Signal 80% 80% 70% 70% 60% 60% 50% 50% 40% 40% 30% 30% 20% 20% 10% 10% 0% ADSQ CH_B Stand Alone ADSQ CH_A Stand Alone ADSQ CH_D with 2.42MHz on A,B,C ADSQ CH_D Stand Alone ADSQ CH_C with 2.42MHz on A,B,D ADSQ CH_C Stand Alone ADSQ CH_B with 2.42MHz on A,C,D ADSQ CH_B Stand Alone ADSQ CH_A with 2.42MHz on B,C,D ADSQ CH_A Stand Alone Cross-talk Grounded Input Histogram Test channel tied to GND – Other 3 Channels Grounded ADSQ CH_A with 2.42MHz on B,C,D 70.00 76.00 0% 8193 8194 More www.murata-ps.com 8193 8194 More Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 10 of 11 ADSQ-1410 Quad 14-Bit, 10 MSPS Sampling A/D Converter INPUT/OUTPUT CONNECTIONS MECHANICAL SPECIFICATIONS QUAD INDEPENDENT ADSQ-1410 1.10 [27.94] PIN FUNCTION PIN FUNCTION 1 INPUT A 66 B1 AB (MSB) 2 SGND A 65 B2 AB 3 OFFSET ADJ A 64 B3 AB 4 +5V A 63 B4 AB 5 –5V A 62 B5 AB 6 AGND A 61 B6 AB 7 INPUT C 60 B7 AB 8 SGND C 59 B8 AB 9 OFFSET ADJ C 58 B9 AB 10 +5V C 57 B10 AB 11 –5V CD 56 B11 AB 12 AGND C 55 B12 AB 13 RANGE A 54 B13 AB 14 +2.5V REF 53 B14 AB (LSB) 15 RANGE C 52 EN A 16 RANGE D 51 EN C 17 RANGE B 50 START CONV 18 OGND_AB 49 EN D MODEL 19 +VDD_AB 48 EN B 20 OVERFLOW_AB 47 B1 CD (MSB) ADSQ-1410-C ADSQ-1410-EX-C 21 OVERFLOW_CD 46 B2 CD 22 +VDD_CD 45 B3 CD 23 OGND_CD 44 B4 CD 24 AGND D 43 B5 CD 25 +5V D 42 B6 CD 26 OFFSET ADJ D 41 B7 CD 27 SGND D 40 B8 CD 28 INPUT D 39 B9 CD 29 AGND B 38 B10 CD 30 +5V B 37 B11 CD 31 OFFSET ADJ B 36 B12 CD 32 SGND B 35 B13 CD 33 INPUT B 34 B14 CD (LSB) Unless Otherwise Specified Tolerances: .xx ±.02 .xxx ±.010 Dimensions in Inches [mm] Pin 1 Indicator 3.40 [86.36] 0.39 [9.91] Max 0.20 [5.08] Ref 0.100 [2.54] Typ 0.900 [22.86] 3.200 [81.28] 0.10 [2.54] Pin 1 33 0.10 [2.54] 66 66X .020±.002 Gold Plated Copper Alloy Pin 34 ORDERING INFORMATION Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 www.murata-ps.com email: [email protected] ISO 9001 and 14001 REGISTERED 05/18/09 Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. © 2009 Murata Power Solutions, Inc. www.murata-ps.com OPERATING TEMPERATURE RANGE 0 to 70°C PACKAGE (66-PIN) SMT Thru-hole TBD SMT Thru-hole USA: Mansfield (MA), Tel: (508) 339-3000, email: [email protected] Canada: Toronto, Tel: (866) 740-1232, email: [email protected] UK: Milton Keynes, Tel: +44 (0)1908 615232, email: [email protected] France: Montigny Le Bretonneux, Tel: +33 (0)1 34 60 01 01, email: [email protected] Germany: München, Tel: +49 (0)89-544334-0, email: [email protected] Japan: Tokyo, Tel: 3-3779-1031, email: [email protected] Osaka, Tel: 6-6354-2025, email: [email protected] China: Shanghai, Tel: +86 215 027 3678, email: [email protected] Guangzhou, Tel: +86 208 221 8066, email: [email protected] Singapore: Parkway Centre, Tel: +65 6348 9096, email: [email protected] Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADSQ.B01 Page 11 of 11