NJW1110 9-Input 3-Output Stereo Audio Selector ! GENERAL DESCRIPTION NJW1110 is a 9-input 3-output stereo audio selector. It includes three independent 9input-1output stereo audio selectors and adjustable gain buffers. NJW1110 performs superior audio characteristics such as low distortion, low output noise and low crosstalk. All of internal status and variables are 2 controlled by I C BUS interface. And the slave address selector is available for using two chips on same serial Bus line. It is suitable for latest TV system and others. ! PACKAGE OUTLINE NJW1110V ! APPLICATIONS •FPD TV •Car Audio System •Monitor ! FEATURES • Operating Voltage 7.5 to 15V • Operating Current 8mA typ. • 9-Input, 3-Output Stereo Audio Selector • Low Distortion 0.0007% typ. • Low Output Noise 116dBV typ. • Low Crosstalk 110dB typ. • Channel Separation 110dB typ. • Variable Gain Buffer 0, 3 to 8dB/0.5dB step 2 • I C Bus Interface (Comply with fast mode and 3V I/F) • Selectable 2-Slave Address • Bi-CMOS Technology • Package Outline SSOP32 ! BLOCK DIAGRAM InB1 InB2 InB3 InB4 InB5 InB6 InB7 InB8 InB9 OutB1 OutB2 OutB3 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF + + + + + + + + + + + + + 32 31 30 29 28 27 26 22 21 25 24 23 ADR V+ + 100µF 20 19 18 17 GND MUTE Gain Gain 8dB to 3dB / 0.5dBstep 50KΩX18 Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Vref Gain 8dB to 3dB / 0.5dBstep 8dB to 3dB / 0.5dBstep I2C Control Logic MUTE GND 1 10µF + InA1 2 10µF + InA2 3 10µF + InA3 4 10µF + InA4 5 10µF + InA5 6 10µF + InA6 7 10µF + InA7 8 10µF + InA8 9 10µF + InA9 GND 10 11 10µF + OutA1 12 10µF + OutA2 13 10µF 14 15 16 SDA SCL + OutA3 –1– NJW1110 ! PIN CONFIGURATION 1 InA1 InB1 32 2 InA2 InB2 31 3 InA3 InB3 30 4 InA4 InB4 29 5 InA5 InB5 28 6 InA6 InB6 27 7 InA7 InB7 26 8 InA8 InB8 25 9 InA9 InB9 24 10 GND Vref 23 11 OutA1 OutB1 22 12 OutA2 OutB2 21 13 OutA3 OutB3 20 14 GND GND 19 15 SDA ADR 18 16 16 SCL V+ 17 No. Symbol Function No. Symbol Function 1 InA1 Ach Input 1 17 V+ Power Supply Terminal 2 InA2 Ach Input 2 18 ADR Slave address setting terminal 3 InA3 Ach Input 3 19 GND GND Terminal 4 InA4 Ach Input 4 20 OutB3 Bch Output 3 5 InA5 Ach Input 5 21 OutB2 Bch Output 2 6 InA6 Ach Input 6 22 OutB1 Bch Output 1 7 InA7 Ach Input 7 23 Vref Reference Voltage 8 InA8 Ach Input 8 24 InB9 Bch Input 9 9 InA9 Ach Input 9 25 InB8 Bch Input 8 10 GND GND Terminal 26 InB7 Bch Input 7 11 OutA1 Ach Output 1 27 InB6 Bch Input 6 12 OutA2 Ach Output 2 28 InB5 Bch Input 5 13 OutA3 Ach Output 3 29 InB4 Bch Input 4 14 GND GND Terminal 30 InB3 Bch Input 3 15 SDA SDA Data Input (I2C BUS) 31 InB2 Bch Input 2 32 InB1 Bch Input 1 16 –2– SCL 2 SCL Clock Input (I C BUS) NJW1110 ! ABSOLUTE MAXIMUM RATING (Ta=25°C) PARAMETER SYMBOL Power Supply Voltage V + RATING UNIT 16 V Maximum input voltage VIM Power Dissipation PD NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting Operating Temperature Range Topr -40 to +85 °C Storage Temperature Range Tstg -40 to +125 °C (∗) 0 to V+ 800 (∗) V mW For the maximum input voltage less than V+. ! RECOMMENDED OPERATING CONDITIONS (Ta=25°C) PARAMETER Operating Voltage SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT - 7.5 9.0 15.0 V TEST CONDITION MIN. TYP. MAX. UNIT + V ! ELECTRICAL CHARACTERISTICS + ♦Power Supply (Ta=25°C, V =9V) PARAMETER Supply Current Reference Voltage SYMBOL ICC No Signal 4.0 8.0 12.0 MA VREF No Signal 4.0 4.5 5.0 V MAX. UNIT + ♦ AC CHARACTERISTICS (Ta=25°C, V =9V, VIN=0dBV (0dBV=1Vrms), f=1kHz, RL=47kΩ) PARAMETER SYMBOL Maximum Output Voltage VOM Voltage Gain 1 GV1 Voltage Gain 2 GV2 TEST CONDITION THD=1% VIN=200mVrms, Gain=6dB MIN. TYP. 6.0 8.0 (2.0) (2.5) -1.0 0 1.0 5.0 6.0 7.0 - dBV (Vrms) dB Total Harmonic Distortion 1 THD1 BW=400Hz-30kHz - 0.001 0.02 Total Harmonic Distortion 2 THD2 f=10kHz, BW=400Hz-30kHz - 0.003 - Total Harmonic Distortion 3 THD3 V =12V, BW=400Hz-30kHz - 0.0007 - -116 -106 dBV (1.6) (5.0) (µVrms) + Output Noise VNO Rg=0Ω, A-Weighted - Cross Talk 1 CT1 Rg=0Ω, A-Weighted - -110 - Cross Talk 2 CT2 Rg=0Ω, f=20kHz - -90 - Channel Separation 1 CS1 Rg=0Ω, A-Weighted - -110 - Channel Separation 2 CS2 Rg=0Ω, f=20kHz - -90 - % dB dB BW: Band Width + ♦Logic Control Characteristics (Ta=25°C, V =9V) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT + High Level Input Voltage VADRH ADR Terminal 2.5 - V Low Level Input Voltage VADRL ADR Terminal 0 - 1.5 V –3– NJW1110 2 !TIMING ON THE I C BUS (SDA,SCL) SDA tf tr tHD:STA tf tSU:DAT tSP tBUF tr SCL tHD:STA tSU:STA S tLOW tHD:DAT tSU:STO tHIGH Sr P S 2 !CHARACTERISTICS OF I/O STAGES FOR I C BUS (SDA,SCL) 2 I C BUS Load Conditions STANDARD MODE : FAST MODE : Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND) Pull up resistance 4kΩ (Connected to +5V), Load capacitance 50pF (Connected to GND) PARAMETER SYMBOL Standard mode Fast mode MIN. TYP. MAX. MIN. TYP. MAX. UNIT Low Level Input Voltage VIL 0.0 - 1.5 0.0 - 1.5 V High Level Input Voltage VIH 2.7 - 5.0 2.7 - 5.0 V Low level output voltage (3mA at SDA pin) VOL 0 - 0.4 0 - 0.4 V Ii -10 - 10 -10 - 10 µA Input current each I/O pin with an input voltage between 0.1VDD and 0.9VDDmax –4– NJW1110 2 !CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I C-BUS DEVICES PARAMETER SYMBOL Standard mode Fast mode UNIT MIN. TYP. MAX. MIN. TYP. MAX. fSCL - - 100 - - 400 kHz tHD:STA 4.0 - - 0.6 - - µs Low period of the SCL clock tLOW 4.7 - - 1.3 - - µs High period of the SCL clock tHIGH 4.0 - - 0.6 - - µs tSU:STA 4.7 - - 0.6 - - µs tHD:DAT 0 - - 0 - - µs tSU:DAT 250 - - 100 - - ns Rise time of both SDA and SCL signals tr - - 1000 - - 300 ns Fall time of both SDA and SCL signals tf - - 300 - - 300 ns tSU:STO 4.0 - - 0.6 - - µs Bus free time between a STOP and START condition tBUF 4.7 - - 1.3 - - µs Capacitive load for each bus line Cb - - 400 - - 400 pF Noise margin at the Low level VnL 0.5 - - 0.5 - - V Noise margin at the High level VnH 1 - - 1 - - V SCL clock frequency Hold time (repeated) START condition. Set-up time for a repeated START condition Data hold time NOTE) Data set-up time Set-up time for STOP condition Cb ; total capacitance of one bus line in pF. NOTE). Data hold time : tHD:DAT Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge. The SDA block in the NJW1110 does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not providing a hold time of at least 300nsec for the SDA in the master device. The time-consists of the data-delay-circuit of the SDA terminal are as follows. TLH ≈ RP*CD THL ≈ RD*CD (a) Low level ! High level : (b) High level ! Low level : In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward voltage (Vf) as much as possible. VDD RP RP SCL MASTER SBD SDA RD NJW1110 CD –5– NJW1110 2 ! DEFINITION OF I C REGISTER 2 ♦I C BUS FORMAT MSB LSB MSB LSB MSB LSB S Slave Address A Select Address A Data A P 1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit S: Starting Term A: Acknowledge Bit P: Ending Term ♦ SLAVE ADDRESS MSB 1 1 LSB 0 0 0 0 1 1 0 0 1 1 0 1 R/W R/W 94H(ADR=Low) 96H(ADR=High) R/W=0: Receive Only R/W=0: Write mode for register setting R/W=1: Not available ♦ CONTROL REGISTER TABLE The select address and sets each function. The auto increment function cycles the select address as follows. 00H→01H→02H→00H BIT Select Address D7 D6 D5 D4 D3 D2 D1 00H Variable Gain Buffer for OUT1 Input selector for OUT1 01H Variable Gain Buffer for OUT2 Input selector for OUT2 02H Variable Gain Buffer for OUT3 Input selector for OUT3 D0 ♦ CONTROL REGISTER DEFAULT VALUE Control register default value is all “0”. BIT Select Address D7 D6 D5 D4 D3 D2 D1 D0 00H 0 0 0 0 0 0 0 0 01H 0 0 0 0 0 0 0 0 02H 0 0 0 0 0 0 0 0 –6– NJW1110 ! INPUT SELECTOR " INPUT SELECTOR SETTING (OUT1:00H, OUT2:01H, OUT3:02H) Signal Select D3 D2 D1 D0 Mute 0 0 0 0 InA1/InB1 0 0 0 1 InA2/InB2 0 0 1 0 InA3/InB3 0 0 1 1 InA4/InB4 0 1 0 0 InA5/InB5 0 1 0 1 InA6/InB6 0 1 1 0 InA7/InB7 0 1 1 1 InA8/InB8 1 0 0 0 InA9/InB9 1 0 0 1 ! VARIABLE GAIN BUFFER " VARIABLE GAIN BUFFER SETTING (OUT1:00H, OUT2:01H, OUT3:02H) Gain (dB) D7 D6 D5 D4 0 0 0 0 0 3.0 0 0 0 1 3.5 0 0 1 0 4.0 0 0 1 1 4.5 0 1 0 0 5.0 0 1 0 1 5.5 0 1 1 0 6.0 0 1 1 1 6.5 1 0 0 0 7.0 1 0 0 1 7.5 1 0 1 0 8.0 1 0 1 1 –7– NJW1110 ! APPLICATION CIRCUIT InB1 InB2 InB3 InB5 InB4 InB6 InB7 InB8 InB9 OutB1 OutB2 OutB3 10µF 10 µF 10µF 10µF 10µF 10µF 10 µF 10µF 10µF 10µF 10 µF 10 µF 10µF + + + + + + + + + + + + + 32 31 30 29 28 27 26 22 21 25 24 23 ADR V+ + 100 µF 20 19 18 17 GND MUTE Gain Gain 8dB to 3dB / 0.5dBstep 50KΩX18 Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Vref Gain 8dB to 3dB / 0.5dBstep 8dB to 3dB / 0.5dBstep I2C Control Logic MUTE GND 1 10µF + InA1 –8– 2 10 µF + InA2 3 10µF + InA3 4 10µF + InA4 5 10µF + InA5 6 10µF + InA6 7 10 µF + InA7 8 10µF + InA8 9 10µF + InA9 GND 10 11 10 µF + OutA1 12 10 µF + OutA2 13 10µF 14 15 16 SDA SCL + OutA3 NJW1110 ! TYPICAL CHARACTERISTICS VREF vs Supply Voltage ICC vs Supply Voltage No signal, T=85,50,25,-20,-40oC 10 No signal 10 5 -40oC VREF[V] ICC [mA] 0 to 85oC 5 -20oC 0 0 5 10 15 0 20 0 Supply Voltage [V] V =9V, THD=1%, I/O: INA1-1Aout 50 C 20 V+=9V, THD=1%,I/O: INA1-1Aout,T=85,50,25,-20,-40oC + o 10 15 Supply Voltage [V] Maxim um Output Voltage vs Supply Voltage Maxim um Output Voltage vs Frequency 2.8 5 6.0 o 85 C Maximum Output Voltage [Vrms] Maximum Output Voltage [Vrms] 5.0 2.6 -40oC 2.4 -20oC 25oC 4.0 3.0 2.0 1.0 0.0 2.2 10 100 1000 10000 0 100000 5 10 15 20 Supply Voltage [+V] Frequency [Hz] Output Voltage vs Load Resistance Volum e Gain Output vs Volum e Setting V+=9V, f=1kHz, VOL=0dB, I/O: INA1-1Aout ,T=85,50,25,-20,-40oC V+=9V, Vin=1Vrms f=1kHz, I/O: INA1-1Aout, T=85,50,25,-20,-40oC 4 8 3 Volume Gain Output [dB] Maximum Output Voltage [Vrms] 7 85oC -40oC 2 -20oC 6 5 4 3 2 o 25 C 1 1 0 100 1000 RL[Ω] 10000 100000 0 1 2 3 4 5 Volume Setting [dB] 6 7 8 –9– NJW1110 ! TYPICAL CHARACTERISTICS Volum e Gain output vs Frequency THD+N vs Input Voltage V+=9V, Vin=1Vrms, V+=9V, BW:10-22kHz(f=100Hz), 400-30kHz(f=1kHz, 10kHz), I/O: INA1-1Aout, T=85,50,25,-20,-40oC 10 I/O: INA1-1Aout, T=85,50,25,-20,-40oC 10 VOL= 8dB 9 1 VOL= 6dB 7 6 VOL= 3dB 5 0.1 THD+N [%] Volume Gain Output [dB] 8 4 0.01 3 2 VOL= 0dB f=100Hz 0.001 1 f=1kHz 0 -1 10 100 1000 10000 Frequency [Hz] 100000 1000000 0.0001 0.01 THD+N vs Input Voltage f=10kHz 0.1 1 Input Voltage [Vrms] 10 THD+N vs Frequency V+=9V, f=1kHz, BW:400-30kHz, I/O: INA1-1Aout V+=9V, f=1kHz, BW:10-80kHz, Vin=1Vrms I/O: INA1-1Aout, T=85,50,25,-20,-40oC T=85,50,25,-20,-40℃ 10 10 VOL= 8dB 1 VOL= 6dB VOL= 3dB 0.1 THD+N [%] THD+N [%] 1 VOL=0dB 0.01 0.001 0.1 0.01 0.001 0.0001 0.01 0.1 1 Input Voltage [Vrms] 10 0.0001 10 Cross Talk vs Frequency 100 I/O: INB1-1Aout, T=25oC I/O: INA13456789-1Aout,Select channel:INA2, T=25 C -40 -40 Rg=5.1kΩ Rg=5.1kΩ Rg=3.3kΩ -60 -80 Channel Separation[dB] Cross Talk[dB] 100000 V+=9V, Vin=1Vrms, VOL=0dB, BW:10-80kHz, o Rg=620Ω -100 Rg=0Ω -120 Rg=3.3kΩ Rg=620Ω -80 Rg=0Ω -100 -120 10 100 1000 Frequency [Hz] – 10 – 10000 Channel Separation vs Frequency V+=9V, Vin=1Vrms, VOL=0dB, BW:10-80kHz, -60 1000 Frequency [Hz] 10000 100000 10 100 1000 Frequency [Hz] 10000 100000 NJW1110 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. – 11 –