TI SN74GTLPH16945

SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
D
D
D
D
D
D
D
D
D
D
D
D
DGG OR DGV PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
LVTTL Outputs (–24 mA/24 mA)
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
Bus Hold on A-Port Data Inputs
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1DIR
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2DIR
description
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
1OE
1B1
1B2
GND
1B3
1B4
BIAS VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VREF
2B5
2B6
GND
2B7
2B8
2OE
25
The SN74GTLPH16945 is a medium-drive, 16-bit
bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It is
partitioned as two 8-bit transceivers. The device
provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times
faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP’s reduced output swing
(<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 19 Ω.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH16945 is given only at the preferred higher noise margin GTLP, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V
and VREF = 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
description (continued)
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
A
1DIR
NC
NC
NC
NC
1OE
B
B
1A2
1A1
GND
GND
1B1
1B2
C
C
1A4
1A3
1B3
1B4
D
1A6
1A5
VCC
GND
BIAS VCC
D
GND
1B5
1B6
E
2A8
1A7
1B7
1B8
F
2A1
2A2
2B2
2B1
G
2A3
2A4
GND
GND
2B4
2B3
H
2A5
2A6
2A8
VREF
GND
2B5
2A7
VCC
GND
2B6
J
2B8
2B7
K
2DIR
NC
NC
NC
NC
2OE
E
F
G
H
J
K
NC – No internal connection
ORDERING INFORMATION
TA
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74GTLPH16945GR
GTLPH16945
TVSOP – DGV
Tape and reel
SN74GTLPH16945VR
GL945
VFBGA – GQL
Tape and reel
SN74GTLPH16945KR
GL945
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
2
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SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
functional description
The SN74GTLPH16945 is a medium-drive (50 mA), 16-bit bus transceiver partitioned as two 8-bit segments
and is designed for asynchronous communication between data buses. The device transmits data from the
A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR)
input. OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting.
For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When
OE is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to that of A to B, except OE and DIR are low.
FUNCTION TABLE
INPUTS
OUTPUT
MODE
X
Z
Isolation
L
B data to A port
H
A data to B port
OE
DIR
H
L
L
True transparent
logic diagram (positive logic)
1DIR
1
48
1A1
47
2
31
1OE
1B1
VREF
To Seven Other Channels
2DIR
24
25
2A1
36
13
2OE
2B1
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
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3
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1): A port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Current into any A port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4
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SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
recommended operating conditions (see Notes 4 through 7)
VCC,
BIAS VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IIK
IOH
Input clamp current
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
NOM
MAX
UNIT
3.15
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
VCC
VTT
5.5
B port
Except B port
B port
Except B port
VREF+0.05
2
B port
V
V
V
V
VREF–0.05
0.8
V
–18
mA
A port
–24
mA
A port
24
B port
50
Except B port
High-level output current
IOL
MIN
Outputs enabled
10
–40
ns/V
µs/V
20
Operating free-air temperature
mA
85
°C
NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable, but generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
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5
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER
VIK
VOH
A port
TEST CONDITIONS
VCC = 3.15 V,
VCC = 3.15 V to 3.45 V,
II = –18 mA
IOH = –100 µA
VCC = 3
3.15
15 V
IOH = –12 mA
IOH = –24 mA
VOL
B port
II
Control inputs
A port
IOZH‡
B port
TYP†
MAX
UNIT
–1.2
V
VCC–0.2
2.4
V
2
IOL = 100 µA
IOL = 12 mA
0.2
0.5
VCC = 3.15 V to 3.45 V,
IOL = 24 mA
IOL = 100 µA
0.2
VCC = 3.15 V
IOL = 10 mA
IOL = 40 mA
IOL = 50 mA
0.55
VI = 0 or 5.5 V
±10
VCC = 3.15 V to 3.45 V,
A port
MIN
VCC = 3
3.15
15 V
VCC = 3.45 V,
VCC = 3
3.45
45 V
0.4
0.2
0.4
VO = VCC
10
VO = 1.5 V
10
–10
IOZL‡
IBHL§
A and B ports
VCC = 3.45 V,
VO = GND
A port
IBHH¶
IBHLO#
IBHHO||
A port
VCC = 3.15 V,
VCC = 3.15 V,
VI = 0.8 V
VI = 2 V
VCC = 3.45 V,
VCC = 3.45 V,
VI = 0 to VCC
VI = 0 to VCC
VCC = 3.45 V, IO = 0,
VI (A-port or control input) = VCC or GND,
VI (B port) = VTT or GND
Outputs high
50
Outputs low
50
Outputs disabled
50
ICC
A port
A port
A or B port
Ci
Ciio
Control inputs
µA
µA
µA
75
µA
–75
µA
500
µA
µA
–500
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
∆ICCk
V
mA
1.5
mA
pF
4.5
5
A port
VI = 3.15 V or 0
VO = 3.15 V or 0
7.5
9
B port
VO = 1.5 V or 0
7.5
9
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For I/O ports, the parameters IOZH and IOZL include the input leakage current.
§ The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and
then raising it to VILmax.
¶ The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and
then lowering it to VIHmin.
# An external driver must source at least IBHLO to switch this node from low to high.
|| An external driver must sink at least IBHHO to switch this node from high to low.
k This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
6
TEST CONDITIONS
MIN
MAX
UNIT
10
µA
VO = 0.5 V to 3 V,
VI or VO = 0 to 5.5 V
OE = 0
±30
µA
VO = 0.5 V to 3 V,
OE = 0
±30
µA
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
BIAS VCC = 0,
IOZPD
VCC = 1.5 V to 0,
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SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
BIAS VCC = 0,
±30
µA
BIAS VCC = 0,
VO = 0.5 V to 1.5 V, OE = 0
±30
µA
BIAS VCC = 3
3.15
15 V to 3
3.45
45 V
V,
VO (B port) = 0 to 1.5
15V
BIAS VCC = 3.3 V,
IO = 0
VO (B port) = 0.6 V
IOZPD
VCC = 1.5 V to 0,
VCC = 0 to 3.15 V
VO
IO
VCC = 0,
UNIT
µA
BIAS VCC = 0,
VCC = 3.15 V to 3.45 V
VCC = 0,
MAX
10
VCC = 0,
VCC = 0 to 1.5 V,
ICC (BIAS VCC)
MIN
VI or VO = 0 to 1.5 V
VO = 0.5 V to 1.5 V, OE = 0
Ioff
IOZPU
BIAS VCC = 3.15 V to 3.45 V,
0.95
5
mA
10
µA
1.05
V
µA
–1
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
OE
B
ten
tdis
tr
tf
tPLH
tPHL
ten
tdis
MIN
TYP†
MAX
2.1
6.3
2.1
6.3
2
6.9
2
6.9
UNIT
ns
ns
Rise time, B outputs (20% to 80%)
2.5
ns
Fall time, B outputs (80% to 20%)
2.1
ns
B
A
OE
A
2.1
5.3
2.1
5.3
0.3
5.7
0.3
5.7
ns
ns
† All typical values are at VCC = 3.3 V, TA = 25°C.
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SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
25 Ω
From Output
Under Test
CL = 30 pF
(see Note A)
S1
Open
6V
GND
LOAD CIRCUIT FOR A OUTPUTS
Test
Point
LOAD CIRCUIT FOR B OUTPUTS
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
1V
Output
1V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
1V
0V
tPLH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
1.5 V
tPZL
1.5 V
1V
Input
3V
Output
Control
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
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SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
38 Ω
.25”
ZO = 70 Ω
2”
Conn.
1”
Conn.
Conn.
1”
1”
2”
38 Ω
1.5 V
1.5 V
.25”
1.5 V
19 Ω
Conn.
From Output
Under Test
1”
LL = 19 nH
Test
Point
CL = 9 pF
Rcvr
Rcvr
Rcvr
Slot 2
Slot 9
Slot 10
Drvr
Slot 1
Figure 2. Medium-Drive Test Backplane
Figure 3. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
OE
B
ten
tdis
tr
tf
TYP†
4.3
4.3
5
4.4
UNIT
ns
ns
Rise time, B outputs (20% to 80%)
1
ns
Fall time, B outputs (80% to 20%)
2
ns
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
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9
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74GTLPH16945GR
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74GTLPH16945VR
ACTIVE
TVSOP
DGV
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
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for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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