TI TMS470R1A288

TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
FEATURES
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High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI™)
– 24-MHz System Clock (48-MHz Pipeline)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
Integrated Memory
– 288K-Byte Program Flash
• Two Banks With 8 Contiguous Sectors
– 16K-Byte Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
Operating Features
– Low-Power Modes: STANDBY and HALT
– Industrial Temperature Range
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– Interrupt Expansion Module (IEM)
– System Integrity and Failure Detection
– ICE Breaker
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-8 Internal ZPLL Option
– ZPLL Bypass Mode
Ten Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
• 255 Programmable Baud Rates
– Two Serial Communication Interfaces (SCIs)
• 224 Selectable Baud Rates
• Asynchronous/Isosynchronous Modes
– Class II Serial Interface B (C2SIb)
• Normal 10.4 Kbps and 4X Mode 41.6 Kbps
– Two Standard CAN Controllers (SCC)
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(1)
• 16-Mailbox Capacity
• Fully Compliant With CAN Protocol,
Version 2.0B
– Three Inter-Integrated Circuit (I2C) Modules
• Multi-Master and Slave Interfaces
• Up to 400 Kbps (Fast Mode)
• 7- and 10-Bit Address Capability
High-End Timer Lite (HET)
– 12 Programmable I/O Channels:
• 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
• 64-Instruction Capacity
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
12-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 µs Minimum Sample/Conversion Time
– Calibration Mode and Self-Test Features
Flexible Interrupt Handling
Expansion Bus Module (EBM) (PGE only)
– Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
– 42 I/O Expansion Bus Pins
50 Dedicated General-Purpose I/O (GIO) Pins
and 43 Additional Peripheral I/Os (PGE)
14 Dedicated General-Purpose I/O (GIO) Pins
and 43 Additional Peripheral I/Os (PZ)
16 External Interrupts
On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1(1) (JTAG) Test-Access Port
144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
100-Pin Plastic Low-Profile Quad Flatpack (PZ
Suffix)
The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
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ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
GIOF[7]
GIOF[6]
GIOA[5]/INT[5]
PLLDIS
GIOF[5]
I2C2SCL
I2C2SDA
GIOF[4]
VCC
VSS
GIOF[3]
GIOF[2]
I2C1SCL
I2C1SDA
VCCIO
VSSIO
CAN1STX
CAN1SRX
GIOF[1]
CLKOUT
GIOF[0]
GIOA[7]/INT[7]
GIOA[6]/INT[6]
GIOE[7]
TCK
TDO
TDI
HET[0]
TMS470R1A288 144-Pin PGE Package (Top View) (without Expansion Bus)
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SPI1SCS
SPI1ENA
GIOG[4]
SPI1CLK
SPI1SIMO
GIOG[3]
SPI1SOMI
GIOG[2]
HET[6]
GIOG[1]
HET[7]
HET[8]
VCC
VSS
HET[18]
TMS2
TMS
HET[20]
HET[22]
GIOG[0]
C2SILPN
C2SIRX
GIOD[5]
C2SITX
VCCIO
VSSIO
GIOD[4]
I2C3SCL
I2C3SDA
GIOD[3]
VCC
OSCOUT
OSCIN
VSS
GIOD[2]
AWD
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ADREFHI
ADREFLO
VCCAD
VSSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
GIOC[4]
GIOC[3]
RST
VSS
VCC
TEST
GIOH[5]/INT[13]
GIOC[2]
GIOA[4]/INT[4]
GIOC[1]
VSS
VCC
VCCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
GIOC[0]
GIOA[1]/INT[1]/ECLK
VCCIO
VSSIO
GIOH[0]/INT[8]
GIOG[7]
GIOA[0]/INT[0]
GIOG[6]
GIOG[5]
TRST
2
HET[1]
HET[2]
GIOE[6]
VCCIO
VSSIO
GIOE[5]
HET[3]
HET[4]
GIOE[4]
HET[5]
SPI2SCS
GIOE[3]
SPI2ENA
SPI2SIMO
GIOE[2]
SPI2SOMI
SPI2CLK
CAN2STX
CAN2SRX
VCC
VSS
SCI2CLK
SCI2RX
SCI2TX
SCI1CLK
GIOE[1]
SCI1RX
SCI1TX
GIOE[0]
GIOB[0]
GIOD[0]
GIOH[1]/INT[9]
GIOH[2]/INT10]
GIOD[1]
GIOH[3]/INT[11]
GIOH[4]/INT[12]
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
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ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
EBADDR[13]EBDATA[15]
EBADDR[12]EBDATA[14]
GIOA[5]/INT[5]
PLLDIS
EBADDR[11]EBDATA[13]
I2C2SCL
I2C2SDA
EBADDR[10]EBDATA[12]
VCC
VSS
EBADDR[9]EBDATA[11]
EBADDR[8]EBDATA[10]
I2C1SCL
I2C1SDA
VCCIO
VSSIO
CAN1STX
CAN1SRX
EBADDR[7]EBDATA[9]
CLKOUT
EBADDR[6]EBDATA[8]
GIOA[7]/INT[7]
GIOA[6]/INT[6]
EBDATA[7]
TCK
TDO
TDI
HET[0]
TMS470R1A288 144-Pin PGE Package (Top View) (with Expansion Bus)
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HET[1]
HET[2]
EBDATA[6]
VCCIO
VSSIO
EBDATA[5]
HET[3]
HET[4]
EBDATA[4]
HET[5]
SPI2SCS
EBDATA[3]
SPI2ENA
SPI2SIMO
EBDATA[2]
SPI2SOMI
SPI2CLK
CAN2HTX
CAN2HRX
VCC
VSS
SCI2CLK
SCI2RX
SCI2TX
SCI1CLK
EBDATA[1]
SCI1RX
SCI1TX
EBDATA[0]
EBDMAREQ[0]
EBADDR[0]
EBADDR[23]/EBADDR[15]
EBADDR[24]/EBADDR[16]
GIOD[1]
EBADDR[26]/EBADDR[18]
EBADDR[25]/EBADDR[17]
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SPI1SCS
SPI1ENA
EBADDR[18]/EBADDR[10]
SPI1CLK
SPI1SIMO
EBADDR[17]/EBADDR[9]
SPI1SOMI
EBADDR[16]/EBADDR[8]
HET[6]
EBADDR[15]/EBADDR[7]
HET[7]
HET[8]
VCC
VSS
HET[18]
TMS2
TMS
HET[20]
HET[22]
EBADDR[14]/EBADDR[6]
C2SILPN
C2SIRX
EBADDR[5]
C2SITX
VCCIO
VSSIO
EBADDR[4]
I2C3SCL
I2C3SDA
EBADDR[3]
VCC
OSCOUT
OSCIN
VSS
EBADDR[2]
AWD
ADREFHI
ADREFLO
VCCAD
VSSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
EBCS[6]
EBCS[5]
RST
VSS
VCC
TEST
EBHOLD
EBWR[1]
GIOA[4]/INT[4]
EBWR[0]
VSS
VCC
VCCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
BOE
GIOA[1]/INT[1]/ECLK
VCCIO
VSSIO
EBADDR[22]/EBADDR[14]
EBADDR[21]/EBADDR[13]
GIOA[0]/INT[0]
EBADDR[20]/EBADDR[12]
EBADDR[19]/EBADDR[11]
TRST
3
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
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ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
GIOA[5]/INT[5]
PLLDIS
I2C2SCL
I2C2SDA
VCC
VSS
I2C1SCL
I2C1SDA
CAN1STX
CAN1SRX
CLKOUT
GIOA[7]/INT[7]
GIOA[6]/INT[6]
TCK
TDO
TDI
HET[0]
TMS470R1A288 100-Pin PZ Package (Top View)
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SPI1SCS
SPI1ENA
SPI1CLK
SPI1SIMO
SPI1SOMI
HET[6]
HET[7]
HET[8]
HET[18]
TMS2
TMS
HET[20]
HET[22]
C2SILPN
C2SIRX
C2SITX
VCCIO
VSSIO
I2CSCL
I2C3SDA
VCC
OSCOUT
OSCIN
VSS
AWD
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ADREFHI
ADREFLO
VCCAD
VSSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
RST
TEST
GIOH[5]/INT[13]
GIOA[4]/INT[4]
VSS
VCC
VCCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
GIOA[1]/INT[1]/ECLK
VCCIO
VSSIO
GIOA[0]/INT[0]
TRST
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HET[1]
HET[2]
VCCIO
VSSIO
HET[3]
HET[4]
HET[5]
SPI2SCS
SPI2ENA
SPI2SIMO
SPI2SOMI
SPI2CLK
CAN2STX
CAN2SRX
SCI2CLK
SCI2RX
SCI2TX
SCI1CLK
SCI1RX
SCI1TX
GIOB[0]
GIOH[1]/INT[9]
GIOH[2]/INT[10]
GIOH[3]/INT[11]
GIOH[4]/INT[12]
www.ti.com
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
SPNS106 – SEPTEMBER 2005
DESCRIPTION
The TMS470R1A288 (1) devices are members of the Texas Instruments TMS470R1x family of general-purpose
16/32-bit reduced instruction set computer (RISC) microcontrollers. The A288 microcontroller offers high
performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a
high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views
memory as a linear collection of bytes numbered upwards from zero. The A288 utilizes the big-endian format
where the most significant byte of a word is stored at the lowest-numbered byte and the least significant byte at
the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining low
costs. The A288 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The A288 devices contain the following:
• ARM7TDMI 16/32-Bit RISC CPU
• TMS470R1x system module (SYS) with 470+ enhancements
• 288K-byte flash
• 16K-byte SRAM
• Zero-pin phase-locked loop (ZPLL) clock module
• Digital watchdog (DWD) timer
• Analog watchdog (AWD) timer
• Enhanced real-time interrupt (RTI) module
• Interrupt expansion module (IEM)
• Memory security module (MSM)
• JTAG security module (JSM)
• Two serial peripheral interface (SPI) modules
• Two serial communications interface (SCI) modules
• Two standard CAN controllers (SCC)
• Three inter-integrated circuit (I2C) modules
• Class II serial interface B (C2SIb) module
• 10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
• High-end timer lite (HET) controlling 12 I/Os
• External clock prescale (ECP)
• Expansion bus module (EBM)
• Up to 93 I/O pins (PGE only), up to 57 I/O (PZ only)
The functions performed by the 470+ system module (SYS) include:
• Address decoding
• Memory protection
• Memory and peripherals bus supervision
• Reset and abort exception management
• Prioritization for all internal interrupt sources
• Device clock control
• Parallel signature analysis (PSA)
The enhanced real-time interrupt (RTI) module on the A288 has the option to be driven by the oscillator clock.
The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the
watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral
select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the
SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).
The A288 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
(1)
Throughout the remainder of this document, the TMS470R1A288 will be referred to as either the full device name or as A288.
5
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface. When in pipeline mode, the flash operates with a system clock frequency of
up to 48 MHz. The flash operates with a system clock frequency of up to 24 MHz. For more detailed information
on the flash, see the Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature
number SPNU213).
The memory security module (MSM) and JTAG security module (JSM) prevent unauthorized access and visibility
to on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code. For more
information, see the TMS470R1x Memory Security Module Reference Guide (literature number SPNU246) and
the TMS470R1x JTAG Security Module Reference Guide (literature number SPNU245).
The A288 device has ten communication interfaces: two SPIs, two SCIs, two SCCs, a C2SI, and three I2Cs. The
SPI provides a convenient method of serial interaction for high-speed communications between similar
shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication
between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a
serial, multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy
and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring.
The C2SIb allows the A288 to transmit and receive messages on a class II network following an SAE J1850 (2)
standard. The I2C module is a multi-master communication module providing an interface between the A288
microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports both 100 Kbps and 400
Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the specific
reference guides (literature numbers SPNU195, SPNU196, and SPNU197). For more detailed functional
information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number
SPNU223). For more detailed functional information on the C2SI, see the TMS470R1x Class II Serial Interface B
(C2SIb) Reference Guide (literature number SPNU214).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For
more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide
(literature number SPNU199).
The A288HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
The A288 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be
converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which can be triggered by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A288 device modules. For more
detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide (literature number SPNU212).
NOTE:
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.
(2)
6
SAE Standard J1850 Class B Data Communication Network Interface
www.ti.com
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
SPNS106 – SEPTEMBER 2005
The expansion bus module (EBM) is a standalone module that supports the multiplexing of the GIO functions
and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module
(EBM) Reference Guide (literature number SPNU222).
The A288 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
7
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Device Characteristics
The A288 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1 identifies all the
characteristics of the A288 device except the SYSTEM and CPU, which are generic.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1A288
COMMENTS
MEMORY
For the number of memory selects on this device, see Table 3, TMS470R1A288 Memory Selection Assignment.
INTERNAL MEMORY
Pipeline/Non-Pipeline
288K-Byte Flash
16K-Byte SRAM
Memory Security Module (MSM)
JTAG Security Module (JSM)
Flash is pipeline-capable.
The A288 RAM is implemented in one 16K-byte array selected by
two memory-select signals (see Table 3, TMS470R1A288 Memory
Selection Assignment).
PERIPHERALS
For the device-specific interrupt priority configurations, see Table 6, Interrupt Priority (IEM and CIM). For the 1K-byte peripheral address
ranges and their peripheral selects, see Table 4, A288 Peripherals, System Module, and Flash Base Addresses.
CLOCK
ZPLL
Zero-pin phase-locked loop has no external loop filter pins.
EXPANSION BUS
EBM
Expansion bus module with 42 pins. Supports 8- and 16-bit
memories. See Table 7 for details.
GENERAL-PURPOSE I/Os
50 I/O (PGE Suffix)
14 I/O (PZ Suffix)
ECP
YES
SCI
2 (3-pin)
CAN (HECC and/or SCC)
2 SCC
SPI (5-pin, 4-pin or 3-pin)
2 (5-pin)
C2SIb
1
I2C
3
HET with XOR SHARE
HET RAM
MibADC
12 I/O
Two standard CAN controllers
The high-resolution (HR) SHARE feature allows even-numbered HR
pins to share the next higher odd HR pin structures. This HR sharing
is independent of whether or not the odd pin is available externally. If
an odd pin is available externally and shared, then the odd pin can
only be used as a general-purpose I/O. For more information on HR
SHARE, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
64-Instruction Capacity
10-bit, 12-channel
64-word FIFO
CORE VOLTAGE
1.8 V
I/O VOLTAGE
3.3 V
PINS
144
100
PACKAGES
PGE
PZ
8
In the PGE package, Port A has 8 external pins, Port B has only 1
external pin, Port C has 5 external pins, Port D has 6 external pins,
Ports E, F, and G each have 8 external pins, and Port H has 6
external pins.
In the PZ package, Port A has 8 external pins, Port B has only 1
external pin, and Port H has 5 external pins.
Both the logic and registers for a full 16-channel MibADC are
present.
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Functional Block Diagram
External
Pins
FLASH
(288K Byte)
2 Banks
8 Sectors
VCCP
FLTP2
OSCIN
Memory
Security
Module
(MSM)
RAM
(16K Bytes)
ZPLL
OSCOUT
Crystal
External
Pins
PLLDIS
ADIN[11:0]
CPU Address Data Bus
MibADC
64−Word
FIFO
TRST
ADEVT
ADREFHI
ADREFLO
VCCAD
TCK
TMS470R1x CPU
VSSAD
TDI
TDO
HET
64 Words
Expansion Address/Data Bus
ICE Breaker
TMS
TMS2
RST
TMS470R1x System Module
with Enhanced RTI Module(A)
AWD
TEST
PORRST
CLKOUT
DMA Controller
16 Channels
Digital
Watchdog
(DWD)
Interrupt Expansion
Module (IEM)
Analog
Watchdog
(AWD)
SCC1
SCC2
HET[0:8;18,30,22]
CAN1TX
CAN1RX
CAN2TX
CAN2RX
SCI1CLK
SCI1
SCI1TX
SCI1RX
SCI2CLK
SCI2
SCI2TX
SCI2RX
HECC
I2C3
I2C2
C2SI
SPI2
SPI1
GIO/EBM(A)
ECP
I2C3SCL
I2C2SDA
I2C2SCL
I2C1SDA
I2C1SCL
GIOH[5,0]/INT[13:8](A)
GIOF[7:0] (A)
GIOG[7:0] (A)
GIOE[7:0](A)
GIOD[5:0] (A)
GIOB[0]
GIOC[4:0] (A)
GIOA[0]/INT[0]
GIOA[7:2]/INT[7:2]
GIOA[1]/INT[1]/ECLK
SPI1CLK
SPI1SOMI
SPI1SIMO
SPI1SCS
SPI1ENA
SPI2CLK
SPI2SOMI
SPI2SIMO
SPI2SCS
SPI2ENA
C2SILPN
C2SITX
C2SIRX
I2C1
I2C3SDA
A.
The enhanced RTI module is the system module with two extra bits to disable the ZPLL while in STANDBY mode.
B.
GIOC[4:0], GIOD[5:0], GIOE[5:0], GIOF[7:0], and GIOH[0], which are muxed with EBM, are not available on the PZ
package. See Table 7 for EBM-to-GIO mapping.
9
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Table 2. Terminal Functions
TERMINAL
NAME
PZ
PGE
HET[0]
51
73
HET[1]
50
72
HET[2]
49
71
HET[3]
46
66
HET[4]
45
65
HET[5]
44
63
HET[6]
6
9
HET[7]
7
11
HET[8]
8
12
HET[18]
9
15
HET[20]
12
18
HET[22]
13
19
CAN1SRX
58
83
CAN1STX
59
CAN2SRX
37
CAN2STX
38
INPUT
VOLTAGE (1) (2)
OUTPUT
CURRENT (3)
INTERNAL
PULLUP/
PULLDOWN
DESCRIPTION
HIGH-END TIMER (HET)
3.3-V
Timer input capture or output compare. The
HET[8:0,18,20,22] applicable pins can be programmed as general-purpose input/output (GIO)
pins. All are high-resolution pins.
The high-resolution (HR) SHARE feature allows
even HR pins to share the next higher odd HR
pin structures. This HR sharing is independent of
whether or not the odd pin is available externally.
If an odd pin is available externally and shared,
then the odd pin can only be used as a general-purpose I/O. For more information on HR
SHARE, see the TMS470R1x High-End Timer
(HET) Reference Guide (literature number
SPNU199).
2 mA -z
STANDARD CAN CONTROLLER (SCC)
5 V tolerant
4 mA
SCC1 receive pin or GIO pin
84
3.3-V
2 mA -z
SCC1 transmit pin or GIO pin
54
5 V tolerant
4 mA
SCC2 receive pin or GIO pin
55
3.3-V
2 mA -z
SCC 2 transmit pin or GIO pin
CLASS II SERIAL INTERFACE (C2SIB)
C2SILPN
14
21
3.3-V
2 mA -z
C2SIRX
15
22
5 V tolerant
4 mA
C2SITX
16
24
3.3-V
2 mA -z
GIOA[0]/INT[0]
99
141
GIOA[1]/INT[1]/ECLK
96
136
GIOA[2]/INT[2]
95
134
GIOA[3]/INT[3]
94
133
GIOA[4]/INT[4]
89
127
GIOA[5]/INT[5]
67
98
GIOA[6]/INT[6]
55
78
GIOA[7]/INT[7]
56
79
GIOB[0]/DMAREQ[0]
C2SIb module loopback enable pin or GIO pin
C2SIb module receive data input pin or GIO pin
C2SIb module transmit data output pin or GIO
pin
GENERAL-PURPOSE I/O (GIO)
30
43
GIOC[0]/EBOE
-
135
GIOC[1]/EBWR[0]
-
128
GIOC[2]/EBWR[1]
-
126
GIOC[3]/EBCS[5]
-
120
GIOC[4]/EBCS[6]
-
119
(1)
(2)
(3)
10
5 V tolerant
3.3-V
General-purpose input/output pins.
GIOA[7:0]/INT[7:0] are interrupt-capable pins.
GIOA[1]/INT[1]/ECLK pin is multiplexed with the
external clock-out function of the external clock
prescale (ECP) module.
4 mA
2 mA -z
IPD (20 µA)
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:],
GIOF[7:0], GIOG[7:0], and GIOH[5:0] are
multiplexed with the expansion bus module.
See Table 7.
PWR = power, GND = ground, REF = reference voltage, NC = no connect
All I/O pins, except RST , are configured as inputs while PORRST is low and immediately after PORRST goes high.
IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Table 2. Terminal Functions (continued)
TERMINAL
NAME
PZ
PGE
INPUT
VOLTAGE (1) (2)
OUTPUT
CURRENT (3)
INTERNAL
PULLUP/
PULLDOWN
DESCRIPTION
GENERAL-PURPOSE I/O (GIO) (CONTINUED)
GIOD[0]/EBADDR[0]
-
42
GIOD[1]/EBADDR[1]
-
39
GIOD[2]/EBADDR[2]
-
35
GIOD[3]/EBADDR[3]
-
30
GIOD[4]/EBADDR[4]
-
27
GIOD[5]/EBADDR[5]
-
23
GIOE[0]/EBDATA[0]
-
44
GIOE[1]/EBDATA[1]
-
47
GIOE[2]/EBDATA[2]
-
58
GIOE[3]/EBDATA[3]
-
61
GIOE[4]/EBDATA[4]
-
64
GIOE[5]/EBDATA[5]
-
67
GIOE[6]/EBDATA[6]
-
70
GIOE[7]/EBDATA[7]
-
77
GIOF[0]/EBADDR[6]/
EBDATA[8]
-
80
GIOF[1]/EBADDR[7]/
EBDATA[9]
-
82
GIOF[2]/EBADDR[8]/
EBDATA[10]
-
89
GIOF[3]/EBADDR[9]/
EBDATA[11]
-
90
GIOF[4]/EBADDR[10]/
EBDATA[12]
-
93
GIOF[5]/EBADDR[11]/
EBDATA[13]
-
96
GIOF[6]/EBADDR[12]/
EBDATA[14]
-
99
GIOF[7]/EBADDR[13]/
EBDATA[15]
-
100
GIOG[0]/EBADDR[14]
/EBADDR[6]
-
20
GIOG[1]/EBADDR[15]
/EBADDR[7]
-
10
GIOG[2]/EBADDR[16]
/EBADDR[8]
-
8
GIOG[3]/EBADDR[17]
/EBADDR[9]
-
6
3.3-V
2 mA -z
IPD (20 µA)
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:],
GIOF[7:0], GIOG[7:0], AND GIOH[5:0] are
multiplexed with the expansion bus module.
See Table 7.
11
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Table 2. Terminal Functions (continued)
TERMINAL
NAME
PZ
PGE
INPUT
VOLTAGE (1) (2)
OUTPUT
CURRENT (3)
INTERNAL
PULLUP/
PULLDOWN
DESCRIPTION
GENERAL-PURPOSE I/O (GIO) (CONTINUED)
GIOG[4]/EBADDR[18]
/EBADDR[10]
-
3
GIOG[5]/EBADDR[19]
/EBADDR[11]
-
143
GIOG[6]/EBADDR[20]
/EBADDR[12]
-
142
GIOG[7]/EBADDR[21]
/EBADDR[13]
-
140
GIOH[0]/EBADDR[22]
/EBADDR[14]/INT[8]
-
139
GIOH[1]/EBADDR[23]
/EBADDR[15]/INT[9]
29
41
GIOH[2]/EBADDR[24]
/EBADDR[16]/INT[10]
28
40
GIOH[3]/EBADDR[25]
/EBADDR[17]/INT[11]
27
38
GIOH[4]/EBADDR[26]
/EBADDR[18]/INT[12]
26
37
GIOH[5]/EBHOLD/
INT[13]
88
125
2 mA -z
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:],
GIOF[7:0], GIOG[7:0], AND GIOH[5:0] are
multiplexed with the expansion bus module.
See Table 7.
GIOH[5:0]/INT[13:8] are interrupt-capable pins.
3.3-V
IPD (20 µA)
2 mA
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
68
101
ADIN[0]
84
117
ADIN[1]
83
116
ADIN[2]
82
115
ADIN[3]
81
114
ADIN[4]
80
113
ADIN[5]
75
108
ADIN[6]
74
107
ADIN[7]
73
106
ADIN[8]
72
105
ADIN[9]
71
104
ADIN[10]
70
103
ADIN[11]
69
102
ADREFHI
76
109
3.3-V REF
MibADC module high-voltage reference input
ADREFLO
77
110
GND REF
MibADC module low-voltage reference input
VCCAD
78
111
3.3-V PWR
MibADC analog supply voltage
VSSAD
79
112
GND
12
3.3-V
3.3-V
2 mA -z
MibADC event input. Can be programmed as a
GIO pin.
ADEVT
MibADC analog input pins
MibADC analog ground reference
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Table 2. Terminal Functions (continued)
TERMINAL
NAME
PZ
PGE
INPUT
VOLTAGE (1) (2)
OUTPUT
CURRENT (3)
INTERNAL
PULLUP/
PULLDOWN
DESCRIPTION
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
3
4
SPI1 clock. SPI1CLK can be programmed as a
GIO pin.
SPI1ENA
2
2
SPI1 chip enable. Can be programmed as a GIO
pin.
SPI1SCS
1
1
SPI1SIMO
4
5
SPI1 data stream. Slave in/master out. Can be
programmed as a GIO pin.
SPI1SOMI
5
7
SPI1 data stream. Slave out/master in. Can be
programmed as a GIO pin.
5 V tolerant
SPI1 slave chip select. Can be programmed as a
GIO pin.
4 mA
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2CLK
39
56
SPI2 clock. Can be programmed as a GIO pin.
SPI2ENA
42
60
SPI2 chip enable. Can be programmed as a GIO
pin.
SPI2SCS
43
62
SPI2SIMO
41
59
SPI2 data stream. Slave in/master out. Can be
programmed as a GIO pin.
SPI2SOMI
40
57
SPI2 data stream. Slave out/master in. Can be
programmed as a GIO pin.
I2C1SDA
60
87
I2C1 serial data pin or GIO pin
I2C1SCL
61
88
I2C1 serial clock pin or GIO pin
I2C2SDA
64
94
I2C2SCL
65
95
I2C3SDA
20
29
I2C3SCL
19
28
5 V tolerant
SPI2 slave chip select. Can be programmed as a
GIO pin.
4 mA
INTER-INTEGRATED CIRCUIT (I2C)
5 V tolerant
I2C2 serial data pin or GIO pin
4 mA
I2C2 serial clock pin or GIO pin
I2C3 serial data pin or GIO pin
I2C3 serial clock pin or GIO pin
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
OSCIN
23
33
OSCOUT
22
32
PLLDIS
66
97
1.8-V
Crystal connection pin or external clock input
2 mA
3.3-V
External crystal connection pin
IPD (20 µA)
Enable/disable the ZPLL. The ZPLL can be
bypassed and the oscillator becomes the system
clock. If not in bypass mode, TI recommends
that this pin be connected to ground or pulled
down to ground by an external resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SCI1CLK
33
48
3.3-V
2 mA -z
SCI1 clock. SCI1CLK can be programmed as a
GIO pin.
SCI1RX
32
46
5 V tolerant
4 mA
SCI1 data receive. SCI1RX can be programmed
as a GIO pin.
SCI1TX
31
45
3.3-V
2 mA -z
SCI1 data transmit. SCI1TX can be programmed
as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2CLK
36
51
3.3-V
2 mA -z
SCI2 clock. SCI2CLK can be programmed as a
GIO pin.
SCI2RX
35
50
5 V tolerant
4 mA
SCI2 data receive. SCI2RX can be programmed
as a GIO pin.
SCI2TX
34
49
3.3-V
2 mA -z
SCI2 data transmit. SCI2TX can be programmed
as a GIO pin.
13
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Table 2. Terminal Functions (continued)
TERMINAL
NAME
PZ
PGE
INPUT
VOLTAGE (1) (2)
OUTPUT
CURRENT (3)
INTERNAL
PULLUP/
PULLDOWN
DESCRIPTION
SYSTEM MODULE (SYS)
CLKOUT
57
81
3.3-V
PORRST
85
118
3.3-V
RST
86
121
3.3-V
Bidirectional pin. CLKOUT can be programmed
as a GIO pin or the output of SYSCLK, ICLK, or
MCLK.
8 mA
4 mA
IPD (20 µA)
Input master chip power-up reset. External VCC
monitor circuitry must assert a power-on reset.
IPU (20 µA)
Bidirectional reset. The internal circuitry can
assert a reset, and an external system reset can
assert a device reset.
On this pin, the output buffer is implemented as
an open drain (drives low only).
To ensure an external reset is not arbitrarily
generated, TI recommends that an external
pullup resistor be connected to this pin.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
AWD
25
36
3.3-V
Analog watchdog reset. The AWD pin provides a
system reset if the WD KEY is not written in time
by the system, providing an external RC network
circuit is connected. If the user is not using AWD,
TI recommends that this pin be connected to
ground or pulled down to ground by an external
resistor.
For more details on the external RC network
circuit, see the TMS470R1x System Module
Reference Guide (literature number SPNU189).
8 mA
TEST/DEBUG (T/D)
TCK
54
76
TDI
52
74
TDO
53
Test clock. TCK controls the test hardware
(JTAG).
75
8 mA
Test data in. TDI inputs serial data to the test
instruction register, test data register, and
programmable test address (JTAG).
8 mA
Test data out. TDO outputs serial data from the
test instruction register, test data register, identification register, and programmable test address
(JTAG).
Test enable. Reserved for internal use only. TI
recommends that this pin be connected to
ground or pulled down to ground by an external
resistor.
TEST
87
124
TMS
11
17
8 mA
Serial input for controlling the state of the CPU
test access port (TAP) controller (JTAG).
TMS2
10
16
8 mA
Serial input for controlling the second TAP. TI
recommends that this pin be connected to
VCCIO or pulled up to VCCIO by an external
resistor.
TRST
100
144
14
3.3-V
IPD (20 µA)
Test hardware reset to TAP1 and TAP2. IEEE
Standard 1149-1 (JTAG) Boundary-Scan Logic.
TI recommends that this pin be pulled down to
ground by an external resistor.
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Table 2. Terminal Functions (continued)
TERMINAL
NAME
PZ
PGE
INPUT
VOLTAGE (1) (2)
OUTPUT
CURRENT (3)
INTERNAL
PULLUP/
PULLDOWN
DESCRIPTION
FLASH
FLTP2
93
132
NC
NC
VCCP
92
131
3.3-V PWR
Flash test pad 2. For proper operation, this pin
must not be connected [no connect (NC)].
Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
VCC
21
13
63
31
91
53
-
92
-
123
-
130
17
25
48
69
-
86
97
137
90
14
-
34
-
52
-
91
62
122
24
129
18
26
47
68
-
85
98
138
1.8-V
PWR
Core logic supply voltage
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
VCCIO
3.3-V
PWR
Digital I/O supply voltage
SUPPLY GROUND CORE
VSS
GND
Core supply ground reference
SUPPLY GROUND DIGITAL I/O
VSSIO
GND
Digital I/O supply ground reference
15
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
TMS470R1A288 DEVICE-SPECIFIC INFORMATION
Memory
Memory (4G Bytes)
0xFFFF_FFFF
0xFFF8_0000
0xFFF7_FFFF
SYSTEM with PSA, CIM, RTI,
DEC, DMA, MMC, DWD
System Module Control
Registers
(512K Bytes)
IEM
MSM
Reserved
Peripheral Control Registers
(512K Bytes)
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4021
0xFFE8_4020
0xFFE8_4000
Reserved
HET
Reserved
SPI1
Reserved
SCI2
SCI1
Reserved
MibADC
ECP
Reserved
EBM
GIO
HECC
HECC RAM
SCC2
SCC1
Reserved
SCC2 RAM
Reserved
SCC1 RAM
Reserved
I2C3
I2C2
I2C1
Reserved
SPI2
Reserved
S2SIb
Reserved
Reserved
Flash Control Registers
Reserved
MPU Control Registers
Reserved (1 MByte)
0xFFE0_0000
0x7FFF_FFFF
RAM
(61K Bytes)
FLASH
(288K Bytes)
2 Banks
8 Sectors
Program
and
Data Area
0xFFFF_FFFF
0xFFFF_FD00
0xFFFF_FC00
0xFFFF_F700
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EF00
0xFFF7_ED00
0xFFF7_EC00
0xFFF7_E200
0xFFF7_E000
0xFFF7_DE00
0xFFF7_DC00
0xFFF7_DA00
0xFFF7_D900
0xFFF7_D800
0xFFF7_D400
0xFFF7_C800
0xFFF0_0000
HET RAM
(1K Bytes)
0x0000_0024
0x0000_0023
Exception, Interrupt, and
Reset Vectors
0x0000_0000
Reserved
FIQ
IRQ
Reserved
Data Abort
Prefetch Abort
Software Interrupt
Undefined Instruction
Reset
A.
Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B.
The CPU registers are not a part of the memory map.
Figure 1. TMS470R1A288 Memory Map
16
0x0000_0023
0x0000_0020
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
0x0000_0000
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Memory Selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array's starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple of
the decoded block size. For more information on how to control and configure these memory select registers, see
the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature number
SPNU189).
For the memory selection assignments and the memory selected, see Table 3.
Table 3. TMS470R1A288 Memory Selection Assignment
MEMORY
SELECT
MEMORY SELECTED
(ALL INTERNAL)
0 (fine)
FLASH/ROM
1 (fine)
FLASH/ROM
2 (fine)
RAM
MEMORY
SIZE (1)
288K
16K (2)
MPU
MSM
MEMORY BASE ADDRESS REGISTER
NO
YES
MFBAHR0 and MFBALR0
NO
YES
MFBAHR1 and MFBALR1
YES
YES
MFBAHR2 and MFBALR2
STATIC MEM
CTL REGISTER
3 (fine)
RAM
YES
YES
MFBAHR3 and MFBALR3
4 (fine)
HET RAM
1K
NO
NO
MFBAHR4 and MFBALR4
SMCR1
5 (coarse)
CS[5]/GIOC[3]
128 MB
(x8)
1MB (x16)
NO
NO
MCBAHR2 and MCBALR2
SMCR5
6 (coarse)
CS[6]/GIOC[4]
128 MB
(x8)
1MB (x16)
NO
NO
MCBAHR3 and MCBALR3
SMCR6
(1)
(2)
x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.
The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block
size in the memory-base address register.
Memory Security Module
The A288 device also includes a memory security module (MSM) to provide additional security and flexibility to
the memory contents' protection. The password for unlocking the MSM is located in the four words just before
the flash protection keys (see the Flash Protection Keys section below).
JTAG Security Module (JSM)
The A288 device includes a JTAG security module to provide maximum security to the memory contents. The
visible unlock code can be chosen to be in the OTP sector or in the first bank of the user-programmable memory.
For the A288, the visible unlock code is in the OTP sector.
RAM
The A288 device contains 16K-bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This A288 RAM is implemented in one 16K-byte array
selected by two memory-select signals.
NOTE:
This A288 configuration imposes an additional constraint on the memory map for
RAM; the starting addresses for both RAM memory selects cannot be offset from
each other by the multiples of the size of the physical RAM (i.e., 16K for the A288
device). The A288 RAM is addressed through memory selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion of
the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference
Guide (literature number SPNU189).
17
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
F05 Flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the Flash Read and Flash Program and Erase sections below.
Flash Protection Keys
The A288 device provides flash protection keys. These four 32-bit protection keys prevent program/erase/compaction operations from occurring until after the four protection keys have been matched by the
CPU loading the correct user keys into the FMPKEY control register. The protection keys on the A288 are
located in the last 4 words of the first 8K sector. For more detailed information on the flash protection keys and
the FMPKEY control register, see the "Optional Quadruple Protection Keys" and "Programming the Protection
Keys" portions of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
Flash Read
The A288 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to
0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
NOTE:
The flash external pump voltage (VCCP) is required for all operations (program, erase,
and read).
Flash Pipeline Mode
When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. In normal mode, the
flash operates with a system clock frequency of up to 24 MHz. Flash in pipeline mode is capable of accessing
64-bit words and provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read
with no wait states when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).
NOTE:
After a system reset, pipeline mode is disabled (FMREGOPT[0] is a 0). In other
words, the A288 device powers up and comes out of reset in non-pipeline mode.
Furthermore, setting the flash configuration mode bit (GBLCTRL[4]) will override
pipeline mode.
Flash Program and Erase
The A288 device flash contains one 32K-byte memory array (or bank) and one 256K-byte bank, for a total of
288K-bytes of flash, and consists of eight sectors. These eight sectors are sized as follows:
18
SECTOR
NO.
SEGMENT
LOW ADDRESS
OTP
2K Bytes
0x0000_0000
0x0000_07FF
0
8K Bytes
0x0000_0000
0x0000_1FFF
1
8K Bytes
0x0000_2000
0x0000_3FFF
2
8K Bytes
0x0000_4000
0x0000_5FFF
3
8K Bytes
0x0000_6000
0x0000_7FFF
0
64K Bytes
0x0004_0000
0x0004_FFFF
1
64K Bytes
0x0005_0000
0x0005_FFFF
2
64K Bytes
0x0006_0000
0x0006_FFFF
3
64K Bytes
0x0007_0000
0x0007_FFFF
HIGH ADDRESS
MEMORY ARRAYS
(OR BANKS)
BANK0
(32K Bytes)
BANK1
(256K Bytes)
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit
word.
NOTE:
The flash external pump voltage (VCCP) is required for all operations (program, erase,
and read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,
execution can not occur from any sector within a bank that is being programmed or erased.
For more detailed information on flash program and erase operations, see the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
HET RAM
The A288 device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
XOR Share
The A288 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
Peripheral Selects and Base Addresses
The A288 device uses 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These
peripheral selects are fixed and transparent to the user because they are part of the decoding scheme used by
the SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 4.
Table 4. A288 Peripherals, System Module, and Flash Base Addresses
CONNECTING MODULE
ADDRESS RANGE
PERIPHERAL SELECTS
BASE ADDRESS
ENDING ADDRESS
SYSTEM
0xFFFF_FFD0
0x FFFF_FFFF
N/A
RESERVED
0xFFFF_FF70
0xFFFF_FFCB
N/A
DWD
0xFFFF_FF60
0x FFFF_FF6F
N/A
PSA
0xFFFF_FF40
0xFFFF_FF5F
N/A
CIM
0xFFFF_FF20
0xFFFF_FF3F
N/A
RTI
0xFFFF_FF00
0xFFFF_FF1F
N/A
DMA
0xFFFF_FE80
0xFFFF_FEFF
N/A
DEC
0xFFFF_FE00
0xFFFF_FE7F
N/A
RESERVED
0xFFFF_FD80
0xFFFF_FDFF
N/A
MMC
0xFFFF_FD00
0xFFFF_FD7F
N/A
IEM
0xFFFF_FC00
0xFFFF_FCFF
N/A
RESERVED
0xFFFF_FB00
0xFFFF_FBFF
N/A
RESERVED
0xFFFF_FA00
0xFFFF_FAFF
N/A
DMA CMD BUFFER
0xFFFF_F800
0xFFFF_F9FF
N/A
MSM
0xFFFF_F700
0xFFFF_F7FF
N/A
RESERVED
0xFFF8_0000
0xFFFF_F6FF
N/A
RESERVED
0xFFF7_FD00
0xFFF7_FFFF
HET
0xFFF7_FC00
0xFFF7_FCFF
PS[0]
19
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Table 4. A288 Peripherals, System Module, and Flash Base Addresses (continued)
CONNECTING MODULE
20
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
RESERVED
0xFFF7_F900
0xFFF7_FBFF
SPI1
0xFFF7_F800
0xFFF7_F8FF
RESERVED
0xFFF7_F600
0xFFF7_F7FF
SCI2
0XFFF7_F500
0XFFF7_F5FF
SCI1
0xFFF7_F400
0xFFF7_F4FF
RESERVED
0xFFF7_F100
0xFFF7_F3FF
MibADC
0xFFF7_F000
0xFFF7_F0FF
ECP
0xFFF7_EF00
0xFFF7_EFFF
RESERVED
0xFFF7_EE00
0xFFF7_EEFF
EBM
0xFFF7_ED00
0xFFF7_EDFF
GIO
0xFFF7_EC00
0xFFF7_ECFF
HECC
0xFFF7_EA00
0xFFF7_EBFF
RESERVED
0xFFF7_E800
0xFFF7_E9FF
HECC RAM
0xFFF7_E600
0xFFF7_E7FF
RESERVED
0xFFF7_E400
0xFFF7_E5FF
RESERVED
0xFFF7_E300
0xFFF7_E3FF
SCC2
0xFFF7_E200
0xFFF7_E2FF
RESERVED
0xFFF7_E100
0xFFF7_E1FF
SCC1
0xFFF7_E000
0xFFF7_E0FF
RESERVED
0xFFF7_DF00
0xFFF7_DFFF
SCC2 RAM
0xFFF7_DE00
0xFFF7_DEFF
RESERVED
0xFFF7_DD00
0xFFF7_DDFF
SCC1 RAM
0xFFF7_DC00
0xFFF7_DCFF
RESERVED
0xFFF7_DB00
0xFFF7_DBFF
I2C3
0xFFF7_DA00
0xFFF7_DAFF
I2C2
0xFFF7_D900
0xFFF7_D9FF
PERIPHERAL SELECTS
PS[1]
PS[2]
PS[3]
PS[4]
PS[5]
PS[6]
PS[7]
PS[8]
PS[9]
I2C1
0xFFF7_D800
0xFFF7_D8FF
RESERVED
0xFFF7_D500
0xFFF7_D7FF
SPI2
0xFFF7_D400
0xFFF7_D4FF
RESERVED
0xFFF7_CC00
0xFFF7_D3FF
RESERVED
0xFFF7_C900
0xFFF7_CBFF
C2SIb
0xFFF7_C800
0xFFF7_C8FF
RESERVED
0xFFF7_C000
0xFFF7_C7FF
PS[14] - PS[15]
RESERVED
0xFFF0_0000
0xFFF7_BFFF
N/A
Flash Control Registers
0xFFE8_8000
0xFFE8_BFFF
N/A
PS[10]
PS[11] - PS[12]
PS[13]
RESERVED
0xFFF8_4024
0xFFF8_7FFF
N/A
MPU Control Registers
0xFFE8_4000
0xFFE8_4023
N/A
RESERVED
0xFFF8_0000
0xFFF8_3FFF
N/A
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Direct-Memory Access (DMA)
The direct-memory access (DMA) controller transfers data to and from any specified location in the A288
memory map (except for restricted memory locations such as the system control registers area). The DMA
manages up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals.
The DMA controller is connected to both the CPU and peripheral buses, enabling these data transfers to occur in
parallel with CPU activity and thus maximizing overall system performance.
Although the DMA controller has two possible configurations for the A288 device, the DMA controller
configuration is 32 control packets and 16 channels.
For the A288 DMA request hardwired configuration, see Table 5.
Table 5. DMA Request Lines Connections (1)
MODULES
DMA REQUEST INTERRUPT SOURCES
EBM
Expansion Bus DMA request
EBDMAREQ0
DMAREQ[0]
SPI1
SPI1 end-receive
SPI1DMA0
DMAREQ[1]
SPI1
SPI1 end-transmit
SPI1DMA1
DMAREQ[2]
MibADC/I2C1
ADC EV/I2C1 read
MibADCDMA0/I2C1DMA0
DMAREQ[3]
MibADC/SCI1
ADC G1/SCI1 end-receive
MibADCDMA1/SCI1DMA0
DMAREQ[4]
MibADC/SCI1
ADC G2/SCI1 end-transmit
MibADCDMA2/SCI1DMA1
DMAREQ[5]
I2C1
I2C1 write
I2C1DMA1
DMAREQ[6]
SPI2
SPI2 end-receive
SPI2DMA0
DMAREQ[7]
SPI2
SPI2 end-transmit
SPI2DMA1
DMAREQ[8]
I2C2/C2SIb
I2C2 read end-receive/C2SIb end-receive
I2C2DMA0/C2SIDMA0
DMAREQ[9]
I2C2/C2SIb
I2C2 write end-transmit/C2SIb end-transmit I2C2DMA1/C2SIDMA1
DMAREQ[10]
I2C3
I2C3 read
I2C3DMA0
DMAREQ[11]
I2C3
I2C3 write
I2C3DMA1
DMAREQ[12]
Reserved
(1)
DMA CHANNEL
DMAREQ[13]
SCI2
SCI2 end-receive
SCI2DMA0
DMAREQ[14]
SCI2
SCI2 end-transmit
SCI2DMA1
DMAREQ[15]
For DMA channels with more than one assigned request source, only one of the sources listed can be the DMA request generator in a
given application. The device has software control to ensure that there are no conflicts between requesting modules.
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
• Non-request mode (used when transferring from memory to memory)
• Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU194).
Interrupt Priority (IEM to CIM)
Interrupt requests originating from the A288 peripheral modules (i.e., SPI1 or SPI2; SCI1 or SCI2; RTI; etc.) are
assigned to channels within the 48-channel interrupt expansion module (IEM) where, via programmable register
mapping, these channels are then mapped to the 32-channel central interrupt manager (CIM) portion of the SYS
module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel
between sources.
The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
• Fast interrupt request (FIQ)
• Normal interrupt request (IRQ)
21
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
The CIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order in
the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their
associated modules, see Table 6.
Table 6. Interrupt Priority (IEM and CIM)
MODULES
INTERRUPT SOURCES
DEFAULT CIM
INTERRUPT
LEVEL/CHANNEL
IEM CHANNEL
SPI1
SPI1 end-transfer/overrun
0
0
RTI
COMP2 interrupt
1
1
RTI
COMP1 interrupt
2
2
RTI
TAP interrupt
3
3
SPI2
SPI2 end-transfer/overrun
4
4
GIO
GIO interrupt A
5
5
6
6
Reserved
HET
HET interrupt 1
7
7
I2C1
I2C1 interrupt
8
8
SCI1 or SCI2 error interrupt
9
9
SCI1
SCI1 receive interrupt
10
10
C2SIb
SCI1/SCI2
C2SIb interrupt
11
11
I2C2
I2C2 interrupt
12
12
SCC2
SCC2 interrupt A
13
13
SCC1
SCC1 interrupt A
14
14
Reserved
15
15
MibADC end event conversion
16
16
SCI2
SCI2 receive interrupt
17
17
DMA
DMA interrupt 0
18
18
I2C3
I2C3 interrupt
19
19
SCI1
SCI1 transmit interrupt
20
20
SW interrupt (SSI)
21
21
22
22
HET interrupt 2
23
23
SCC2
SCC2 interrupt B
24
24
SCC1
SCC1 interrupt B
25
25
SCI2
SCI2 transmit interrupt
26
26
MibADC end Group 1 conversion
27
27
DMA
DMA Interrupt 1
28
28
GIO
GIO interrupt B
29
29
MibADC end Group 2 conversion
30
30
MibADC
System
Reserved
HET
MibADC
MibADC
Reserved
31
31
Reserved
31
32–37
38
HECC
HECC interrupt A
31
HECC
HECC interrupt B
31
39
31
40–47
Reserved
For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM)
Reference Guide (literature number SPNU211). For more detailed functional information on the CIM, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).
22
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Expansion Bus Module (EBM)
The expansion bus module (EBM) is a standalone module used to bond out both general-purpose input/output
pins and expansion bus interface pins. The module supports 8- and 16-bit expansion bus memory interface
mappings, as well as mapping of the following expansion bus signals:
• 27-bit address bus (EBADDR[26:0]) for x8, 19-bit address bus (EBADDR[18:0]) for x16
• 8- or 16-bit data bus (EBDATA[7:0]or EBDATA[15:0])
• 2 write strobes (EBWR[1:0])
• 2 memory chip selects (EBCS[6:5])
• 1 output enable (EBOE)
• 1 external hold signal for interfacing to slow memories (EBHOLD)
Table 7 shows the multiplexing of I/O signals with the expansion bus interface signals. The mapping of these
pins varies depending on the memory mode.
Table 7. Expansion Bus Mux Mapping (1)
EXPANSION BUS MODULE PINS (2)
GIO
(1)
(2)
x8
x16
GIOB[0]
EBDMAREQ[0]
EBDMAREQ[0]
GIOC[0]
EBOE
EBOE
GIOC[2:1]
EBWR[1:0]
EBWR[1:0]
GIOC[4:3]
EBCS[6:5]
EBCS[6:5]
GIOD[5:0]
EBADDR[5:0]
EBADDR[5:0]
GIOE[7:0]
EBDATA[7:0]
EBDATA[7:0]
GIOF[7:0]
EBADDR[13:6]
EBDATA[15:8]
GIOG[7:0]
EBADDR[21:14]
EBADDR[13:6]
GIOH[4:0]
EBADDR[26:22]
EBADDR[18:14]
GIOH[5]
EBHOLD
EBHOLD
These mappings are controlled by the EBM mux control registers B-H (EBMXCRB - EBMXCRH) and
the EBM control register 1 (EBMCR1). For GPIO functions, use GIODIRx, GIODINx, GIODOUTx,
GIODSETx, and GIODCLRx. For more detailed information, see the TMS470R1x General-Purpose
Input/Output (GIO) Reference Guide (literature number SPNU192) and the TMS470R1x Expansion
Bus Module (EBM) Reference Guide (literature number SPNU222).
x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.
Table 8 lists the names of the expansion bus interface signals and their functions.
Table 8. Expansion Bus Pins
PIN
DESCRIPTION
EBDMAREQ
Expansion bus DMA request
EBOE
Expansion bus output enable
EBWR
Expansion bus write strobe. EBWR[1] controls
EBDATA[15:8] and EBWR[0] controls EBDATA[7:0].
EBCS
Expansion bus chip select
EBADDR
Expansion bus address
EBDATA
Expansion bus data
EBHOLD
Expansion bus hold: an external device connected to
the expansion bus may assert this signal to add wait
states to an expansion bus transaction.
23
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The A288 MibADC module can function in two modes: compatibility mode, where its programmer's model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by
interrupts or by the DMA.
MibADC Event Trigger Enhancements
The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
• Both group 1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.
• The trigger source and polarity can be selected individually for both group 1 and the event group from the
options identified in Table 8.
Table 9. MibADC Event Hookup Configuration
EVENT NO.
SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] OR EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
00
ADEVT
EVENT2
01
HET18
EVENT3
10
Reserved
EVENT4
11
Reserved
For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0]) in
the AD event source register (ADEVTSRC[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
JTAG Interface
There are two main test access ports (TAPs) on the A288 device:
• TMS470R1x CPU TAP
• Device TAP for factory test
Some of the JTAG pins are shared among these two TAPs. The hookup is illustrated in Figure 2.
TMS470R1x CPU
TCK
TCK
TRST
TRST
TMS
TMS
TDI
TDI
TDO
Factory Test
TCK
TRST
TMS2
TMS
TDI
TDO
Figure 2. JTAG Interface
24
TDO
www.ti.com
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
SPNS106 – SEPTEMBER 2005
Documentation Support
Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types of
documentation available include: data sheets with design specifications; complete user's guides for all devices
and development support tools; and hardware and software applications. Useful reference documentation
includes:
• Bulletin
– TMS470 Microcontroller Family Product Bulletin (literature number SPNB086)
• User's Guides
– TMS470R1x System Module Reference Guide (literature number SPNU189)
– TMS470R1x General Purpose Input/Output (GIO) Reference Guide (literature number SPNU192)
– TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)
– TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
– TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
– TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
– TMS470R1x High End Timer (HET) Reference Guide (literature number SPNU199)
– TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
– TMS470R1x MultiBuffered Analog to Digital (MibADC) Reference Guide (literature number SPNU206)
– TMS470R1x ZeroPin Phase Locked Loop (ZPLL) Clock Module Reference Guide (literature number
SPNU212)
– TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
– TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214)
– TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218)
– TMS470R1x JTAG Security Module (JSM) Reference Guide (literature number SPNU245)
– TMS470R1x Memory Security Module (MSM) Reference Guide (literature number SPNU246)
– TMS470 Peripherals Overview Reference Guide (literature number SPNU248)
• Errata Sheet
• TMS470R1A288 TMS470 Microcontrollers Silicon Errata (literature number SPNZ142)
25
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS470R1A288). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed quality
and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
Figure 3 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
26
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
TMS 470 R1 A
288
Pxx
T
OPTIONS
PREFIX
TMS = Fully Qualified Device
FAMILY
470 = TMS470 RISC − Embedded
Microcontroller Family
TEMPERATURE RANGE
T = -40°C − 85°C
PACKAGE TYPE
PZ = 100-pin Low-Profile Quad Flatpack (LQFP)
PGE = 144-pin Low-Profile Quad Flatpack (LQFP)
ARCHITECTURE
R1 = ARM7TDM1 CPU
DEVICE TYPE A
With 288K−Bytes Flash Memory:
48-MHz Frequency
1.8-V Core, 3.3-V I/O
Flash Program Memory
ZPLL Clock
1K-Byte Static RAM
1K-Byte HET RAM (64 Instructions)
AWD
DWD
RTI
10-Bit, 12-Input MibADC
Two SPI Modules
Two SCI Modules
C2SIb
Two CAN [SCC]
HET, 12 Channels
ECP
Three I2C Modules
EBM
MSM
REVISION CHANGE
Blank = Original
FLASH MEMORY
288 = 288K-Bytes Flash Memory
Figure 3. TMS470R1x Family Nomenclature
27
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Device Identification Code Register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Figure 4). The A288 device identification code register
value is 0xn95F.
Figure 4. TMS470 Device ID Bit Allocation Register [offset = FFFF_FFF0h]
31
16
Reserved
15
12
11
10
VERSION
TF
R/F
R-K
R-K
R-K
9
3
2
1
0
PART NUMBER
1
1
1
R-K
R-1
R-1
R-1
LEGEND:
R = Read only, -K = Value constant after RESET; -n = Value after RESET
Table 10. TMS470 Device ID Bit Allocation Register Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
Reads are undefined and writes have no effect.
15-12
VERSION
Silicon version (revision) bits
These bits identify the silicon version of the device. Initial device version numbers start at 0000.
TF
Technology family bit
This bit distinguishes the technology family core power supply:
11
10
28
0
3.3 V for F10/C10 devices
1
1.8 V for F05/C05 devices
R/F
ROM/flash bit
This bit distinguishes between ROM and flash devices:
0
Flash device
1
ROM device
9-3
PART NUMBER
Device-specific part number bits
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the A288 device is 0101011.
2-0
1
Mandatory High
Bits 2, 1, and 0 are tied high by default.
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Device Electrical Specifications and Timing Parameters
Absolute Maximum Ratings
over operating free-air temperature range, A version unless otherwise noted (1)
Supply voltage range:
VCC (2)
-0.3 V to 2.5 V
(2)
Supply voltage range:
VCCIO , VCCAD , VCCP (flash pump)
Input voltage range:
All 5 V- tolerant input pins
-0.3 V to 6.0V
All other input pins
-0.3 V to 4.1V
Input clamp current:
Operating free-air temperature ranges, TA
-0.3 V to 4.1V
All 5-V tolerant pins, PORRST, TRST, TEST, and TCK (VI <
0)
-20 mA (3)
ADIN[0:11] IIK (VI < 0 or VI > VCCAD)
±10 mA
All other pins IIK (VI < 0 or VI > VCCAD)
±20 mA
A version
-40°C to 85°C
Operating junction temperature range, TJ
-40°C to 150°C
Storage temperature range, Tstg
-40°C to 150°C
(1)
(2)
(3)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to their associated grounds.
These pins do not have an internal clamp diode to a positive supply voltage.
Device Recommended Operating Conditions (1)
MIN
VCC
Digital logic supply voltage (Core)
VCCIO
NOM
MAX
UNIT
1.71
2.05
V
Digital logic supply voltage (I/O)
3
3.6
V
VCCAD
MibADC supply voltage
3
3.6
V
VCCP
Flash pump supply voltage
3
3.6
V
VSS
Digital logic supply ground
VSSAD
MibADC supply ground
TA
Operating free-air temperature
TJ
Operating junction temperature
(1)
0
-0.1
A version
V
0.1
V
-40
85
°C
-40
150
°C
All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
29
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (1)
PARAMETER
TEST CONDITIONS
Vhys
Input hysteresis
VIL
Low-level input voltage
All inputs (2)
VIH
High-level input voltage
All inputs
Vth
Input threshold voltage
AWD only (3)
VOL
VOH
IIC
MIN
Low-level output voltage (4)
IOH = IOH MIN
IOH = 50 µA
Input clamp current (I/O pins) (5)
V
2
VCCIO + 0.3
V
1.35
1.8
V
0.2 VCCIO
0.2
0.8 VCCIO
VI = VSS
-1
1
IIH Pulldown
VI = VCCIO
5
40
IIL Pullup
VI = VSS
-40
-5
IIH Pullup
VI = VCCIO
-1
1
All other pins
No pullup or pulldown
-1
1
VI = VSS
-1
1
VI = VCCIO
-1
1
VI = 5 V
0.5
20
1
40
RST
High-level output current
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
30
4
VOL = VOL MAX
All other 3.3 V
I/O (6)
2
5 V tolerant
4
RST
mA
µA
µA
mA
-8
VOH = VOH MIN
-4
All other 3.3 V
I/O (6)
-2
5 V tolerant
-4
mA
SYSCLK = 48 MHz, ICLK = 24
MHz, VCC = 2.05 V
115
mA
SYSCLK = 24 MHz, ICLK = 15
MHz, VCC = 2.05 V
90
mA
VCC Digital supply current (standby mode) (7) (8) OSCIN = 4MHz, VCC = 2.05 V
750
µA
VCC Digital supply current (halt mode) (7) (8)
30°C version, no DC load,
VCCIO = 2.05 V
30
µA
VCC = 2.05 V
160
µA
VCC Digital supply current (operating mode)
ICC
2
8
CLKOUT, TDI,
TDO, TMS,
TMS2
IOH
V
IIL Pulldown
CLKOUT, AWD,
TDI, TDO, TMS,
TMS2
Low-level output current
V
VCCIO - 0.2
-2
VI = 5.5 V
IOL
V
VI < VSSIO - 0.3 or VI > VCCIO +
0.3
Input current (5 V tolerant input pins)
UNIT
0.8
IOL = IOL MAX
High-level output voltage (4)
II
MAX
-0.3
IOL = 50 µA
Input current (3.3 V input
pins)
TYP
0.15
Source currents (out of the device) are negative while sink currents (into the device) are positive.
This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section.
These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
Parameter does not apply to input-only or output-only pins.
The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a
low level and the other is outputting a high level, the resulting value will always be low.
For flash banks/pumps in sleep mode.
For reduced power consumption in low power mode, CANSRX and CANSTX should be driven output LOW.
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Electrical Characteristics (continued)
over recommended operating free-air temperature range
PARAMETER
ICCIO
MAX
UNIT
VCCIO Digital supply current (operating mode)
No DC load, VCCIO = 3.6 V (9)
TEST CONDITIONS
15
mA
VCCIO Digital supply current (standby mode) (8)
No DC load, VCCIO = 3.6 V (9)
10
µA
30°C version, no DC load,
VCCIO = 3.6 V (9)
5
µA
VCCIO Digital supply current (halt
ICCAD
mode) (8)
MIN
TYP
No DC load, VCCIO = 3.6 V (9)
5
µA
VCCAD supply current (operating mode)
All frequencies, VCCAD = 3.6 V
25
mA
VCCAD supply current (standby mode)
No DC load, VCCAD = 3.6 V (9)
10
µA
VCCAD supply current (halt mode)
30°C version, no DC load,
VCCAD = 3.6 V
5
ICCP
VCCP pump supply current
µA
VCCAD = 3.6 V
5
µA
VCCP = 3.6 V read operation
60
mA
VCCP = 3.6 V program and erase
70
mA
VCCP = 3.6 V standby mode operation (7)
10
µA
30°C version, no DC load,
VCCP = 3.6 V halt mode operation (7)
5
µA
VCCP = 3.6 V halt mode operation (7)
5
µA
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
(9)
I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO - 0.2 V.
Parameter Measurement Information
Ω
Where:
IOL
=
IOH
=
VLOAD =
CL
=
IOL MAX for the respective pin (A)
IOH MIN for the respective pin(A)
1.5 V
150-pF typical load-circuit capacitance(B)
A.
For these values, see the "Electrical Characteristics over Recommended Operating Free-Air Temperature Range"
table.
B.
All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 5. Test Load Circuit
31
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Timing Parameter Symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
CM
Compaction, CMPCT
RD
Read
CO
CLKOUT
RST
Reset, RST
ER
Erase
RX
SCInRX
ICLK
Interface clock
S
Slave mode
M
Master mode
SCC
SCInCLK
OSC, OSCI
OSCIN
SIMO
SPInSIMO
OSCO
OSCOUT
SOMI
SPInSOMI
P
Program, PROG
SPC
SPInCLK
R
Ready
SYS
System clock
R0
Read margin 0, RDMRGN0
TX
SCInTX
R1
Read margin 1, RDMRGN1
Lowercase subscripts and their meanings are:
a
access time
r
rise time
c
cycle time (period)
su
setup time
d
delay time
t
transition time
f
fall time
v
valid time
h
hold time
w
pulse duration (width)
The following additional letters are used with these meanings:
H
High
X
Unknown, changing, or don't care level
L
Low
Z
High impedance
V
Valid
32
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
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SPNS106 – SEPTEMBER 2005
External Reference Resonator/Crystal Oscillator Clock Option
The oscillator is enabled by connecting the appropriate fundamental 4-10 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6a. The oscillator is a single-stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and
HALT mode. TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best
tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 6b.
" ! A.
The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 6. Crystal/Clock Connection
33
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
ZPLL AND CLOCK SPECIFICATIONS
Timing Requirements for ZPLL Circuits Enabled or Disabled
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
tw(OSCIL)
tw(OSCIH)
f(OSCRST)
(1)
MIN
TYP MAX UNIT
4
10 MHz
100
ns
Pulse duration, OSCIN low
15
ns
Pulse duration, OSCIN high
15
ns
OSC FAIL
frequency (1)
53
kHz
Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL[15]) and the OSC FAIL flag (GLBSTAT[1])
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
Switching Characteristics Over Recommended Operating Conditions for Clocks (1) (2)
PARAMETER
f(SYS)
System clock frequency (4)
f(CONFIG)
System clock frequency - flash config mode
f(ICLK)
Interface clock frequency
f(ECLK)
External clock output frequency for ECP module
tc(SYS)
Cycle time, system clock
tc(CONFIG)
Cycle time, system clock - flash config mode
tc(ICLK)
Cycle time, interface clock
tc(ECLK)
Cycle time, ECP module external clock output
(1)
(2)
(3)
(4)
34
TEST CONDITIONS (3)
MAX
UNIT
Pipeline mode enabled
MIN
48
MHz
Pipeline mode disabled
24
MHz
24
MHz
Pipeline mode enabled
25
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
25
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
20.8
ns
Pipeline mode disabled
41.6
ns
41.6
ns
Pipeline mode enabled
40
ns
Pipeline mode disabled
41.6
ns
Pipeline mode enabled
40
ns
Pipeline mode disabled
41.6
ns
f(SYS) = M × f(OSC) / R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT[0]).
Flash Vread must be set to 5 V to achieve maximum system clock frequency.
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Switching Characteristics Over Recommended Operating Conditions for External Clocks (1) (2) (3)
(see Figure 7 and Figure 8)
PARAMETER
tw(COL)
TEST CONDITIONS
Pulse duration, CLKOUT low
0.5tc(SYS) - tf
ICLK: X is even or 1 (5)
0.5tc(ICLK) - tf
ICLK: X is odd and not 1 (5)
tw(COH)
Pulse duration, CLKOUT high
tw(EOH)
Pulse duration, ECLK low
Pulse duration, ECLK high
0.5tc(SYS) - tr
ICLK: X is even or 1 (5)
0.5tc(ICLK) - tr
(1)
(2)
(3)
(4)
(5)
UNIT
ns
ns
0.5tc(ICLK) - 0.5tc(SYS) - tr
N is even and X is even or odd
0.5tc(ECLK) - tf
N is odd and X is even
0.5tc(ECLK) - tf
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) - tf
N is even and X is even or odd
0.5tc(ECLK) - tr
N is odd and X is even
0.5tc(ECLK) - tr
N is odd and X is odd and not 1
MAX
0.5tc(ICLK) + 0.5tc(SYS) - tf
SYSCLK or MCLK (4)
ICLK: X is odd and not 1 (5)
tw(EOL)
MIN
SYSCLK or MCLK (4)
ns
ns
0.5tc(ECLK) - 0.5tc(SYS) - tr
X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).
Figure 7. CLKOUT Timing Diagram
Figure 8. ECLK Timing Diagram
35
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
RST AND PORRST TIMINGS
Timing Requirements for PORRST
(see Figure 9)
MIN
MAX UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and become
active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and become
active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before V CCIO > VCCIOPORL
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
tsu(PORRST)f
Setup time, PORRST active before VCC≤ VCCPORH during power down
8
µs
th(PORRST)rio
Hold time, PORRST active after VCC > VCCIOPORH
1
ms
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
tsu(PORRST)fio
Setup time, PORRST active before VCC≤ VCCIOPORH during power down
0
ns
tsu(VCCIO)f
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
0
ns
1.1
2.75
V
V
V
V
V
V
0.5
1.5
0.2 VCCIO
0.6
Figure 9. PORRST Timing Diagram
Switching Characteristics Over Recommended Operating Conditions for RST (1)
PARAMETER
tv(RST)
tfsu
(1)
36
Valid time, RST active after PORRST inactive
Valid time, RST active (all others)
Flash start-up time, from RST inactive to fetch of first instruction from flash (flash pump
stabilization time)
MIN
4112tc(OSC)
8tc(SYS)
670tc(OSC)
MAX UNIT
ns
ns
Specified values do NOT include rise/fall times. For rise and fall timings, see the "Switching Characteristics for Output Timings versus
Load Capacitance" table.
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
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SPNS106 – SEPTEMBER 2005
JTAG SCAN INTERFACE TIMING
(JTAG Clock Specification 10-MHz and 50-pF Load on TDO Output)
MIN
MAX
UNIT
tc(JTAG)
Cycle time, JTAG low and high period
50
ns
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
th(TCKr
ns
Hold time, TDI, TMS after TCKr
15
th(TCKf -TDO)
Hold time, TDO after TCKf
10
td(TCKf -TDO)
Delay time, TDO valid after TCK fall (TCKf)
-TDI/TMS)
ns
45
ns
Figure 10. JTAG Scan Timings
37
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
OUTPUT TIMINGS
Switching Characteristics for Output Timings versus Load Capacitance (CL)
(see Figure 11)
PARAMETER
tr
tf
tr
tf
tr
tf
tr
tf
Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
Rise time, RST
Fall time, RST
Rise time, 4 mA, 5 V tolerant pins
Fall time, 4 mA, 5 V tolerant pins
MIN
MAX
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5.0
CL = 100 pF
3
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5.0
CL = 100 pF
3
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
3
10
CL = 50 pF
3.5
12
CL = 100 pF
7
21
CL = 150 pF
9
28
CL = 15 pF
2
8
CL = 50 pF
2.5
9
8
25
CL = 150 pF
11
35
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
CL = 100 pF
Rise time, all other output pins
Fall time, all other output pins
Figure 11. CMOS-Level Outputs
38
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
INPUT TIMINGS
Timing Requirements for Input Timings (1)
(see Figure 12)
MIN
tpw
(1)
Input minimum pulse width
MAX UNIT
tc(ICLK) + 10
ns
tc(ICLK) = interface clock cycle time = 1 / f(ICLK)
Figure 12. CMOS-Level Inputs
FLASH TIMINGS
Timing Requirements for Program Flash (1)
MIN
TYP
MAX
UNIT
4
16
200
µs
288K-byte programming time (2)
2
8
s
terase(sector)
Sector erase time
5
15
s
twec
Write/erase cycles at TA = 105°C
tfp(RST)
Flash pump settling time from RST to SLEEP
134tc(SYS)
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
134tc(SYS)
tfp(STANDBY)
Initial flash pump settling time from STANDBY to ACTIVE
67tc(SYS)
tprog(16-bit)
Half word (16-bit) programming time
tprog(Total)
(1)
(2)
1000
10000
cycles
ns
For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
The 288K-byte programming time includes overhead of state machine.
39
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
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SPNS106 – SEPTEMBER 2005
SPIn MASTER MODE TIMING PARAMETERS
SPIn Master Mode External Timing Parameters
(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 13)
NO.
1
2 (5)
3 (5)
4 (5)
5 (5)
6 (5)
7 (5)
(1)
(2)
(3)
(4)
(5)
MIN
MAX
UNIT
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M - tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M - tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M - tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M - tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
tc(SPC)M - 5 - tf
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
tc(SPC)M - 5 - tr
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
4
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
4
tc(SPC)M
Cycle time, SPInCLK (4)
tw(SPCH)M
ns
ns
ns
ns
ns
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2[0]) is cleared.
tc(ICLK) = interface clock cycle time = 1 / f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2tc(ICLK)≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2[1]).
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Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 0)
40
ns
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
SPIn Master Mode External Timing Parameters
(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 14)
NO.
1
2 (5)
3 (5)
4 (5)
5 (5)
6 (5)
7 (5)
(1)
(2)
(3)
(4)
(5)
MIN
MAX
UNIT
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M - tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M - tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M - tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M - tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid (clock polarity = 0)
0.5tc(SPC)M - 10
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1)
0.5tc(SPC)M - 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0)
0.5tc(SPC)M - 5 - tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1)
0.5tc(SPC)M - 5 - tf
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high (clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0)
4
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1)
4
tc(SPC)M
Cycle time, SPInCLK (4)
tw(SPCH)M
ns
ns
ns
ns
ns
ns
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2[0]) is set.
tc(ICLK) = interface clock cycle time = 1 / f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2tc(ICLK)≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2[1]).
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#$"%$$#
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#$"$
%#$
Figure 14. SPIn Master Mode External Timing (CLOCK PHASE = 1)
41
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16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
SPIn SLAVE MODE TIMING PARAMETERS
SPIn Slave Mode External Timing Parameters
(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 15)
NO.
1
2 (6)
3 (6)
MIN
MAX
UNIT
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
6 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
6 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
tc(SPC)S - 6 - tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
tc(SPC)S - 6 - tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
6
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 0)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
6
tc(SPC)S
Cycle time, SPInCLK (5)
tw(SPCH)S
4 (6)
5 (6)
6(6)
7(6)
(1)
(2)
(3)
(4)
(5)
(6)
ns
ns
ns
ns
ns
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2[0]) is cleared.
If the SPI is in slave mode, the following must be true: tc(SPC)S≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
tc(ICLK) = interface clock cycle time = 1 /f(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2tc(ICLK)≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2[1]).
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! "$&
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$
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Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
42
ns
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
SPIn Slave Mode External Timing Parameters
(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 16)
NO.
1
2 (6)
3 (6)
MIN
MAX
UNIT
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
0.5tc(SPC)S - 6 - tr
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI data valid
(clock polarity = 1)
0.5tc(SPC)S - 6 - tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S - 6 - tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)S - 6 - tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
6
tc(SPC)S
Cycle time, SPInCLK (5)
tw(SPCH)S
4 (6)
5 (6)
6(6)
7(6)
(1)
(2)
(3)
(4)
(5)
(6)
ns
ns
ns
ns
ns
ns
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2[0]) is set.
If the SPI is in slave mode, the following must be true: tc(SPC)S≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
tc(ICLK) = interface clock cycle time = 1 /f(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2tc(ICLK)≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2[1]).
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Figure 16. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
43
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK
Timing Requirements for Internal Clock SCIn Isosynchronous Mode (1) (2) (3)
(see Figure 18)
(BAUD + 1)
IS EVEN OR BAUD = 0
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224 tc(ICLK)
3tc(ICLK)
(224 -1) tc(ICLK)
ns
tc(SCC)
Cycle time,
SCInCLK
tw(SCCL)
Pulse duration,
SCInCLK low
0.5tc(SCC) - tf
0.5tc(SCC) + 5
0.5tc(SCC) + 0.5tc(ICLK) - tf
0.5tc(SCC) + 0.5tc(ICLK)
ns
tw(SCCH)
Pulse duration,
SCInCLK high
0.5tc(SCC) - tr
0.5tc(SCC) + 5
0.5tc(SCC) - 0.5tc(ICLK) - tr
0.5tc(SCC) - 0.5tc(ICLK)
ns
td(SCCH-TXV)
Delay time,
SCInCLK high to
SCInTX valid
10
ns
tv(TX)
Valid time,
SCInTX data
after SCInCLK
low
tc(SCC) - 10
tc(SCC) - 10
ns
tsu(RX-SCCL)
Setup time,
SCInRX before
SCInCLK low
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
tv(SCCL-RX)
Valid time,
SCInRX data
after SCInCLK
low
-tc(ICLK) + tf + 20
- tc(ICLK) + tf + 20
ns
(1)
(2)
(3)
10
BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
A.
Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock
44
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
SCIn ISOSYNCHRONOUS MODE TIMINGS EXTERNAL CLOCK
Timing Requirements for External Clock SCIn Isosynchronous Mode (1) (2)
(see Figure 17)
MIN
MAX
UNIT
tc(SCC)
Cycle time, SCInCLK (3)
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC) - 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC) - 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + tr
ns
tv(TX)
Valid time, SCInTX data after SCInCLK low
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
(1)
(2)
(3)
8tc(ICLK)
ns
2tc(SCC) -10
ns
0
ns
2tc(ICLK) + 10
ns
tc(ICLK) = interface clock cycle time = 1 / f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When driving an external SCInCLK, the following must be true: tc(SCC)≥ 8tc(ICLK).
A.
Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 18. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
45
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
I2C TIMING
Table 11 below assumes testing over recommended operating conditions.
Table 11. I2C Signals (SDA and SCL) Switching Characteristics (1)
STANDARD
MODE
PARAMETER
MIN
MAX
150
FAST MODE
MIN
MAX
75
150
UNIT
tc(I2CCLK)
Cycle time, I2C module clock
75
tc(SCL)
Cycle time, SCL
10
2.5
µs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START condition)
4.7
0.6
µs
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated START condition)
4
0.6
µs
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
th(SDA-SCLL)
Hold time, SDA valid after SCL low
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
4.7
1.3
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
4.0
0.6
tw(SP)
Pulse duration, spike (must be suppressed)
Cb
(1)
(2)
(3)
(3)
For I2C bus devices
3.45 (2)
0
0
0
Capacitive load for each bus line
400
ns
0.9
µs
µs
µs
50
ns
400
pF
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
The maximum th(SDA-SCLL) for I2C bus devices needs only be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
Cb = The total capacitance of one bus line in pF.
SDA
tw(SDAH)
tw(SP)
tsu(SDA−SCLH)
tr(SCL)
tw(SCLL)
tsu(SCLH−SDAH)
tw(SCLH)
SCL
tc(SCL)
tf(SCL)
th(SCLL−SDAL)
th(SDA−SCLL)
tsu(SCLH−SDAL)
th(SCLL−SDAL)
Stop
Start
Repeated
Stop
A.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
B.
The maximum th(SDA-SCLL) needs only be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL
signal.
C.
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250
ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr max + tsu(SDA-SCLH).
D.
Cb = total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
Figure 19. I2C Timings
46
ns
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
STANDARD CAN CONTROLLER (SCC) MODE TIMINGS
Dynamic Characteristics for the CANSTX and CANSRX Pins
PARAMETER
MIN
pin (1)
td(CANSTX)
Delay time, transmit shift register to CANSTX
td(CANSRX)
Delay time, CANSRX pin to receive shift register
(1)
MAX
UNIT
15
ns
5
ns
These values do not include the rise/fall times of the output buffer.
47
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
EXPANSION BUS MODULE TIMING
Expansion Bus Timing Parameters, -40°C ≤ TJ≤ 150°C, 3.0 V ≤ V CC≤ 3.6 V
(see Figure 20 and Figure 21)
MIN
MAX
20.8
UNIT
tc(CO)
Cycle time, CLKOUT
td(COH-EBADV)
Delay time, CLKOUT high to EBADDR valid
21.4
ns
th(COH-EBADIV)
Hold time, EBADDR invalid after CLKOUT high
12.4
ns
td(COH-EBOE)
Delay time, CLKOUT high to EBOE fall
11.4
ns
th(COH-EBOEH)
Hold time, EBOE rise after CLKOUT high
11.4
ns
td(COL-EBWR)
Delay time, CLKOUT low to write strobe (EBWR) low
11.3
ns
th(COL-EBWRH)
Hold time, EBWR high after CLKOUT low
11.6
ns
tsu(EBRDATV-COH)
Setup time, EBDATA valid before CLKOUT high (READ) (1)
th(COH-EBRDATIV)
Hold time, EBDATA invalid after CLKOUT high (READ)
15.2
(WRITE) (2)
td(COL-EBWDATV)
Delay time, CLKOUT low to EBDATA valid
th(COL-EBWDATIV)
Hold time, EBDATA invalid after CLKOUT low (WRITE)
ns
ns
(-14.7)
ns
16.1
ns
14.7
ns
13.6
ns
13.2
ns
SECONDARY TIMES
td(COH-EBCS0)
Delay, CLKOUT high to EBCS0 fall
th(COH-EBCS0H)
Hold, EBCS0 rise after CLKOUT high
tsu(COH-EBHOLDL)
Setup time, EBHOLD low to CLKOUT high (1)
10.9
ns
tsu(COH-EBHOLDH)
Setup time, EBHOLD high to CLKOUT high (1)
10.5
ns
(1)
(2)
Setup time is the minimum time under worst case conditions. Data with less setup time will not work.
Valid after CLKOUT goes low for write cycles.
tc(CO)
CLKOUT
th(COH-EBADIV)
td(COH-EBADV)
Valid
EBADDR
tsu(EBRDATV-COH)
th(COH-EBRDATIV)
Valid
EBDATA
th(COH-EBOEH)
td(COH-EBOE)
EBOE
td(COH-EBCS0)
th(COH-EBCS0H)
EBCS0
tsu(COH-EBHOLDH)
tsu(COH-EBHOLDL)
EBHOLD
1 Hold State
Figure 20. Expansion Memory Signal Timing - Reads
48
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
tc(CO)
CLKOUT
th(COH-EBADIV)
td(COH-EBADV)
Valid
EBADDR
th(COL-EBWDATIV)
td(COL-EBWDATV)
Valid
EBDATA
th(COL-EBWRH)
td(COL-EBWR)
EBWR
td(COH-EBCS0)
td(COH-EBCS0)
EBCS0
tsu(COH-EBHOLDH)
tsu(COH-EBHOLDL)
EBHOLD
1 Hold State
Figure 21. Expansion Memory Signal Timing - Writes
49
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
HIGH-END TIMER (HET) TIMINGS
Minimum PWM Output Pulse Width:
This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale
factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
Minimum Input Pulses that Can Be Captured:
The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the
HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which
is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
NOTE:
Once the input pulse width is greater than LRP, the resolution of the measurement is
still HRP. (That is, the captured value gives the number of HRP clocks inside the
pulse.)
Abbreviations:
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
50
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
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SPNS106 – SEPTEMBER 2005
MULTI-BUFFERED A-TO-D CONVERTER (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on VSS
and VCC, from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO
unless otherwise noted.
Resolution
10 bits (1024 values)
Monotonic
Assured
00h to 3FFh [00 for VAI≤ ADREFLO; 3FF for VAI≥ ADREFHI]
Output conversion code
Table 12. MibADC Recommended Operating Conditions (1)
MIN
MAX
UNIT
ADREFHI
A-to-D high-voltage reference source
VSSAD
VCCAD
V
ADREFLO
A-to-D low-voltage reference source
VSSAD
VCCAD
V
VAI
Analog input voltage
VSSAD - 0.3
VCCAD + 0.3
V
IAIC
Analog input clamp current (2)
(VAI < VSSAD - 0.3 or VAI > VCCAD + 0.3)
-2
2
mA
(1)
(2)
For VCCAD and VSSAD recommended operating conditions, see the "Device Recommended Operating Conditions" table.
Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Table 13. Operating Characteristics Over Full Ranges of Recommended Operating Conditions (1) (2)
PARAMETER
Ri
Analog input resistance
DESCRIPTION/CONDITIONS
MIN
See Figure 22.
TYP
250
Conversion
MAX UNIT
500
Ω
10
pF
Ci
Analog input capacitance
See Figure 22.
IAIL
Analog input leakage current
See Figure 22.
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which specified
accuracy is maintained
ADREFHI - ADREFLO
EDNL
Differential nonlinearity error
Difference between the actual step width
and the ideal value. See Figure 23.
±2 LSB
EINL
Integral nonlinearity error
Maximum deviation from the best straight
line through the MibADC. MibADC transfer characteristics, excluding the
quantization error. See Figure 24.
±2 LSB
E TOT
Total error/absolute accuracy
Maximum value of the difference between an analog value and the ideal
midstep value. See Figure 25.
±2 LSB
(1)
(2)
Sampling
-1
3
30
pF
1
µA
5
mA
3.6
V
VCCAD = ADREFHI
1 LSB = (ADREFHI - ADREFLO)/ 210 for the MibADC
51
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
Figure 22. MibADC Input Equivalent Circuit
Multi-Buffer ADC Timing Requirements
MIN
µs
µs
Delay time, conversion time
0.55
µs
Delay time, total sample/hold and conversion time
1.55
µs
td(SH)
Delay time, sample and hold time
td(C)
td(SHC)
(1)
MAX UNIT
1
Cycle time, MibADC clock
(1)
NOM
0.05
tc(ADCLK)
This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for
more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
The differential nonlinearity error shown in Figure 23 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
!
!
A.
1 LSB = (ADREFHI - ADREFLO)/210
Figure 23. Differential Nonlinearity (DNL)
52
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
The integral nonlinearity error shown in Figure 24 (sometimes referred to as linearity error) is the deviation of the
values on the actual transfer function from a straight line.
"#$ $%
"#$ $"#$ &
$"" "
$"#$ & A.
!%$%
1 LSB = (ADREFHI - ADREFLO)/210
Figure 24. Integral Nonlinearity (INL) Error
The absolute accuracy or total error of an MibADC as shown in Figure 25 is the maximum value of the difference
between an analog value and the ideal midstep value.
A.
1 LSB = (ADREFHI - ADREFLO)/210
Figure 25. Absolute Accuracy (Total) Error
53
TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106 – SEPTEMBER 2005
PGE Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
43
RΘJC
5
PZ Thermal Resistance Characteristics
54
PARAMETER
°C/W
RΘJA
48
RΘJC
5
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147 / C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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