PI6C100 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Precision Clock Synthesizer for Desktop PCs Features Description The PI6C100 is a high-speed low-noise clock generator designed to work with the PI6C180 clock buffer to meet all clock needs for Intel Architecture platforms. CPU and chipset clock frequencies of 66.6 MHz and 100 MHz are supported. Four copies of CPU clock with VDD of 2.5V + 5% 100 MHz or 66 MHz operation Eight copies of PCI clock, (synchronous with CPU clock) 3.3V Two copies of IO APIC clock @14.31818 MHz Two copies of 48 MHz clock Three copies of Ref. clock @14.31818 MHz (3.3V TTL) Low cost 14.31818 MHz crystal oscillator input Spread spectrum modulation of CPU and PCI clocks for reduced EMI Power management control Isolated core VDD, VSS pins for noise reduction 48-pin SSOP package (V48) Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PWRDWN# signal may be used to orderly power down (or up) the system. Pin Configuration Block Diagram Buffers REF0 REF1 VDDREF XTAL_IN XTAL_OUT 3 REF[0:2] REF OSC VDDAPIC VDDCPU 0,1 SEL0,1 SPREAD# SEL100/66# 2 APIC0,1 4 CPUCLK[0:3] PLL1 CPUSTOP# ÷2 VDDPCI 0,1 7 PCICLK[1:7] PCISTOP# PCICLK_F VDD48MHz PLL2 2 48MHz 198 VSSREF XTAL_IN XTAL_OUT VSSPCI0 PCICLK_F PCICLK1 VDDPCI0 PCICLK2 PCICLK3 VSSPCI1 PCICLK4 PCICLK5 VDDPCI1 PCICLK6 PCICLK7 VSSPCI2 VDDCORE0 VSSCORE0 VDD48MHz 48MHz 48MHz VSS48MHz 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 9 48-Pin 40 10 V48 39 38 11 37 12 36 13 35 14 34 15 33 16 17 32 18 31 19 30 20 29 21 28 22 27 23 26 25 24 VDDREF REF2 VDDAPIC APIC0 APIC1 VSSAPIC NC VDDCPU0 CPUCLK0 CPUCLK1 VSSCPU0 VDDCPU1 CPUCLK2 CPUCLK3 VSSCPU1 VDDCORE1 VSSCORE1 PCISTOP# CPUSTOP# PWRDWN# SPREAD# SEL0 SEL1 SEL100/66# PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description Pin Signal Name Type Qty. De s cription 1,2,47 REF[0:2] O 3 14.318 MHz clock output. 3 VSSREF ground 1 Ground for REF[0:2] outputs 48 VDDREF power 1 Power for REF[0:2] outputs 4 XTAL_IN I 1 14.318 MHz crystal input. 5 XTAL_OUT O 1 14.318 MHz crystal output. 6,12,18 VSSPCI[0:2] ground 3 Ground for PCI clock outputs 7 PCICLK_F O 1 Free running PCI clock output 9,15 VDDPCI[0:1] power 2 Power for PCI clock outputs 8,10,11,13, 14,16,17 PCICLK[1:7] O 7 PCI clock outputs, TTL compatible 3.3V 19,33 VDDCORE[0:1] power 2 Isolated power for core 20,32 VSSCORE[0:1] ground 2 Isolated ground for core 21 VDD48MHz power 1 Isolated power for 48 MHz outputs 24 VSS48MHz ground 1 Isolated ground for 48 MHz outputs 22,23 48MHz O 2 48 MHz outputs 26,27 SEL[0:1] 1 2 Logic select pins. LVTTL levels 25 SEL100/66# I 1 Select pin for enabling 100 MHz or 66 MHz H = 100 MHz. L = 66 MHz 29 PWRDWN# I 1 Powers down device when held LOW 30 CPUSTOP# I 31 PCI_STOP# I 1 Stops PCI clocks LOW if held LO W 37,41 VDDCPU[0:1] power 2 Power for CPU outputs 34,38 VSSPCU[0:] ground 2 Ground for CPU outputs O 4 CPU and Host clock outputs 2.5V 35,36,39,40 CPUCLK[0:3] Stops CPU clocks LOW if held LOW 43 VSSAPIC ground 1 Ground for APIC outputs 46 VDDAPIC power 1 Power for APIC outputs 44,45 APIC[0:1] O 2 APIC outputs @2.5V. 14.31818 MHz 28 SPREAD# I 1 Enables Spread Spectrum feature when LO W 42 NC 1 Reserved for future modification 199 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Select Functions SEL100/66# SEL1 SEL0 Function 0 0 0 Hi- Z 0 0 1 Reserved 0 1 0 Reserved 0 1 1 66 MHz active 1 0 0 Test mode 1 0 1 Reserved 1 1 0 Reserved 1 1 1 100 MHz active Outputs Function D e s cription CPU PCI, PCI F 48M Hz REF[0:2] IOAPIC Hi- Z Hi- Z Hi- Z Hi- Z Hi- Z Hi- Z Test Mode TCLK /2 TCLK /6 TCLK /2 TCLK TCLK Note: TCLK is a test clock over driven on the XTAL_IN input during test mode. Clock Enable Configuration CPU_STOP# PCI_STOP# PWR_D WN# CPUCLK PCICLK Othe r Clocks Crys tal VCO's X X 0 low low Stopped off off 0 0 1 low low running running running 0 1 1 low 33 MHz running running running 1 0 1 100/66 MHz low running running running 1 1 1 100/66 MHz 33 MHz running running running 200 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 CPU_STOP# is an input signal used to turn off the CPU clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock and is internally synchronized to the external PCICLK_F output. All other clocks continue to run while the CPU clocks are disabled. The CPU clocks are always stopped in a low state and started guaranteeing that the high pulse width is a full pulse. CPU clock on latency is 2 or 3 CPU clocks and CPU clock off latency is 2 or 3 CPU clocks. Power Management Timing Late ncy Signal Signal State CPU_STOP# 0 (disabled) 1 1 (enabled) 1 0 (disabled) 1 1 (enabled) 1 1 (normal operation) 3ms 0 (power down 2 max. PCI_STOP# PWR_DWN# No. of ris ing e dge s of fre e running PCICLK Notes: 1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs between when the clock disable goes low/high to when the first valid clock comes out of the device. 2. Power up latency is from when PWR_DWN# goes inactive (high) to when the first valid clocks are driven from the device. CPUCLK (Internal) CPUCLK (Internal) PCICLK_F (Free-running) CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK (External) CPU_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3 CPU_STOP# is an input signal that is made synchronous to the free running PCICLK_F. 4. ON/OFF latency shown is 2 CPU clocks. 201 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PCI_STOP# is an input signal used to turn off the PCI clocks for low power operation. PCI clocks are stopped in the low state and started with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic. CPUCLK (Internal) PCICLK (Internal) PCICLK_F (Free-running) CPU_STOP# PCI_STOP# PWR_DWN# PCICLK (External) PCI_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. The PWR_DWN# is used to place the device in a very low power state. PWR_DWN# is an asynchronous active low input. Internal clocks are stopped after the device is put in power down mode. The power on latency is less than 3ms. PCI_STOP# and CPU_STOP# are dont cares during the power down operations. The REF0 clock is stopped in the LOW state as soon as possible. CPUCLK (Internal) PCICLK (Internal) PWR_DWN# CPUCLK (External) PCICLK (External) VCO Crystal PWR_DWN# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 202 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................................................65°C to +150°C Ambient Temperature with Power Applied .................................... 0°C to +70°C 3.3V Supply Voltage to Ground Potential ....................................... 0.5V to +4.6V 2.5V Supply Voltage to Ground Potential ....................................... 0.5V to +3.6V DC Input Voltage ............................................................................ 0.5V to +4.6V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (VDDQ3 = +3.3V ± 5%, VDDQ2 = +2.5V ± 5%, TA = 0°C to +70°C) Parame te rs D e s cription Te s t Conditions IIL Input Leakage Current 0V < VIN < VDD VIL Input Low Voltage VIH Input High Voltage @VDD VOL O utput Low Voltage IOL = 1mA, VDD = Min. VOH O utput High Voltage IOL = - 1mA, VDD = Min. M in. Typ. M ax. Units -5 +5 µA VSS - 0.3 0.8 +2.0 VDD +0.3 0.4 2 VDDQ2 = 2.625V, PWRDWN#=0 CLOAD = Max. 100 VDDQ2 =2.625V @ 66.66 MHz CLOAD = Max. 72 IDDQ2 VDDQ2 =2.625V @ 100 MHz CLOAD = Max. 100 IDDQ3 VDDQ3 =3.465V, PWRDWN#=0 CLOAD = Max. 500 VDDQ3 =3.465V, 66.66 MHz CLOAD = Max. 170 VDDQ3 =3.465V, 100 MHz CLOAD = Max. 170 IDDQ2 IDDQ2 IDDQ3 2.5V Supply Current 3.3V Supply Current IDDQ3 V µA mA µA mA CIN Input Capacitance 5 COUT O utput Capacitance 6 LPIN Pin Conductance 7 nH 70 °C TA Ambient Temperature No Airflow 0 203 pF PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Operating Specifications Symbol Parame te rs Conditions M in. M ax. VDDCORE 2.0 VDDCORE +0.3 VSS - 0.3 0.8 -5 +5 Units Input Voltage , VDDCORE [0-1] = 3.3V ± 5% VIH3 Input high voltage VIL3 Input low voltage IIL Input leakage current 0 < VIN < VDDCORE V µA Output Voltage = 2.5V ± 5% VDDAPIC, VDDCPU [0-1] VOH2 O utput high voltage IOH = - 1mA VOL2 O utput low voltage IOL = 1mA 2.0 0.4 V Output Voltage = 3.3V ± 5% VDDREF VOH3 O utput high voltage IOH = - 1mA VOL3 O utput low voltage IOL = 1mA 2.4 0.4 V Output Voltage = 3.3V ± 5% VDDCPI [0-1] VPOH PCI Bus output high voltage IOH = - 1mA VPOL PCI Bus output low voltage IOL = 1mA 2.4 0.55 V CIN Input pin capacitance CXTAL XTAL pins capacitance COUT O utput pin capacitance 6 LPIN Pin Inductance 7 nH 70 °C TA Ambient Temperature 5 13.5 18.0 No airflow 0 204 22.5 pF PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Buffer Specifications Buffe r Name VDD Range (V) Impe dance (Ω ) Buffe r Type CPU 2.375 - 2.625 13.5 - 45 Type 1 APIC 2.375 - 2.625 9 - 30 Type 2 48MHz, REF 3.135 - 3.465 20 - 60 Type 3 PCI 3.135 - 3.465 12 - 55 Type 4 Type 1: CPU Clock Buffers (2.5V) Symbol Parame te rs Conditions M in. IOHMIN Pull- up current VOUT = 1.0V - 27 IOHMAX Pull- up current VOUT = 2.375V IOLMIN Pull- down current VOUT = 1.2V IOLMAX Pull- down current VOUT = 0.3V Typ. M ax. - 27 27 Units mA 30 tRH 2.5V Type 1 output rise edge rate 2.5V + /- 5% @ 0.4V- 2.0V 1 4 tFH 2.5V Type 1 output fall edge rate 2.5V + /- 5% @ 2.0V- 0.4V 1 4 V/ns Type 2: APIC Buffers (2.5V) Symbol Parame te rs Conditions M in. IOHMIN Pull- up current VOUT = 1.4V - 36 IOHMAX Pull- up current VOUT = 2.5V IOLMIN Pull- down current VOUT = 1.0V IOLMAX Pull- down current VOUT = 0.2V tRH 2.5V Type 2 output rise edge rate 2.5V ±5% @0.4V- 2.0V Typ. M ax. - 21 36 Units mA 31 1 4 V/ns tFH 2.5V Type 2 output fall edge rate 2.5V ±5% @2.0V- 0.4V 1 4 Type 3: 48MHz, REF Buffers (3.3V) Symbol Parame te rs Conditions M in. IOHMIN Pull- up current VOUT = 1.0V - 29 IOHMAX Pull- up current VOUT = 3.135V IOLMIN Pull- down current VOUT = 1.95V IOLMAX Pull- down current VOUT = 0.4V tRH 3.3V Type 3 output rise edge rate 3.3V ±5% @0.4V- 2.4V Typ. M ax. - 23 29 Units mA 27 0.5 2 V/ns tFH 3.3V Type 3 output fall edge rate 3.3V ±5% @2.4V- 0.4V 205 0.5 2 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Type 4: PCI Clock Buffers (3.3V) Symbol Parame te rs Conditions M in. IOHMIN Pull- up current VOUT = 1.0V - 33 IOHMAX Pull- up current VOUT = 3.135V IOLMIN Pull- down current VOUT = 1.95V IOLMAX Pull- down current VOUT = 0.4V tRH 3.3V Type 4 output rise edge rate 3.3V ±5% @ 0.4V- 2.4V Typ. M ax. - 33 30 Units mA 38 1 4 V/ns tFH 3.3V Type 4 output fall edge rate 3.3V ±5% @ 2.4V- 0.4V 1 4 AC Timing Figure 1. Hos t Clock to PCI CLK Offs e t 66 M Hz Parame te rs 100 M Hz M in. M ax. M in. M ax. 15.5 10.0 10.5 tHKP (2.5V) Host CLK period 15.0 tHKH (2.5V) Host CLK high time 5.2 3.0 tHKL (2.5V) Host CLK low time 5.0 2.8 tHRISE (2.5V) Host CLK rise time 0.4 1.6 0.4 1.6 tHFALL (2.5V) Host CLK fall time 0.4 1.6 0.4 1.6 tJITTER (2.5V) Host CLK Jitter Duty Cycle (2.5V) tHSKW (2.5V) tIOSKW 250 Measured at 1.25V 45 55 45 ns 250 ps 55 % Host Bus CLK Skew 175 175 IO APIC Bus CLK Skew 250 250 tPZL, tPZH Output enable delay 1.0 8.0 1.0 8.0 tPLZ, tPHZ Output disable delay 1.0 8.0 1.0 8.0 tHSTB Host CLK Stabilization from power- up tPKP PCI CLK period tPKPS PCI CLK period stability tPKH PCI CLK high time 12.0 12.0 tPKL PCI CLK low time 12.0 12.0 tPSKW tHPOFFSET tPSTB 3 30.0 ∝ 30.0 500 PCI Bus CLK Skew 500 Host to PCI Clock Offset 1.5 PCI CLK Stabilization from power- up 206 4.0 3 1.5 Units ps ns 3 ms ∝ ns 500 ps ns 500 ps 4.0 ns 3 ms PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2.5V 1.25V 1.25V Host CLK V SS t HSKW 2.5V 1.25V 1.25V Host CLK V t HPOFFSET SS t HPOFFSET 3.3V 1.5V 1.5V PCI CLK V SS t PSKW 3.3V 1.5V PCI CLK V SS Figure 1. Host Clock to PCI CLK Offset Test Point Output Buffer Test Load tHKP Duty Cycle tHKH 2.5V 2.0 Clocking 1.25 Interface 0.4 tHKL tHrise tHfall tPKP tPKH 3.3V Clocking Interface (TTL) 2.4 1.5 0.4 tPKL tPrise tPfall Figure 2. Clock Output Waveforms 207 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Minimum and Maximum Expected Capacitive Loads Clock M in. Load M ax. Load Units CPU Clocks (HCLK ) 10 20 1 device load, possible 2 loads PCI Clocks (PCLK ) 30 30 Meets PCI 2.1 requirements 48 MHz Clock 10 20 REF 10 20 1 device load APIC 10 20 2 device loads pF Note s 1 device load Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500W resistor in parallel. Design Guidelines to Reduce EMI 1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of vias of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors. PI6C100 CPUCLK 4 33 Ω 1 Device load CL PCICLK 8 33 Ω Meets PCI2.1 Req. CL REF 3 22 Ω/33Ω 1 Device load CL APIC 2 33 Ω 2 Device loads CL 48MHZ 2 22 Ω 1 Device load CL 208 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PCB Layout Suggestion C11 VDD 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 VSS 12 37 VDD 13 36 14 35 15 34 VSS 16 33 VDD 17 32 VSS VSS 18 31 VDD 19 30 VSS 20 29 VDD 21 28 22 27 23 26 24 25 FB1 C2 VSS VCC C1 VSS C10 VDD FB2 VCC (CPU) VSS C12 22uF C3 VDD VSS C4 VDD C5 C6 VSS Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C2-C11 should be placed as close as possible to their respective VDD. C9 VDD 22uF C8 C7 Via to VDD Plane Via to GND Plane Void in Power Plane Recommended capacitor values: C2-C11 .............. 0.1µF, ceramic C1, C12 ........... 22µF 209 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 48-Pin SSOP Package Data 48 Gauge Plane .395 .291 .420 .299 7.39 10.03 7.59 10.67 .010 0.25 .02 .04 0.51 1.01 .015 0.381 x 45˚ .025 0.635 1 .620 .630 15.75 16.00 .008 0.20 Nom. .110 2.79 Max 0-8˚ .008 .0135 0.20 0.34 .025 BSC 0.635 .008 0.20 .016 0.40 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Table of Dimensions Body E (Width) D (Le ngth) A (He ight) e (Pin-to-Pin pitch) 48 pins Min. 0.291 0.620 0.095 0.025 (300 mil) Max. 0.299 0.630 0.110 - Ordering Information P/N D e s cription PI6C100V 48- pin SSO P Package Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 210 PS8142A 10/13/98