PI6C182 Precision 1-10 Clock Buffer Features Description • Low noise non-inverting 1-10 buffer Pericom Semiconductor’s PI6C clock series is produced using the company’s advanced submicron CMOS technology, achieving industry leading speed. • Supports frequency up to 125 MHz (PI6C182A) The PI6C182 is a high-speed low-noise 1-10 noninverting buffer designed for SDRAM clock buffer applications, supports frequencies up to 110 MHz. • Supports up to four SDRAM DIMMs • Low skew (<200ps) between any two output clocks • I2C Serial Configuration interface At power up all SDRAM output are enabled and active. The I2C Serial control may be used to individually activate/deactivate any of the 10 output drivers. • Multiple VDD, VSS pins for noise reduction • 3.3V power supply voltage The output enable (OE) pin may be pulled low to Hi-Z state all outputs. • Separate Hi-Z state pin for testing • Packaging: -28-pin SSOP (H) Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips. Diagram Pin Configuration SDRAM0 SDRAM1 BUF_IN SDRAM2 SDRAM3 SDRAM9 OE SDATA SCLOCK I2C I/O 1 VDD0 1 28 VDD5 SDRAM0 2 27 SDRAM7 SDRAM1 3 26 SDRAM6 VSS0 4 25 VSS5 VDD1 5 24 VDD4 SDRAM2 6 23 SDRAM5 SDRAM3 7 22 SDRAM4 VSS1 8 21 VSS4 BUF_IN 9 20 OE VDD2 10 19 VDD3 SDRAM8 11 18 SDRAM9 VSS2 12 17 VSS3 VDDIIC 13 16 VSSIIC SDATA 14 15 SCLOCK PS8165D 07/19/04 PI6C182 Precision 1-10 Clock Buffer Pin Description Pin Symbol Type Qty Description 2, 3, 6, 7 SDRAM[0-3] O 4 SDRAM Byte 0 clock output 22, 23, 26, 27 SDRAM[4-7] O 4 SDRAM Byte 1 clock output 11, 18 SDRAM[8-9] O 2 SDRAM Byte 2 clock output 9 BUF_IN I 1 Input for 1-20 buffer 20 OE I 1 Hi-Z states all outputs when held LOW. Has a >100kΩ internal pull-up resistor. 14 SDATA I/O 1 Data pin for I2C curcuitry. Has a >100kΩ internal pull-up resistor. 15 SCLOCK I/O 1 Clock pin I2C circuitry. Has a >100kΩ internal pull-up resistor. 1, 5, 10, 19, 24, 28 VDD[0-5] Power 6 3.3V power supply for SDRAM buffer 4, 8, 12, 17, 21, 25 VSS[0-5] Ground 6 Ground for SDRAM buffers 13 VDDIIC Power 1 3.3V power supply for I2C circuitry 16 VSSIIC Ground 1 Ground for I2C circuitry Serial Configuration Map OE Functionality OE SDRAM[0-9] Notes 0 Hi-Z 1 1 BUF_IN 2 Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Notes: 1. Used for test purposes only 2. Buffers are non-inverting I2C Address Assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 0 Pin Description 7 NC (Initialize to 0) 6 NC (Initialize to 0) 5 NC (Initialize to 0) 4 NC (Initialize to 0) 3 7 SDRAM3 (Active/Inactive) 2 6 SDRAM2 (Active/Inactive) 1 3 SDRAM1 (Active/Inactive) 0 2 SDRAM0 (Active/Inactive) Note: 1. Inactive means outputs are held LOW and are disabled from switching 2 PS8165D 07/19/04 PI6C182 Precision 1-10 Clock Buffer 2-Wire I2C Control The I2C interface permits individual enable/disable of each clock output and test mode enable. a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the device’s own address is detected, PI6C182 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. The PI6C182 is a slave receiver device. It can not be read back. Sub addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every byte put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SCLOCK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLOCK is HIGH indicates a “start” condition. A LOW to HIGH transition on SDATA while SCLOCK is HIGH is a “stop” condition and indicates the end of a data transfer cycle. Following acknowledgement of the address byte (D2), two more bytes must be sent: 1. “Command Code” byte 2. “Byte Count” byte. Although the data bits on these two bytes are “don’t care,” they must be sent and acknowledged. Each data transfer is initiated with a start condition and ended with Byte2: Optional Register for Possible Future Byte1: SDRAM Active/Inactive Register Requirements (1 = enable, 0 = disable) (1 = enable, 0 = disable) Bit Pin Description SDRAM7 (Active/Inactive) 7 18 SDRAM9 (Active/Inactive) 26 SDRAM6 (Active/Inactive) 6 11 SDRAM8 (Active/Inactive) 5 23 SDRAM5 (Active/Inactive) 5 (Reserved) 4 22 SDRAM4 (Active/Inactive) 4 (Reserved) 3 NC (Initialize to 0) 3 (Reserved) 2 NC (Initialize to 0) 2 (Reserved) 1 NC (Initialize to 0) 1 (Reserved) 0 NC (Initialize to 0) 0 (Reserved) Bit Pin Description 7 27 6 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature............................................................–65°C to +150°C Ambient Temperature with Power Applied.............................–0°C to +70°C 3.3V Supply Voltage to Ground Potential ..............................–0.5V to +4.6V DC Input Voltage....................................................................–0.5V to +4.6V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Supply Current (VDD = +3.465V, CLOAD = Max.) Symbol Parameter IDD IDD IDD IDD Test Condidtion BUF_IN = 0 MHz Supply Current Min. Typ. Max. 2 BUF_IN = 66.66 MHz 180 BUF_IN = 100.00 MHz 240 BUF_IN = 133.00 MHz 360 3 Units PS8165D mA 07/19/04 PI6C182 Precision 1-10 Clock Buffer DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C) Symbol Parameter Test Conditions Min. Typ. Max. Units 2.0 VDD +0.3 V VSS -0.3 0.8 0 < VIN < VDD -5 5 2.4 Input Voltage VIH Input High voltage VIL Input Low voltage IIL Input leakage current VDD mA VDD [0-9] = 3.3V ±5% VOH Output High voltage IOH = -1mA V VOL Output Low voltage IOL = 1mA COUT Output pin capacitance 6 CIN Input pin capacitance 5 LPIN Pin Inductance TA Ambient Temperature 0.4 pF 7 No Airflow nH 0 70 °C SDRAM Clock Buffer Operating Specification Symbol Parameter Test Conditions IOHMIN Pull-up current VOUT = 2.0V IOHMAX Pull-up current VOUT = 3.135V IOLMIN Pull-down current VOUT = 1.0V IOLMAX Pull-down current VOUT = 0.4V Min. Typ. Max. Units -40 36 40 mA 38 AC Timing Symbol Parameter 66 MHz 100 MHz 125MHz Min. Max. Min. Max. Min. Max. tSDRISE SDRAM CLK rise time 1.5 4.0 1.5 4.0 1.5 4.0 tSDFALL SDRAM CLK fall time 1.5 4.0 1.5 4.0 1.5 4.0 tPLH SDRAM Buffer LH prop delay 1.0 5.5 1.0 5.5 1.0 5.5 tPHL SDRAM Buffer HL prop delay 1.0 5.5 1.0 5.5 1.0 5.5 tPZL, tPZH SDRAM Buffer Enable 1.0 8.0 1.0 8.0 1.0 8.0 delay(1) Units V/ns ns tPLZ, tPHZ SDRAM Buffer DIsable delay(1) 1.0 8.0 1.0 8.0 1.0 8.0 Duty Cycle Measured at 1.5V 45 55 45 55 45 55 % tSDSKW SDRAM Output-to-Output skew 200 ps 250 250 Note: 1. This Parameter specified at 5MHz input frequency. 4 PS8165D 07/19/04 PI6C182 Precision 1-10 Clock Buffer Test Point Output Buffer Test Load tSDKP tSDKH 3.3V Clocking Interface (TTL) 2.4 1.5 0.4 tSDKL tSDRISE Input Waveform tSDFALL 1.5V 1.5V tplh tphl Output Waveform 1.5V 1.5V Figure 1. Clock Waveforms Design Guidelines to Reduce EMI Minimum and Maximum Expected Capacitive Loads Clock Min. Max. Units SDRAM 20 30 pF 1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of “vias” of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors. Notes SDRAM DIMM Specificaion Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load. 2. Minimum rise/fall times are guaranteed at minimum specified load. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500Ω resistor in parallel. 5 PS8165D 07/19/04 PI6C182 Precision 1-10 Clock Buffer PCB Layout Suggestion C1 C7 1 28 2 27 3 26 VSS 4 25 VSS VDD 5 24 VDD 6 23 7 22 8 21 9 20 10 19 11 18 VSS 12 17 VSS VDD 13 16 VSS 14 15 VDD C2 VSS C3 VDD C4 VDD Ferrite Bead VCC C8 C6 22uF VSS C5 VDD Via to GND Plane Via to VDD Plane Void in Power Plane Note: 1. This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. 2. As a general rule, C1-C7 should be placed as close as possible to their respective VDD. 3. Recommended capacitor values: C1-C7 = 0.1μF, ceramic C8 = 22μF PI6C182 Clock from Chipset SDRAM 10 RS CL SDRAM DIMM Spec. Figure 2. Design Guidelines 6 PS8165D 07/19/04 PI6C182 Precision 1-10 Clock Buffer Packaging Mechanical: 28-Pin SSOP (H) Ordering Information Ordering Code Package Code Package Type PI6C182H H 110 MHz 28-pin SSOP PI6C182AH H 125 MHz 28-pin SSOP Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 7 PS8165D 07/19/04