PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Product Features Description • Dual differential 3.3V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range: 53.33MHz to 366.67MHz • Crystal input frequency range: 14MHz to 40MHz • TEST_CLK freqeuncy range: 10MHz to 50MHz • VCO range: 320MHz to 1.1GHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter: 3ps (typical) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Packages (Pb-free & Green available): - 32-pin LQFP (FB) The PI6C484321 is a dual output, 3.3V LVPECL Frequency Synthesizer using crystal as the input source. The input source is can be selected from either LVTTL/LVCMOS level input (TEST_CLK pin) or crystal inputs. The VCO operates at a frequency range of 320MHz to 1.1GHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed through a simple 2-wire serial interface or through 11-bit parallel interface. The low phase noise characteristics of the PI6C484321 make it an ideal clock source for Fibre Channel 1 (FC1), Fibre Channel 2 (FC2), 10 Gigabit Fibre Channel (10GFC), Gigabit Ethernet and 10 Gigabit Ethernet (10GbE) applications. Pin Configuration Block Diagram VCO_SEL XTAL1 nP_LOAD M0 M1 32 31 30 29 28 27 26 25 XTAL2 PLL PHASE DETECTOR MR VCO ?÷M 0 1 FOUT0 nFOUT0 FOUT1 nFOUT1 XTAL2 2 23 TEST_CLK M7 3 22 XTAL_SEL M8 4 21 VCCA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK VEE 8 17 MR 9 10 11 12 13 14 15 16 VEE nFOUT0 FOUT0 VCCO nFOUT1 M0:M8 24 M6 FOUT1 TEST 1 VCC CONFIGURATION INTERFACE LOGIC ÷3 ÷4 ÷5 ÷6 M5 TEST S_LOAD S_DATA S_CLOCK nP_LOAD M2 1 M3 OSC M4 0 XTAL1 VCO_SEL XTAL_SEL TEST_CLK N0:N1 1 PS8765A 08/01/05 PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Functional Description The following functional description describes operations using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. M divider is defined as follows: fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B to program the VCO Frequency Function Table. The output frequency is defined as follows: The PI6C484321 features a fully integrated PLL, thus requires no external components for setting the loop bandwidth. A fundamental crystal is the input to the internal oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz reference frequency to the phase detector. The actual VCO range of the PLL is 320MHz to 1.1GHz. The output of the M divider is used by the phase detector. fOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some illegal values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable feature that selects the M divider and N output divider supports two modes: parallel and serial modes. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the TEST Output T1 T0 0 0 LOW 0 1 S_Data 1 0 Output of M divider 1 1 CMOS Fout SERIAL LOADING S_CLOCK S_DATA T1 t S S_LOAD T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 t H nP_LOAD t S PARALLEL LOADING M0:M8, N0:N1 M, N nP_LOAD t S t H Time Parallel & Serial Load Operations 2 PS8765A 08/01/05 PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Pin Description Number Name Type Description 1 M5 Input Pullup 2, 3, 4, 28, 29, 30, 31, 32 M6, M7, M8, M0, M1, M2, M3, M4 Input Pulldown 5, 6 N0, N1 Input Pulldown 7 nc unused No connect 8, 16 VEE Power Negative supply pins 9 TEST Output Test output. ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS interface levels 10 VCC Power Positive supply pin 11, 12 FOUT1, nFOUT2 Output Differential output for the synthesizer. LVPECL interface levels 13 VCCO Power Output supply pin 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. LVPECL interface levels M divider input. Data latched on LOW-to-HIGH transition of nP_ LOAD input. LVCMOS / LVTTL interface levels Determines N output divider value as defined in Table 3C Function table. LVCMOS / LVTTL interface levels 17 MR Input Pulldown Active High Master reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. 18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. 19 S_DATA Input Pulldown Shirft register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. 20 S_LOAD Input Pulldown Control transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels 21 VCCA Power 22 XTAL_SEL Input Pullup 23 TEST_CLK Input Pulldown 24, 25 XTAL1, XTAL2 Input 26 nP_LOAD Input Pulldown 27 VCO_SEL Input Pullup Notes 1. Analog supply pin Selects between crystals or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. Test clock input. LVCMOS / LVTTL interface levels Crystal oscillator inputs Parallel load input to determine when data present at M8:M0 is loaded into M divider, and when data is present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Controls the clock synthesizer to be in PLL or bypass mode. LVCMOS /LVTTL interface levels Pullup and Pulldown refer to internal input resistors. See Pin characterstics Table for typical values. 3 PS8765A 08/01/05 PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Pin Characteristics Symbol Parameter Min. Typ. CIN Input capacitance 4 RPULLUP Input Pullup resistor 51 RPULLDOWN Input Pulldown resistor 51 Max. Units pF kΩ Parallel and Serial Modes Function Table Inputs nP_LOAD M N S_LOAD H X X X X X X Reset mode, forces outputs LOW. L L Data Data X X X Data on M and N input passed directly to the M divider. TEST output forced LOW L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs L H X X L ↑ Data Serial input mode. Shift register is loaded with data on S-DATA on each rising edge of S_CLOCK L H X X ↑ L Data Contents of the shift register are passed to the M divider L H X X ↓ L Data M divider and N output divider values are latched L H X X L X X Parallel or serial input do not affect shift registers L H X X Notes: S_CLOCK S_DATA Conditions MR H ↑ Data S_Data passed directly to M divider as it is clocked L = Low, H = High, X = Don't care, ↑ = Rising Edge, and ↓ = Falling edge Transition Programmable VCO Frequency Example Based On 25MHz input 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 25 0 0 0 0 1 1 0 0 1 650 26 0 0 0 0 1 1 0 1 0 675 27 0 0 0 0 1 1 0 1 1 775 31 0 0 0 0 1 1 1 1 1 VCO Freq. M Divider 625 Programmable Output Divider FunctionTable Inputs N1 N0 N Divider Value 0 0 0 Output Frequency (MHz) Min. Max. 3 106.67 366.67 1 4 80 275 1 0 5 64 220 1 1 6 53.33 183.33 Notes: Fout_min = Fvco_min / N = 320MHz / N Fout_max = Fvco_max /N = 1100MHz / N 4 PS8765A 08/01/05 PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Absolute Maximum Ratings Supply voltage, VCC ............................................................ 4.6V Inputs, VI .................................................... -0.5V to VCC + 0.5V Outputs, VO (LVPECL)............................-0.5V to VDDO + 0.5V Outputs, IO (LVCMOS) Continuous current .......................................................... 50mA Surge current ................................................................. 100mA Package Thermal Impedance, Theta JA ......... 47.9ºC/W (0 lfpm) Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may effect product reliability. Storage Temperature, TSTG ................................-65º C to 150ºC Commonly Used Configuration Function Table Input Output Frequency (MHz) Crystal (MHz) M Divider Value N Divider Value 19.44 32 4 155.52 19.53125 32 4 156.25 25 25 4 156.25 25 25 5 125 25.50 25 3 212.50 25.50 25 4 159.375 25.50 25 6 106.25 38.88 16 4 155.52 20 75 20 83.33 5 PS8765A 08/01/05 PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer LVCMOS / LVTTL DC Characteristics, VCC = VCCA = VCCO = 3.3V ±5%, TA = 0°C to 70°C Symbol VIH Parameter Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Min. Typ. Max. VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 2 VCC +0.3V TEST_CLK 2 VCC +0.3V VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 -0.3 0.8 TEST_CLK -0.3 1.3 M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD VCC = VIN = 3.465V 150 M5, XTAL_SEL, VCO_SEL VCC = VIN = 3.465V 5 VCC = 3.465V, VIN = 0V -5 M5, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 Output High Voltage TEST(1) VOL Output Low Voltage TEST(1) Units V µA M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD VOH Notes 1. Test Condition 2.6 0.5 V Outputs terminated with 50Ω to VCC/2. See Parameters Measurement Information table, 3.3V Output Load Test Circuit Figure. Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V ±5%, TA = 0°C to 70°C Symbol Parameter Min. Typ. Max. VCC Positive supply voltage 3.135 3.3 3.465 VCCA Analog supply voltage 3.135 3.3 3.465 VCCO Output supply voltage 3.135 3.3 3.465 IEE Power supply current 180 ICCA Analog supply current 30 Units V mA LVPECL DC Characteristics, VCC = VCCA = VCCO = 3.3V ±5%, TA = 0°C to 70°C Symbol Parameter VOH Output high VOL Output low VSWING Notes 1. Test Condition voltage(1) voltage(1) Peak-to-Peak output voltage swing Min. Typ. Max. VCCO - 1.4 VCCO -1.0 VCCO -2.0 VCCO -1.7 0.6 1.0 Units V Outputs terminated with 50Ω to VCC -2V. See Parameter Measurement Section, 3.3V output load test circuit. 6 PS8765A 08/01/05 PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Input Frequency Characteristics, VCC = VCCA = VCCO = 3.3V±5%, TA 0°C to 70°C Symbol Parameter Test Condition Min. TEST_CLK (1) fIN Input Frequency XTAL, XTAL2(1) Typ. Max. 14 40 14 40 S_CLOCK Notes 1. Units MHz 50 For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate with in the 200MHz to 700MHz range. Using minimum input frequency of 12MHz, valid values of M are 17 ≤ M ≤ 58. Using the maximun frequency of 25MHz, valid values of M are 8 ≤ M ≤ 28. Crystal Characteristics Parameter Test Condition Min. Max. Units 40 MHz Equivalent Series resistance (ESR) 50 Ω Shunt Capacitance 7 pF Mode of Oscillation Typ. Fundamental Frequency 14 AC Characteristics, VCC = VCCA = VCCO = 3.3V ±5%, TA = 0°C to 70°C Symbol FOUT tjit(per) tsk(o) Parameter Test Condition Output frequency Period jitter, Min. Typ. 103.3 RMS(1, 3) 3 Output skew(2, 3) Max. Units 260 MHz 5 ps 15 ps tR Output rise time 20% to 80% 200 700 tF Output fall time 20% to 80% 200 700 tS tH Setup time Hold time Mx, Nx to nP_LOAD 5 S_DATA to S_CLOCK 5 S_CLOCK to S_LOAD 5 Mx, Nx to nP_LOAD 5 S_DATA to S_CLOCK 5 S_CLOCK to S_LOAD 5 45 odc tLOCK PLL lock time ps ns 55 % 1 ms Notes: 1. Jitter performance using XTAL inputs. 2. Defined as skew between outputs with the same supply voltage and with equal load conditions. Measured at the output differential cross points. 3. This parameter is defined in accordance with JEDEC standard 65 7 PS8765A 08/01/05 PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Paramater Measurement Information 2V VCC, VCCA, VCCO Qx SCOPE nFOUTx FOUTx LVPECL nFOUTy nQx VEE FOUTy tsk(o) -1.3V ± 0.165V 3.3V Output Load Test Circuit Output Skew VOH nFOUTx FOUTx VREF 1 2 3 4 6 Pulse Width t VOL contains 68.26% of all measurements contains 95.4% of all measurements contains 99.73% of all measurements contains 99.99366% of all measurements contains (100-1.973x10-7)% of all measurements odc = t PW t PERIOD Histogram Reference Point PERIOD Mean Period (Trigger Edge) (First edge after trigger) Period Jitter Output Duty Cycle/Pulse Width/Period 80% 80% VSW I N G Clock Outputs 20% 20% tF tR Output Rise/Fall Time 8 PS8765A 08/01/05 PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Packaging Mechanical: 32-pin LQFP (FB) 9.00 BSC .354 Square Square 7.00 BSC 0.09 0.20 .004 .008 GAUGE PLANE 0.25 mm .276 1.60 Max. .063 0° 7° 0.45 .018 0.75 .030 1.00 REF .039 .004 0.10 Seating Plane 0.30 .012 0.45 .018 0.80 BSC .032 0.05 0.15 .002 .006 1.35 1.45 .053 .057 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Ordering Code Package Code PackageType PI6C484321FB FB 32-Pin LQFP PI6C484321FBE FB Pb-free & Green, 32-Pin LQFP Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/ Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com 9 PS8765A 08/01/05