PERICOM PI74FCT651T

PI74FCT646/648/651/652T
(25Ω
Ω Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
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PI74FCT646T/648T/651T/652T
Ω Series PI74FCT2646T/2652T
(25Ω
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Fast CMOS Octal Registered Transceivers
Product Features:
Product Description:
• PI74FCT646T/648T/651T/652T/2646T/2652T is pin compatible
with bipolar FAST™ Series at a higher speed and lower power
consumption
• 25Ω series resistor on all outputs (FCT2XXX only)
• TTL input and output levels
• Low ground bounce outputs
• Extremely low static power
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Packages available:
– 24-pin 300 mil wide plastic DIP (P)
– 24-pin 150 mil wide plastic QSOP (Q)
– 24-pin 150 mil wide plastic TQSOP (R)
– 24-pin 300 mil wide plastic SOIC (S)
• Device models available upon request
Pericom Semiconductor’s PI74FCT series of logic circuits are
produced in the Company’s advanced 0.6/0.8 micron CMOS
technology, achieving industry leading speed grades. All
PI74FCT2XXX devices have a built-in 25-ohm series resistor on
all outputs to reduce noise because of reflections, thus eliminating
the need for an external terminating resistor.
The PI74FCT646T/648T/651T/652T and PI74FCT2646T/2652T
are designed with a bus transceiver with 3-state D-type flip-flops
and control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage registers. The
PI74FCT651/652T/2652T utilize GAB and GBA signals to control
the transceiver functions. The PI74FCT646/2646T/648T utilize
the enable control (G) and direction pins (DIR) to control the
transceiver functions. SAB and SBA control pins are used to select
either real-time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in a
multiplexer during the transition between real-time and stored data.
A low input level selects real-time data and a high selects stored
data.
The PI74FCT646T is a non-inverting option of the PI74FCT648T.
The PI74FCT652T is a non-inverting option of the PI74FCT651T.
Logic Block Diagram
PI74FCT651/652 ONLY
GBA
GAB
PI74FCT646/648
ONLY
G
DIR
CPBA
SBA
CPAB
SAB
B REG
1 OR 8 CHANNELS
0D
C0
B0
A REG
A0
0D
PI74FCT651/652 ONLY
646/652
ONLY
C0
646/652
ONLY
TO 7 OTHER CHANNELS
1
PS2022A 03/11/96
PI74FCT646/648/651/652T
(25Ω
Ω Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT646/648T
Product Pin Configuration
PI74FCT651/652T
Product Pin Configuration
CPAB
1
24
Vcc
CPBA
SAB
2
23
CPBA
SBA
GAB
3
22
SBA
G
A0
4
21
GBA
20
B0
A1
5
19
B1
A2
6
18
B2
A3
7
17
B3
A4
8
16
B4
A5
9
10
15
B5
A6
A7
11
14
B6
GND
12
13
B7
CPAB
1
24
Vcc
SAB
2
23
DIR
3
22
A0
4
21
A1
5
A2
6
A3
7
A4
8
A5
9
A6
24-PIN
P24
Q24
R24
S24
24-PIN
P24
Q24
R24
S24
20
B0
19
B1
18
B2
17
B3
16
B4
10
15
B5
A7
11
14
B6
GND
12
13
B7
Product Pin Description
Pin Name
A0-A7
B0-B7
CPAB, CPBA
SAB, SBA
DIR, G
GAB, GBA
GND
VCC
Description
Data Register A Inputs
Data Register B Outputs
Data Register B Inputs
Data Register A Outputs
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs
(646/648/2646)
Output Enable Inputs
(651/652/2652)
Ground
Power
PI74FCT646/648/2646T Truth Table
PI74FCT646/2646T
Function/Operation
Isolation
Store A and B Data
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
PI74FCT648T
Function/Operation
Isolation
Store A and B Data
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
DATA I/O(2)
Inputs
G
H
H
L
L
L
L
DIR
X
X
L
L
H
H
CPAB CPBA SAB
H or L H or L X
↑
↑
X
X
X
X
X
H or L X
X
X
L
H or L
X
H
SBA
X
X
L
H
X
X
A0-A7
Input
B0-B7
Input
Output
Input
Input
Output
PI74FCT651/652/2652T Truth Table
PI74FCT651T
Function/Operation
Isolation
Store A and B Data
Store A, Hold B
Store A in Both Registers(3)
Hold A, Store B
Store B in Both Registers(4)
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored B Data to A Bus
1.
2.
3.
4.
PI74FCT652/2652T
Function/Operation
GAB
Isolation
L
Store A and B Data
L
Store A, Hold B
X
Store A in Both Registers
H
Hold A, Store B
L
Store B in Both Registers
L
Real Time B Data to A Bus
L
Stored B Data to A Bus
L
Real Time A Data to B Bus
H
Stored A Data to B Bus
H
Stored A Data to B Bus and
H
Stored B Data to A Bus
DATA I/O(2)
Inputs
GBA
H
H
H
H
X
L
L
L
H
H
L
CPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
CPBA SAB
H or L X
↑
X
H or L X
↑
X(2)
↑
X
↑
X
X
X
H or L X
X
L
X
H
H or L H
SBA A0-A7
B0-B7
X
Input
Input
X
X
Input Unspecified(1)
X
Input
Output
(1)
X Unspecified
Input
X(2) Output
Input
L
Output
Input
H
X
Input
Output
X
H
Output
Output
The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data
input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition
on the clock inputs.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
A in B Register
B in A Register
2
PS2022A 03/11/96
PI74FCT646/648/651/652T
(25Ω
Ω Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
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REAL-TIME TRANSFER
BUS A TO B
REAL-TIME TRANSFER
BUS B TO A
BUS
BUS
BUS
BUS
A
B
A
B
G
L
CPAB CPBA
X
X
SAB
X
SBA
L
646/648/
2646
CPAB CPBA
X
X
SAB
L
SBA
X
651/652/ GAB GBA CPAB CPBA
2652
L
L
X
X
SAB
X
SBA
L
651/652/ GAB GBA CPAB CPBA
2652
H
H
X
X
SAB
L
SBA
X
CPAB CPBA
X
H or L
H or L
X
SAB
X
H
SBA
H
X
651/652/ GAB GBA CPAB CPBA
2652
H
L H or L H or L
SAB
H
SBA
H
646/648/
2646
DIR
L
DIR
H
STORAGE FROM
A AND/OR B
G
L
TRANSFER STORES
DATA TO A AND/OR B
BUS
BUS
BUS
BUS
A
B
A
B
G
L
L
H
CPAB CPBA
↑
X
X
↑
↑
↑
SAB
X
X
X
SBA
X
X
X
651/652/ GAB GBA CPAB CPBA
2652
X
H
↑
X
L
X
X
↑
L
H
↑
↑
SAB
X
X
X
SBA
X
X
X
646/648/
2646
DIR
H
L
X
646/648(1) DIR
2646
L
H
G
L
L
1. Note: The FCT646/2646 cannot transfer data to
A bus and B bus simultaneously.
3
PS2022A 03/11/96
PI74FCT646/648/651/652T
(25Ω
Ω Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................................. –65°C to +150°C
Ambient Temperature with Power Applied ................................. -40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ....... –0.5V to +7.0V
DC Input Voltage ......................................................................... –0.5V to +7.0V
DC Output Current ................................................................................... 120 mA
Power Dissipation ......................................................................................... 0.5W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 5%)
Parameters Description
Test Conditions(1)
Min. Typ(2) Max. Units
VOH
Output HIGH Voltage
VCC = Min., VIN = VIH or VIL
IOH = –15.0 mA
2.4
3.0
V
VOL
Output LOW Current
VCC = Min., VIN = VIH or VIL
IOL = 64 mA
0.3
0.55
V
VOL
Output LOW Current
VCC = Min., VIN = VIH or VIL
IOL = 12 mA (25Ω Series)
0.3
0.50
V
VIH
Input HIGH Voltage
Guaranteed Logic HIGH Level
VIL
Input LOW Voltage
Guaranteed Logic LOW Level
IIH
Input HIGH Current
VCC = Max.
IIL
Input LOW Current
IOZH
High Impedance
IOZL
Output Current
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18 mA
IOFF
Power Down Disable
VCC = GND, VOUT = 4.5V
IOS
Short Circuit Current
VCC = Max.(3), VOUT = GND
VH
Input Hysteresis
2.0
V
0.8
V
VIN = VCC
1
µA
VCC = Max.
VIN = GND
–1
µA
VCC = MAX.
VOUT = 2.7V
1
µA
VOUT = 0.5V
–1
µA
–0.7
–1.2
V
—
—
100
µA
–60
–120
mA
200
mV
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(4)
Description
Test Conditions
Typ
Max.
Units
CIN
Input Capacitance
VIN = 0V
6
10
pF
COUT
Output Capacitance
VOUT = 0V
8
12
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
4
PS2022A 03/11/96
PI74FCT646/648/651/652T
(25Ω
Ω Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
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Power Supply Characteristics
Test Conditions(1)
Parameters Description
Min.
Typ(2)
Max.
Units
ICC
Quiescent Power
Supply Current
VCC = Max.
VIN = GND
or VCC
0.1
500
µA
∆ICC
Supply Current per
Input @ TTL HIGH
VCC = Max.,
VIN = 3.4V(3)
0.5
2.0
mA
ICCD
Supply Current per
Input per MHz(4)
VCC = Max.,
Outputs Open
G = DIR = GND or
GAB = GBA = GND
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
0.15
0.25
mA/
MHz
IC
Total Power Supply
Current(6)
VCC = Max.,
Outputs Open
fCP = 10 MHZ
50% Duty Cycle
G = DIR = GND or
GAB = GBA = GND
fI = 5 MHZ
One Bit Toggling
VCC = Max.,
Outputs Open
fCP = 10 MHZ
50% Duty Cycle
G = DIR = GND or
GAB = GBA = GND
Eight Bits Toggling
fI = 2.5 MHZ
50% Duty Cycle
VIN = VCC
VIN = GND
1.5
3.5(5)
mA
VIN = 3.4V
VIN = GND
2.0
5.5(5)
VIN = VCC
VIN = GND
3.8
7.3(5)
VIN = 3.4V
VIN = GND
6.0
16.3(5)
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
5
PS2022A 03/11/96
PI74FCT646/648/651/652T
(25Ω
Ω Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT646/2646T Switching Characteristics over Operating Range
646T/2646T
646AT/2646AT
Com.
Parameters
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
Description
Propagation Delay
Bus to Bus
Output Enable Time
G, DIR to Bus
Output Disable Time(3)
G, DIR to Bus
Propagation Delay
Clock to Bus
Propagation Delay
SBA or SAB to Bus
Setup Time HIGH or
LOW, BUS to Clock
Hold Time HIGH or
LOW, Bus to Clock
Clock Pulse Width(3)
HIGH or LOW
646CT
Com.
646DT
Com.
Com.
Conditions(1)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
CL = 50 pF
RL = 500Ω
2.0
7.5
2.0
6.3
1.5
5.4
1.5
4.8
ns
2.0
14.0
2.0
9.8
1.5
7.8
1.5
7.3
ns
2.0
9.0
2.0
6.3
1.5
6.3
1.5
6.3
ns
2.0
9.0
2.0
6.3
1.5
5.7
1.5
5.2
ns
2.0
9.5
2.0
7.7
1.5
6.2
1.5
5.8
ns
4.0
—
2.0
—
2.0
—
2.0
—
ns
2.0
—
1.5
—
1.5
—
1.5
—
ns
6.0
—
5.0
—
5.0
—
5.0
—
ns
PI74FCT648T Switching Characteristics over Operating Range
648T
648AT
Com.
Parameters
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
Description
Propagation Delay
Bus to Bus
Output Enable Time
G, DIR to Bus
Output Disable Time(3)
G, DIR to Bus
Propagation Delay
Clock to Bus
Propagation Delay
SBA or SAB to Bus
Setup Time HIGH or
LOW, BUS to Clock
Hold Time HIGH or
LOW, Bus to Clock
Clock Pulse Width(3)
HIGH or LOW
648CT
Com.
648DT
Com.
Com.
Conditions(1)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
CL = 50 pF
RL = 500Ω
2.0
7.5
2.0
6.3
1.5
5.4
1.5
4.8
ns
2.0
14.0
2.0
9.8
1.5
7.8
1.5
7.3
ns
2.0
9.0
2.0
6.3
1.5
6.3
1.5
6.3
ns
2.0
9.0
2.0
6.3
1.5
5.7
1.5
5.2
ns
2.0
9.5
2.0
7.7
1.5
6.2
1.5
5.8
ns
4.0
—
2.0
—
2.0
—
2.0
—
ns
2.0
—
1.5
—
1.5
—
1.5
—
ns
6.0
—
5.0
—
5.0
—
5.0
—
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter guaranteed but not production tested.
6
PS2022A 03/11/96
PI74FCT646/648/651/652T
(25Ω
Ω Series) P174FCT2646T/2652T
OCTAL REGISTERED TRANSCEIVERS
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT651T Switching Characteristics over Operating Range
Parameters
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
Description
Conditions
Propagation Delay
Bus to Bus
Output Enable Time
GBA, GAB to Bus
Output Disable Time(3)
GBA, GAB to Bus
Propagation Delay
Clock to Bus
Propagation Delay
SBA or SAB to Bus
Setup Time HIGH or
LOW, BUS to Clock
Hold Time HIGH or
LOW, Bus to Clock
Clock Pulse Width(3)
HIGH or LOW
CL = 50 pF
RL = 500Ω
(1)
651T
651AT
651CT
651DT
Com.
Com.
Com.
Com.
Min
Max
Min
Max
Min
Max
Min
Max
Unit
2.0
9.0
2.0
6.3
1.5
5.4
1.5
4.8
ns
2.0
12.5
2.0
9.8
1.5
7.8
1.5
7.3
ns
2.0
9.0
2.0
6.3
1.5
6.3
1.5
6.0
ns
2.0
9.0
2.0
6.3
1.5
5.7
1.5
5.2
ns
2.0
9.5
2.0
7.7
1.5
6.2
1.5
5.8
ns
4.0
—
2.0
—
2.0
—
2.0
—
ns
2.0
—
1.5
—
1.5
—
1.5
—
ns
6.0
—
5.0
—
5.0
—
5.0
—
ns
PI74FCT652/2652T Switching Characteristics over Operating Range
Parameters
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
Description
Conditions
Propagation Delay
Bus to Bus
Output Enable Time
GBA, GAB to Bus
Output Disable Time(3)
GBA, GAB to Bus
Propagation Delay
Clock to Bus
Propagation Delay
SBA or SAB to Bus
Setup Time HIGH or
LOW, BUS to Clock
Hold Time HIGH or
LOW, Bus to Clock
Clock Pulse Width(3)
HIGH or LOW
CL = 50 pF
RL = 500Ω
(1)
652T/2652T
652AT/2652AT
652CT
652DT
Com.
Com.
Com.
Com.
Min
Max
Min
Max
Min
Max
Min
Max
Unit
2.0
9.0
2.0
6.3
1.5
5.4
1.5
4.8
ns
2.0
12.5
2.0
9.8
1.5
7.8
1.5
7.3
ns
2.0
9.0
2.0
6.3
1.5
6.3
1.5
6.0
ns
2.0
9.0
2.0
6.3
1.5
5.7
1.5
5.2
ns
2.0
9.5
2.0
7.7
1.5
6.2
1.5
5.8
ns
4.0
—
2.0
—
2.0
—
2.0
—
ns
2.0
—
1.5
—
1.5
—
1.5
—
ns
6.0
—
5.0
—
5.0
—
5.0
—
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
7
PS2022A 03/11/96