PI74SSTVF16859 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 13-Bit to 26-Bit Registered Buffer Product Features Product Description • PI74 SSTVF16859 is designed for low-voltage operation, 2.5V for PC1600 ~ PC2700; 2.6V for PC3200 • Supports SSTL_2 Class I specifications on outputs • All Inputs are SSTL_2 Compatible, except RESET which is LVCMOS. • Designed for DDR Memory • Flow-Through Architecture • Packages: 64-pin, 240-mil wide plastic TSSOP (A) 56-pin, Plastic Very Thin Fine Pitch Quad Flat No Lead QFN (ZB) Pericom Semiconductor’s PI74SSTVF16859 logic circuit is produced using the Company’s advanced sub-micron CMOS technology, achieving industry leading speed. All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. The device operates from a differential clock (CLK and CLK). Data registered at the crossing of CLK going HIGH, and CLK going LOW. The PI74SSTVF16859 supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. Logic Block Diagram - TSSOP RESET D1 VREF 48 49 16 51 R V CLK CLK 35 45 CLK D To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power up. Q1A 32 In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of RESET, the register will become active quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock is stable, during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. Q1B TO 12 OTHER CHANNELS Logic Block Diagram - QFN RESET D1 VREF 35 36 7 38 R V CLK CLK 24 32 CLK D Q1A 22 Pericom’s PI74SSTVF16859 is characterized for operation from 0°C to 70°C. Q1B TO 12 OTHER CHANNELS Truth Table(1) Product Pin Description Pin Name Inputs De s cription Outputs RESET CLK CLK D Q L X or Floating X or Floating X or Floating L RESET Reset (Active Low) LVCMOS CLK Clock Input, Positive Differential Input CLK Clock Input, Negative Differential Input H ↑ ↓ H H D Data Input, D1- D13 Η ↑ ↓ L L Q Data Output, Q1- Q13 H L or H L or H X Q o( 2 ) GND Ground VDD Core Supply Voltage VDDQ Output Supply Voltage VREF Input Reference Voltage Notes: 1. H L ↑ ↓ X 1 = High Signal Level 2. Output level before the = Low Signal Level indicated steady state = Transition LOW-to-HIGH input conditions were = Transition HIGH-to-LOW established. = Irrelevant or floating PS8657 02/13/03 PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 VDDQ GND VDDQ Q13A Q12A Q11A Q10A VDDQ Product Pin Configurations 62 D13 Q10A 4 61 D12 Q7A 1 42 D10 Q9A 5 60 VDD Q6A 2 41 D9 VDDQ 6 59 VDDQ Q5A 3 40 D8 GND 7 58 GND Q4A 4 39 D7 Q8A 8 57 D11 Q3A 5 38 RESET Q7A 9 56 D10 Q2A 6 37 GND Q6A 10 55 D9 Q1A 7 36 CLK Q5A 11 54 GND Q13B 8 35 CLK Q4A 12 53 D8 VDDQ 9 34 VDDQ Q3A 13 52 D7 Q12B 10 33 VDD Q2A 14 51 RESET Q11B 11 32 VREF 12 31 D6 64-Pin A D11 3 VDD GND Q11A D12 VDDQ 63 D13 64 2 Q9A 1 Q12A Q8A Q13A 56 55 54 53 52 51 50 49 48 47 46 45 44 43 56-Pin ZB 14 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 D4 VDDQ 18 47 VDDQ Q12B 19 46 VDD Q11B 20 45 VREF Q10B 21 44 D6 Q9B 22 43 GND Q8B 23 42 D5 Q7B 41 40 D4 Q6B 24 25 GND 26 39 GND Maximum Ratings (Above which the useful life may be VDDQ Q5B 27 38 VDDQ impaired. For user guidelines, not tested.) 28 37 VDD Q4B 29 36 D2 Q3B 30 35 D1 Q2B 31 34 GND Q1B 32 33 VDDQ D3 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol/ Conditions Ratings Units Storage Temperature Tstg –65 to 150 °C Supply Voltage VD D or VD D Q –0.5 to 3.6 Input Voltage(1 ,2 ) VI –0.5 to VD D +0.5 (1 , 2 ) VO –0.5 to VD D Q +0.5 Input Clamp Current IIK , VI<0 or VI >VD D ± 50 Output Clamp Current IO K , VO <0 or VO >VD D Q ± 50 Continuous Output Current IO , VO = 0 to VD D Q ± 50 VD D , VD D Q or GND Current/Pin ID D , ID D Q or IG N D ±100 Package Thermal (3 ) impedance A Package Ø JA 2 B- Package 2 D3 Ite m Output Voltage 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 3.6V Maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. VDDQ Q8B VDD CLK D2 48 D1 17 VDDQ D5 Q13B Q1B 30 Q2B 13 Q3B Q9B Q4B CLK Q5B GND 49 VDDQ 50 16 Q6B 15 Q1A Q7B GND Q10B V mA 55 °C/W 24 PS8657 02/13/03 PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Recommended Operating Conditions(4) Parame te rs De s cription VTT VI Nom. M ax. Core Output Supply Voltage PC1600 P C 2700 2.3 2.5 2.7 I/O Supply Voltage P C 3200 2.5 2.6 2.7 PC1600 P C 2700 1.15 1.25 1.35 P C 3200 1.25 1.3 1.35 VREF –0.04 VREF VREF +0.04 VDD/VDDQ VREF M in. Reference Voltage VREF = 0.5X VDDQ Termination Voltage Input Voltage 0 Units VDD VIH AC High - Level Input Voltage VREF +310mV VIL AC Low - Level Input Voltage VIH DC High - Level Input Voltage VIL DC Low - Level Input Voltage VIH High - Level Input Voltage VIL Low - Level Input Voltage VICR Common- mode input range VID Differential Input Voltage IOH High- Level Output Current –16 IOL Low- Level Output Current 16 TA Operating Free- Air Temperature V VREF – 310mV Data Inputs VREF +150mV VREF –150mV 1.7 RESET 0.7 0.97 1.53 CLK, CLK 0.36 mA 0 70 ºC Note: 4. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW. 3 PS8657 02/13/03 PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics for PC1600 ~ PC2700 (Over the Operating Range, TA = 0°C to +70°C, VDD = 2.5V ± 200mV, VDDQ = 2.5V ± 200mV) Pa ra me te rs VIK Typ. 2.3V IO H = –10 0 µA M ax. 2.3V 1.95 IO L =10 0 µA 2 . 3 V- 2 . 7 V 0.2 IO H =8 mA 2.3V 0.35 All Inp uts VI = VDD o r GN D 2.7V ±5 S tand b y (S tatic) RES ET = GN D 10 O p erating (S tatic) RES ET = VDD VI = VIH(AC ) o r VIL(AC ) 25 Dynamic O p erating clo ck o nly RES ET = VDD VI = VIH(AC ) o r VIL(AC ) C LK and C LK switching 5 0 % d uty cycle Dynamic O p erating p er each d ata inp ut RES ET = VDD VI = VIH(AC ) o r VIL(AC ) C LK and C LK switching 5 0 % d uty cycle. O ne d ata inp ut switching at half clo ck freq uency, 5 0 % d uty cycle Data Inp uts VI = VREF ± 3 10 mV C LK and C LK VIC R = 1. 2 5 V, VI(PP) = 3 6 0 mV RES ET VI = VDD o r GN D IO = 0 4 V µA mA 30 µA/ clo ck MHz 10 µA/ clo ck MHz d a ta inp ut 2.7V 2.5V Units – 1.2 IO H = –8 mA IDDD CI II = –18 mA M in. VDD – 0 . 2 VO L IDD VD D 2 . 3 V- 2 . 7 V VO H II Te s t Co nditio ns 2.5 3.5 2.5 3.5 PS8657 pF 02/13/03 PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics for PC3200 (Over the Operating Range, TA = 0°C to +70°C, VDD = 2.6V ± 100mV, VDDQ = 2.6V ± 100mV) Pa ra me te rs VIK Ty p. 2.5V IO H = – 1 0 0 µA M ax. 2.5V 1.95 IO L =1 0 0 µA 2 . 5 V- 2 . 7 V 0.2 IO H =8 mA 2.5V 0.35 All Inp uts VI = VDD o r GN D 2.7V ±5 S tand b y (S tatic) RES ET = GN D 10 O p erating (S tatic) RES ET = VDD VI = VIH(AC ) o r VIL(AC ) 25 Dynamic O p erating clo ck o nly RES ET = VDD VI = VIH(AC ) o r VIL(AC ) C LK and C LK switching 5 0 % d uty cycle Dynamic O p erating p er each d ata inp ut RES ET = VDD VI = VIH(AC ) o r VIL(AC ) C LK and C LK switching 5 0 % d uty cycle. O ne d ata inp ut switching at half clo ck freq uency, 5 0 % d uty cycle Data Inp uts VI = VREF ± 3 1 0 mV C LK and C LK VIC R = 1 . 2 5 V, VI(PP) = 3 6 0 mV RES ET VI = VDD o r GN D IO = 0 5 V µA mA 30 µA/ clo ck MHz 10 µA/ clo ck MHz d a ta inp ut 2.7V 2.6V Units – 1.2 IO H = – 8 mA IDDD CI II = – 1 8 mA M in. VDD – 0 . 2 VO L IDD VD D 2 . 5 V- 2 . 7 V VO H II Te s t Co nditio ns 2.5 3.5 2.5 3.5 PS8657 pF 02/13/03 PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) fclo ck VDD =2 .5 V ± 0 . 2 V VDD =2 .6 V ± 0 . 1 V M in. M in. C lo ck F req uency P ulse Duratio n, C LK , C LK High o r Lo w ta c t Differential inp uts active time, d ata inp uts must b e lo w after RES ET High tinact Differential Inp uts inactive time, d ata and clo ck inp uts must b e held at valid levels (no t flo ating) after RES ET Lo w S etup time, slo w slew rate Ho ld time, fast slew rate 2.5 (5 , 7 ) S etup time, fast slew rate th M ax. 270 tW tS U M ax. (6 , 7 ) Ho ld time, slo w slew rate (6 , 7 ) MHz 2.5 22 22 22 ns ↑ Data b efo re C K↑ , C K (5 , 7 ) 270 Units ↑ Data b efo re C K↑ , C K 0.75 0.75 0.9 0.9 0.75 0.75 0.9 0.9 Notes: 5. Data signal input slew rate ≥ 1 V/ns 6. Data signal input slew rate ≥ 0.5V/ns and <1V/ns 7. CLK, CLK input slew rates are ≥ 1 V/ns. Switching Characteristics for PC1600 ~ PC2700 (over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms). Parame te r From (Input) VDD = 2.5V ±0.2V To (Output) M in. fmax Typ. Units M ax. 210 tpd CLK, CLK Q tphl RESET Q MHz 1.1 2.2 ns 5.0 Switching Characteristics for PC3200 (over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms). Parame te r From (Input) VDD = 2.6V ±0.1V To (Output) M in. Typ. Units M ax. 210 fmax tpd CLK, CLK Q tphl RESET Q 1.1 MHz 2.2 ns 5.0 6 PS8657 02/13/03 PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Circuit and Switching Waveforms LVCMOS RESET Input VDD VDD/2 From Output Under Test 0V t inact tact IDD(9) Test Point 500Ω CL = 30pF(8) IDDH 90% 10% Load Circuit IDDL Voltage and Current Waveforms Input Active and Inactive Times Timing Input VICR tw VIH Input VREF VREF Output VIL VICR tsu VREF t PLH t PHL VTT VTT VOH Voltage Waveforms - Propagation Delay Times LVCMOS RESET Input VI(PP) VIH VDD/2 VIL t PHL th VIH Input VI(PP) VOL Voltage Waveforms - Pulse Duration Timing Input VICR Output VREF VOH VTT VIL VOL Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Setup and Hold Times Parameter Measurement Information Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 10. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 ohms. Input slew rate = 1V/ns ±20% (unless otherwise specified). 11. The outputs are measured one at a time with one transition per measurement. 12. VTT = VREF = VDDQ/2 13. VIH = VREF + 310mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input. 14. VIL = VREF –310mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input. 15. tPLH and tPHL are the same as tpd. 7 PS8657 02/13/03 PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 64-Pin TSSOP (A) Package 64 .236 .244 1 .665 .673 6.0 6.2 16.9 17.1 .004 .008 0.09 0.20 0.45 .018 0.75 .030 SEATING PLANE 1.20 .047 Max. .319 BSC 8.1 .004 0.10 .0197 BSC 0.50 .002 .006 .007 0.17 .011 0.27 0.05 0.15 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS .311 .319 7.90 8.10 0.25 C A 56-Pin QFN (ZB) Package .033 MAX 0.84 .012 .019 0.30 0.50 .007 .012 0.18 0.30 .019 BSE 0.50 .008 REF 0.20 0 .0015 0.00 0.04 O 0.10 M C A B R 0.25 x 3 .311 .319 7.90 8.10 .199 .211 5.05 5.35 0.25 Chamfer .171 .183 4.35 4.65 0.08 C 0.25 C B X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Notes: 1. Controlling dimensions in millimeters 2. Ref: JEDEC MO-220 variation VLLD-2 Ordering Information Orde ring Code Package Type PI74SSTVF16859A 64- Pin TSSOP PI74SSTVF16859ZB 56- Pin QFN Te mpe rature Range 0°C to 70°C Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 8 PS8657 02/13/03