PI74SSTUA32864 25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer Features Description • • • • Pericom Semiconductor’s PI74SSTUA32864 is a 25-Bit 1:1 or 14-Bit 1:2 configurable registered buffer and designed for 1.7V to 1.9V VDD operation. Designed for low-voltage operation: VDD = 1.8V Supports Low Power Standby Operation Enhanced Signal Integrity for 1 and 2 Rank Modules All Inputs are SSTL_18 compatible, except RST, C0, C1, which are LVCMOS. • Output drivers are optimized to drive DDR2 DIMM loads • Packaging (Pb-free & Green available): 96-Ball LFBGA (NB) • Used in DDR2-400/533/667 memory applications All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V drivers that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18 specifications. The device operates from a differential clock (CK and CK). Data is registered at the crossing of CK going high, and CK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration for 25-Bit 1:1 (when LOW) to 14-Bit 1:2 (when HIGH). Block Diagram 1:2 Mode (Positive Logic) The device supports low-power standby operation. When the reset input (RST) is low, the differential input receivers are disabled and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition , when RST is low, all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be held at a valid logic high or low level. RST CK CK VREF DCKE To ensure defined outputs from the register before a stable clock has been supplied, RST must be held in the low state during power up. QCKEA 1D In the DDR2 RDIMM application, RST is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. C1 DODT R QCKEB* 1D QODTA C1 R QODTB* 1D QCSA DCS As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until the input receivers are fully enabled, the design of the registered buffer must ensure that the outputs remain low, thus ensuring no glitches on the output. C1 R QCSB* The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will function normally. The RST input has priority over the DCS and CSR control will force the outputs low. If the DCS control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the set-up time requirement for DCS would be the same as for the other D data inputs. CSR D1 0 1 1D Q1A C1 R Q1B* Note: Disabled in 1:1 configuration TO OTHER CHANNELS 07-0266 1 PS8743D 11/06/07 PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer Pin Configuration 1:1 Register (C0 = 0, C1 = 0) 1 2 3 4 5 6 A DCKE NC VREF VDD QCKE NC B D2 D15 GND GND Q2 Q15 C D3 D16 VDD VDD Q3 Q16 D DODT NC GND GND QODT NC E D5 D17 VDD VDD Q5 Q17 F D6 D18 GND GND Q6 Q18 G NC RST VDD VDD C1 C0 H CK DCS GND GND QCS NC J CK CSR VDD VDD ZOH ZOL K D8 D19 GND GND Q8 Q19 L D9 D20 VDD VDD Q9 Q20 M D10 D21 GND GND Q10 Q21 N D11 D22 VDD VDD Q11 Q22 P D12 D23 GND GND Q12 Q23 R D13 D24 VDD VDD Q13 Q24 T D14 D25 VREF VDD Q14 Q25 Pin Configuration 1:2 Register (C0 = 0, C1 = 1) 1 2 3 4 A DCKE NC VREF VDD B D2 NC GND GND Q2A Q2B C D3 NC VDD VDD Q3A Q3B D DODT NC GND GND E D5 NC VDD VDD Q5A Q5B F D6 NC GND GND Q6A Q6B G NC RST VDD VDD C1 C0 H CK DCS GND GND QCSA QCSB J CK CSR VDD VDD ZOH ZOL K D8 NC GND GND Q8A Q8B L D9 NC VDD VDD Q9A Q9B M D10 NC GND GND Q10A Q10B N D11 NC VDD VDD Q11A Q11B P D12 NC GND GND Q12A Q12B R D13 NC VDD VDD Q13A Q13B T D14 NC VREF VDD Q14A Q14B 07-0266 5 6 QCKEA QCKEB QODTA QODTB 2 PS8743D 11/06/07 PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer Pin Configuration 1:2 Register (C0 = 1, C1 = 1) 1 2 3 4 5 6 A D1 NC VREF VDD Q1A Q1B B D2 NC GND GND Q2A Q2B C D3 NC VDD VDD Q3A Q3B D D4 NC GND GND Q4A Q4B E D5 NC VDD VDD Q5A Q5B F D6 NC GND GND Q6A Q6B G NC RST VDD VDD C1 C0 H CK DCS GND GND QCSA QCSB J CK CSR VDD VDD ZOH ZOL K D8 NC GND GND Q8A Q8B L D9 NC VDD VDD Q9A Q9B M D10 NC GND GND Q10A Q10B N DODT NC VDD VDD P D12 NC GND GND Q12A Q12B R D13 NC VDD VDD Q13A Q13B T DCKE NC VREF VDD QODTA QODTB QCKEA QCKEB NB, 96-ball LFBGA (MO-205CC) 07-0266 3 PS8743D 11/06/07 PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer Terminal Functions Name Description Characteristics GND Ground Ground Input VDD Power Supply 1.8V nominal VREF Input Reference Voltage 0.9V nominal ZOH Reserved for future use Input ZOL Reserved for future use Input CK Positive master clock input Differential Clock input CK Negative master clock input Differential Clock input C0, C1 Configuration control inputs LVCMOS inputs RST Asynchronous reset input - resets registers and disables VREF data and clock differential - input receivers LVCMOS inputs CSR, DCS Chip select inputs disables D1-D24 outputs switching when both inputs are high SSTL_18 input D1, D25 Data input - clocked in on the crossing of the rising edge of CK and the falling edge of CK SSTL_18 input DODT The outputs of this register bit will not be suspended by the DCS and CSR control SSTL_18 input DCKE The outputs of this register bit will not be suspended by the DCS and CSR control SSTL_18 input Q1-Q25 Data outputs that are suspended by the DCS and CSR control 1.8V CMOS QCS Data output that will not be suspended by the DCS and CSR controll 1.8V CMOS QODT Data output that will not be suspended by the DCS and CSR controll 1.8V CMOS QCKE Data output that will not be suspended by the DCS and CSR controll 1.8V CMOS Function Table (each flip-flop) Inputs Outputs RST DCS CSR CK CK Dn, DODT, DCKE Qn QCS QODT, QCKE H L L ↑ ↓ L L L L H L L ↑ ↓ H H L H H L L L or H L or H X Q0 Q0 Q0 H L H ↑ ↓ L L L L H L H ↑ ↓ H H L H H L H L or H L or H X Q0 Q0 Q0 H H L ↑ ↓ L L H L H H L ↑ ↓ H H H H H H L L or H L or H X Q0 Q0 Q0 H H H ↑ ↓ L Q0 H L H H H ↑ ↓ H Q0 H H H H H L or H L or H X Q0 Q0 Q0 L L L L 07-0266 X or floating X or floating X or floating X or floating X or floating 4 PS8743D 11/06/07 PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................................... –65°C to +150°C Supply Voltage Range, VDD .............................................–0.5V to 2.5V Input Voltage Range,VI : (See Notes 2 and 3): ................–0.5V to 2.5V Output Voltage Range, VO (See Notes 2 and 3) .... –0.5V to VDD + 0.5V Input Clamp Current, IIK (VI < 0 or VI = VDD ) .........................–50mA Output Clamp Current, IOK (VO < 0 or VO > VDD) ................... ±50mA Continous Output Current, IO (VO = 0 to VDD) ........................ ±50mA Continous Current through each VDD or GND ......................... ±100mA Notes: 1. Stresses greater than those listed under MAXIMUM RAINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 2.5V maximum Recommended Operating Conditions(1) Parameters Description VDD Supply Voltage VREF Reference Voltage VTT Termination Voltage VI Input Voltage VIH AC High - Level Input Voltage VIL AC Low- Level Input Voltage VIH DC High - Level Input Voltage VIL DC Low- Level Input Voltage VIH High Level Input Voltage VIL Low Level Input Voltage Min. Nom. 1.7 Max. 1.9 0.49 x VDD 0.50 x VDD 0.51 x VDD VREF -40mA VREF VREF +40mA 0 Units VDD VREF +250mV VREF -250mV Data Inputs V VREF +125mV VREF -125mV RST, CN 0.65 x VDD 0.35 x VDD VICR Common-mode input Voltage VID Differential Input Voltage IOH High-Level Output Current -8 IOL Low-Level Output Current -8 TA Operating Free-air Temperature CK, CK 0.675 1.125 600 0 mV mA 70 ºC Notes: 1. The RST and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating, unless RST is low. 07-0266 5 PS8743D 11/06/07 PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer Electrical Characteristics Over Recommended Operating Free Air Temperature range Parameters Description Test Conditions VDD Min. 1.2 VOH IOH = -6 mA 1.7V VOL IOL = 6 mA 1.7V II IDD IDDD Nom. 0.5 All inputs VI = VDD or GND ±5 Static Stand-by RST = GND 100 Static Operating RST = VDD, VI = VIH(AC) or VIL(AC) Dynamic Operating Clock only RST = VDD, VI = VIH(AC), or VIL(AC) CK and CK switching 50% duty cycle 1.9V RST = VDD, VI = VIH(AC), or VIL(AC) CK and CK switching 50% Dynamic Operating - per duty cycle. One data input switcheach data input, 1:1 mode ing at half clock frequency, 50% duty cycle 40 IO = 0 Data inputs VI = VREF ±250mV CK and CK VICR = 0.9V, VID = 600mV RST VI = VDD or GND Units V μA mA μA/ clock MHz 28 36 μA/ clock MHz data input 1.8V RST = VDD, VI = VIH(AC), or VIL(AC) CK and CK switching 50% Dynamic Operating - per duty cycle. One data input switcheach data input, 1:2 mode ing at half clock frequency, 50% duty cycle CI Max. 36 2.5 3.5 2 3 pF 2.5 Timing Requirements Over Recommended Operating Free Air Temperature range (See Figure 1) Parameter fclock tW tact(1) tinact(1) tsu th Description Min. Clock frequency Pulse Duration, CK, CK, High or low Differential inputs active Setup time Hold Time Units 350 MHz 1 time(1) Differential inputs inactive Max 10 time(2) 15 DCS before CK↑, CK↓, CSR high 0.7 DCS before CK↑, CK↓, CSR low 0.5 ODT, CKE and data before CK↑, CK↓ 0.5 DCS, ODT, CKE and data before CK↑, CK↓ 0.5 ns Notes: 1. This parameter is not necessarily production tested. 2. Data and VREF inputs must be a low minimum time of tact max, after RST is taken high. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max after RST is taken low. 07-0266 6 PS8743D 11/06/07 PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer Switching Characteristics (Over Recommended Operating Free Air Temperature range) Parameter fmax tpdm tpdmss (simultaneous switching)(1,2) tRPHL From To (see Fig. 1) Min. CK and CK CK and CK "Test Point" "Test Point" 1.2 RST Q 0 Max. 350 1.90 2.00 Units MHz ns ns 3 ns Notes: 1. Includes 350ps test load transmission-line delay. 2. This parameter is not necessarily production tested. Output Edge Rates Over Recommended Operating Free Air Temperature range (See Figure 2) Parameter VDD = 1.8V ± 0.1V Min. Max. dV/dt_r 1 4 dV/dt_f 1 4 dV/dt(1) Units V/ns 1 Notes: 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 07-0266 7 PS8743D 11/06/07 PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer Test Circuit and Switching Waveforms VDD DUT TL= 50-ohm CK Out CK CK Inputs Test Point R = 1000-ohm TL= 350ps, 50-ohm Test Point R = 1000-ohm CL= 30pF (see note 1) RL= 100-ohm Test Point Load Circuit LVCMOS RST Input CK VDD VDD/2 VICR VDD/2 0V t inact tact IDD(2) VICR VID CK 90% Output 10% t PLH t PHL VTT VTT VOH VOL Voltage and Current Waveforms Input Active and Inactive Times Voltage Waveforms - Propagation Delay Times tw Input VICR VICR LVCMOS RESET Input VID VIH VDD/2 VIL tRPHL Voltage Waveforms - Pulse Duration Output VOH VTT VOL Voltage Waveforms - Propagation Delay Times CK VICR VID CK tsu th VIH VREF Input VREF VIL Voltage Waveforms - Setup and Hold Times Figure 1. Parameter Measurement Information (VDD = 1.8V ± 0.1V) Notes: 1. CL includes probe and jig capacitance 2. IDD tested with clock and data inputs held at VDD or GND and IO = 0mA 3. All input pulses are supplied by generators having the following characteristics: Pulse Repertition Rate ≥ 10 MHz, ZO = 50Ω, input slew rate = 1V/ns ± 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD /2 6. VIH = VREF +250mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF -250mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV 9. tPLH and tPHL are the same as tpdm. 07-0266 8 PS8743D 11/06/07 PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer VDD DUT R = 50-ohm Test Point Out CL= 10pF (see note 1) Load Circuit -High -to- Low Slew Rate Measurement Output VOH 80% 20% dv_f VOL dt_f Voltage Waveforms - High -to- Low Slew Rate Measurement DUT Test Point Out CL= 10pF (see note 1) RL = 50-ohm Load Circuit - Low -to- High Slew Rate Measurement dv_r dv_r 80% 20% Output VOH VOL Voltage Waveforms - Low -to- High Slew Rate Measurement Figure 2. Output Slew-Rate Measurement Information (VDD = 1.8V ± 0.1V) Notes: 1. CL includes probe and jig capacitance 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified). 07-0266 9 PS8743D 11/06/07 PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer Packaging Mechanical: 96-ball LFBGA (NB) DATE: 09/11/06 DESCRIPTION: 96-ball, Low Profile Fine Pitch Ball Grid Array (LFBGA) Notes: 1. 2. PACKAGE CODE: NB96 Controlling dimensions in millimeters Ref: JEDEC MO-205F/CC REVISION: C DOCUMENT CONTROL #: PD-2004 06-0735 Ordering Information Ordering Code Package Code Package Description PI74SSTUA32864NB NB 96-Ball LFBGA PI74SSTUA32864NBE NB Pb-free & Green, 96-Ball LFBGA Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. Number of Transistors = TBD Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 07-0266 10 PS8743D 11/06/07