TM Application Specific Crystal Oscillator 7.0 x 5.0mm SHPCIE100 3.3V HCSL Low Jitter 100MHz PCIe® 2.0 XO ASSP XO™ for Networking 7.0 x 5.0mm Ceramic SMD Package: Product Features Recommended Land Pattern: • Provides 100 MHz HCSL output for interfacing to standard PCIe® devices • Very low PCIe 2.0 jitter - 1.8ps RMS (typ.) • Thicker crystal for improved reliability • Pb-free & RoHS compliant • Industrial temperature range Product Description The SHPCIE100 3.3V crystal clock oscillator achieves superb jitter for PCIe® 1.0 & 2.0 applications. The output clock signal, generated internally with a patented oscillator design, is compatible with HCSL logic levels. The device, available on tape and reel, is contained in a 7.0 x 5.0mm surface-mount ceramic package. Pin Functions: Applications • Server Pin Function 1 OE Function 2 N/C 3 Ground 4 OUT 5 OUT 6 VCC • Network Switch/Router *Extended high frequency power decoupling is recommended (see test circuit for minimum • Telecom Switch recommendation). To ensure optimal performance, do not route RF traces beneath the • Media Box package. • Graphics Card • Host Bus Adapter Part Ordering Information: SHPCIE100 SaRonix-eCera™ is a Pericom® Semiconductor company • US: +1-408-435-0800 TW: +886-3-4518888 • www.pericom.com All specifications are subject to change without notice. SHPCIE100 Rev C 04/07/10 B 3.3V HCSL Low Jitter 100 MHz PCIe® 2.0 XO SHPCIE100 TM Application Specific Crystal Oscillator 7.0 x 5.0mm Electrical Performance Parameter Min. Typ. 2.97 3.30 Output Frequency Max. 100 Supply Voltage Units MHz 3.63 V Supply Current, Output Enabled 40 mA Supply Current, Output Disabled 10 mA Frequency Stability Operating Temperature Range -40 Output Logic 0, VOL -0.15 Output Logic 1, VOH 0.66 Output Load Notes ±50 ppm See Note 1 below +85 °C Industrial 0.9 V V Rs = 33Ω, Rp = 50Ω, CL = 2pF Duty Cycle 45 Rise and Fall Time output requires termination 55 % Measured 50% of waveform 0.7 ns Maximum measured from VOL = 0.175V to VOH = 0.525V Jitter, Phase RMS (1-σ) 1.8 2.5 ps As defined by PCI-SIG for PCIe® 2.0 reference clock Jitter, pk–pk 27 40 ps 100,000 random periods Notes: 1. Stability includes all combinations of operating temperature, load changes, rated input (supply) voltage changes, initial calibration tolerance (25°C), aging (5 year at 40°C average effective ambient temperature), shock and vibration. 2. For specifications othere than those listed, please contact sales. Output Enable / Disable Function Parameter Min. Input Voltage (pin 1), Output Enable Typ. Max. Units 2.2 Notes V or open V Outputs disabled to Hi-Z Input Voltage (pin 1), Output Disable (low power standby) 0.8 Output Disable Delay 200 ns Output Enable Delay 10 ms Absolute Maximum Ratings Parameter Storage Temperature Min. Typ. -55 Max. Units +125 °C Notes For the latest product information visit: http://www.pericom.com/products/asspxo/SHPCIE100 For test circuit go to: http://www.pericom.com/pdf/sre/tc_hcsl.pdf For soldering reflow profile and reliability test ratings go to: http://www.pericom.com/pdf/sre/reflow.pdf For typical phase noise go to: http://www.pericom.com/pdf/sre/pn_SHPCIE100.pdf For tape and reel information go to: http://www.pericom.com/pdf/sre/tr_7050.pdf SaRonix-eCera™ is a Pericom® Semiconductor company • US: +1-408-435-0800 TW: +886-3-4518888 • www.pericom.com All specifications are subject to change without notice. SHPCIE100 Rev C 04/07/10 B