PL0300 Low Noise, Fixed Output Voltage 300mA LDO Regulator FEATURES Guaranteed 300mA output Ultra low output noise Output voltage accuracy: ±2% Low ground current: 90µA Very low dropout: 380mV @ 300mA Zero shutdown supply current TTL-logic-controlled enable input Thermal and current limit protections Compatible with low ESR capacitor to achieve ultra low droop load transient response Ultra fast line transient response Low profile 5-lead SOT-25 package Fixed options from 1.5V to 5.0V with 100mV steps APPLICATIONS Cellular and cordless phones PDAs Battery powered portable equipment Notebook computers PC peripherals Wireless LAN cards Bluetooth devices DESCRIPTION The PL0300/P is a CMOS low dropout linear regulator with ultra-low-noise output, very low dropout voltage and very low ground current. The PL0300/P operates from a 2.5V to 5.5V input voltage range and delivers up to 300mA, with low dropout of 380mV at 300mA. Other features of the PL0300/P include short-circuit protection and thermal-shutdown protection. The PL0300/P is designed especially for batterypowered portable devices. Its reference bypass pin improves low noise performance which makes it ideal for noise-sensitive RF and personal communication applications. Other key application areas for the PL0300/P include handheld computers, PCMCIA cards and WLAN cards. The PL0300/P is available in small 5-lead SOT-25 package. TYPICAL APPLICATION CIRCUIT July 2007 www.picsemi.com © 2007 Power IC. All Rights Reserved. 1 PL0300 PIN CONFIGURATION PIN DESIGNATOR Name IN GND Pin 1 2 Type Supply Ground EN 3 Logic input BYP/ PGD 4 Bypass/PGood OUT 5 Analog output Function Supply voltage. 2.5V ~ 5.5V Ground pin Enable/Shutdown. TTL and CMOS compatible input. Logic ‘H’: enable, logic ‘L’: shutdown Reference voltage bypass pin. Connect 0.01µF ≤ CBYP ≤ 0.1µF to GND to reduce output noise. May be left open Regulator output PIN DESCRIPTION PL0300 Name IN GND EN BYP OUT Pin 1 2 3 4 5 Type Supply Ground Logic input Bypass Analog output Function Supply voltage. 2.5 ~ 5.5V Ground TTL and CMOS compatible input. Logic ‘H’: enable, logic ‘L’: shutdown Noise filtering pin Regulator output Name IN GND EN Pin 1 2 3 Type Supply Ground Logic input PGD 4 Power good OUT 5 Analog output Function Supply voltage. 2.5 ~ 5.5V Ground TTL and CMOS compatible input. Logic ‘H’: enable, logic ‘L’: shutdown Monitors the output voltage and signals an error condition when the output voltage drops 10% below its nominal value Regulator output PL0300P July 2007 www.picsemi.com © 2007 Power IC. All Rights Reserved. 2 PL0300 BLOCK DIAGRAM July 2007 www.picsemi.com © 2007 Power IC. All Rights Reserved. 3 PL0300 ABSOLUTE MAXIMUM RATINGS Symbol VIN VEN PD TSTG RθJA TJ,MAX TL ESD Parameter DC Supply Voltage at Pin 1 Enable Input Voltage at Pin 3 Continuous Power Dissipation Storage Temperature Range Thermal Resistance, Junction-To-Air Operating Junction Temperature Lead Temperature (Soldering, 5sec) ESD Capability, HBM Model Value -0.3 to +6.0 -0.3 to +6.0 Internally limited -65 to +150 +235 -40 to +125 +260 2.0 Unit V V W °C °C/W °C °C KV ELECTRICAL CHARACTERISTICS ( All specifications are at TA = 25°C. VIN = VOUT ( NOMINAL ) + 1V OR 2.5V whichever is greater, VEN = VIN, CIN = COUT = 1µF, unless otherwise specified.) Symbol Parameter VIN Supply Voltage VOUT Output Voltage Accuracy VDP Dropout Voltage (Note 1) IMAX ILIM IQ Maximum Output Current Short Circuit Current Limit Shutdown Quiescent Current IG Ground Pin Current ΔVLINE Line Regulation dVOUT/dVIN PSRR Ripple Rejection eNO Output Voltage Noise July 2007 Test Conditions IO = 1mA to 300mA, TA = +25°C IO = 1mA to 300mA, TA = -40°C to 85°C ILOAD = 300mA ILOAD = 100mA Continuous VOUT < 90% of V NOM VEN < 0.4V Min Max Unit 2.5 5.5 V -2.0 +2.0 % -3.0 +3.0 % 650 0.05 0.5 mV mV mA RMS mA µA 90 140 µA 0.15 %/V 380 130 300 ILOAD = 1mA VIN = VOUT + 1V (or 2.5V, whichever is greater) to 5.5V, -0.15 IO = 1 mA f = 100Hz, COUT= 10µF, CBYP = 10nF, ILOAD = 1mA COUT = 10µF, CBYP = 10nF, f = 10Hz to 100KHz www.picsemi.com © 2007 Power IC. All Rights Reserved. Typ 65 dB 70 µVRMS 4 PL0300 OVER TEMPERATURE PROTECTION Symbol Parameter Thermal Shutdown Temperature Thermal Shutdown Hysteresis Test Conditions Min Typ 165 15 Max Unit °C °C Test Conditions Min 1.6 Typ Max 25 Unit V V µA µS 900 Ω ENABLE INPUT Symbol VIH VIL IEN Parameter Logic Input High Voltage Logic Input Low Voltage Logic Input Current Shutdown Exit Delay Shutdown Discharge Resistance 0.4 0.5 -0.5 VEN = 0 to 5.5V, CBYP = 10nF, COUT = 1µF Note 1: The Dropout Voltage is defined as VIN - VOUT, when VIN = VOUT ( NOM ) July 2007 www.picsemi.com © 2007 Power IC. All Rights Reserved. 5 PL0300 TYPICAL OPERATING CHARACTERSTICS (All specifications are at TA = 25°C , unless otherwise specified) July 2007 www.picsemi.com © 2007 Power IC. All Rights Reserved. 6 PL0300 TYPICAL OPERATING CHARACTERSTICS ( continued ) (All specifications are at TA = 25°C , unless otherwise specified) July 2007 www.picsemi.com © 2007 Power IC. All Rights Reserved. 7 PL0300 TYPICAL OPERATING CHARACTERSTICS ( continued ) (All specifications are at TA = 25°C , unless otherwise specified) July 2007 www.picsemi.com © 2007 Power IC. All Rights Reserved. 8 PL0300 OPERATION The PL0300/P is an ultra-low-noise, low-dropout, lowquiescent current linear regulator designed for spacerestricted applications. It is available with preset output voltages ranging from 1.5V to 5.0V in 100mV increments. It can supply loads of up to 300mA. As shown in the Block Diagram, the PL0300/P consists of a highly accurate band gap core, noise bypass circuit, error amplifier, P-channel pass transistor and an internal feedback voltage divider. The PL0300/P allows for an adjustable output with an external feedback network. The 1.0V band gap reference is connected to the error amplifier’s inverting input. The error amplifier compares this reference with the feedback voltage and amplifies the difference. If the feedback voltage is lower than the reference voltage, the pass transistor gate is pulled low. This allows more current to pass to the output and increases the output voltage. If the feedback voltage is too high, the pass transistor gate is pulled high, allowing less current to pass to the output. The output voltage is fed back through an internal resistor voltage-divider connected to the OUT pin. An external bypass capacitor connected to BYP (PL0300/P-BYP) reduces the noise at the output. Additional blocks include a current limiter, over temperature protection and shutdown logic. Internal P-Channel Pass Transistor The PL0300/P features a 1Ω (typical) P-channel MOSFET pass transistor. This provides several advantages over similar designs using a PNP pass transistor, including longer battery life. The P-channel MOSFET requires no base drive, which considerably reduces the quiescent current. PNP-based regulators waste considerable current in dropout when the pass transistor saturates. They also use high base-drive current under heavy loads. The PL0300/P does not suffer from these problems and consumes only 90μA of quiescent current. July 2007 Current Limit The PL0300/P includes a current limiter. It monitors the output current and controls the pass transistor’s gate voltage to limit the output current under 550mA (typical). The output can be shorted to ground for an indefinite amount of time without damaging the part. The short circuit current limit is increased to approximately 650mA (typical) when the output voltage is within 10% of the nominal output, thus improving the performance of large pulsating loads. The in-regulation current limit option provides the user to overload the device, maintaining a continuous 300mA (RMS) load. Enable Input The PL0300/P features an active-high Enable input (EN) pin that allows on/off control of the regulator. The PL0300/P bias current reduces to ZERO (leakage current) when it goes into shutdown. The Enable input is TTL/CMOS compatible for simple logic interfacing. When EN is ‘H,’ the output voltage startup rising time is typically 25µs. Connect EN pin to IN pin for normal operation. Power Good Flag (Applicable for PL0300P) The PL0300/P features a Power Good flag (PGD), which monitors the output voltage and signals an error condition when the output voltage drops 10% below its nominal value. Under Voltage Lockout When the input supply goes too low (typically below 2.0V), the PL0300/P produces an internal UVLO (Under Voltage Lockout) signal that generates a fault signal and shuts down the chip. This mechanism protects the chip from producing false logic due to low input supply. www.picsemi.com © 2007 Power IC. All Rights Reserved. 9 PL0300 APPLICATION INFORMATION Quick Charging Mode The PL0300/P has a quick charge block to get the reference up very quickly by charging the BYP capacitor with very high current when the chip comes out of shut down. This quick charge block stops charging the BYP capacitor when the reference reaches 95% of its nominal value and then the chip switches out of quick charging mode to normal operating mode. Over Temperature Protection Over temperature protection limits the total power dissipation in the PL0300/P. When the junction temperature exceeds TJ = +165°C, the thermal sensor signals the shutdown logic and turns off the pass transistor. The thermal sensor turns the pass transistor on again after the IC’s junction temperature drops by 15°C, resulting in a pulsed output during continuous thermal-overload conditions. Thermal-overload protection is designed to protect the PL0300/P in the event of a fault condition. For continuous operation, do not exceed the absolute maximum junction temperature rating of TJ = +150°C. Operating Region and Power Dissipation The PL0300/P’s maximum power dissipation depends on (1) the thermal resistance of the case and circuit board, (2) the temperature difference between the die junction and ambient and (3) the rate of airflow. The power dissipation across the device is: P = IOUT × (VIN – VOUT) The maximum power dissipation is: PMAX = (TJ – TA)/(θJC + θCA) Where (TJ – TA) is the temperature difference between the PL0300/P die junction and the surrounding air, θJC is the thermal resistance of the package and θCA is the thermal resistance through the PC board, copper traces and other materials to the surrounding air. The GND pin of the PL0300/P performs the dual function of providing an electrical connection to ground and channeling heat away. Connect the GND pin to ground using a large pad or ground plane. Capacitor Selection And Regulator Stability Use a 1.0μF capacitor on the PL0300/P input and a 1.0μF capacitor on the output. Large input capacitor values and lower ESR provide better noise rejection and linetransient response. Reduce output noise and improve load-transient response, stability and power-supply rejection by using large output capacitors. Note that some ceramic dielectrics exhibit large capacitance and ESR variation with temperature. With dielectrics such as Z5U and Y5V, it may be necessary to use a 2.2μF or larger output capacitor to ensure stability at temperatures below -10°C. With X7R or X5R dielectrics, 1μF is sufficient at all operating temperatures. Use a 0.01μF bypass capacitor at BYP (PL0300/P-BYP) for low-output voltage noise. The leakage current going into the BYP pin should be less than 10nA. Noise, PSRR and Transient Response The PL0300/P is designed to deliver ultra-low noise and high PSRR, as well as low dropout and low quiescent currents in battery-powered systems. The PL0300/P PSRR is 68dB at 100Hz and 60dB at 10KHz. When operating from sources other than batteries, improved supply-noise rejection and transient response can be achieved by increasing the values of the input and output bypass capacitors and through passive filtering techniques. Dropout Voltage A regulator’s minimum dropout voltage determines the lowest usable supply voltage. In battery-powered systems, this determines the useful end-of-life battery voltage. Because the PL0300/P uses a P-channel MOSFET pass transistor, its dropout voltage is a function of drainto-source on resistance (RDSON) multiplied by the load current. Noise Reduction For the PL0300/P, an external 0.01μF bypass capacitor between BYP and GND with innovative noise bypass scheme reduces the output noises dramatically, exhibiting 70μV(RMS) of output voltage noise with CBYP = 0.01μF and COUT = 10μF. July 2007 www.picsemi.com © 2007 Power IC. All Rights Reserved. 10 PL0300 PACKAGE INFORMATION 5-PIN SOT-25 OUTLINE DIMENSION D Detail A b 4 E E1 5 1 e c 3 1 R R θ A A2 1 L2 e1 L θ A1 θ L1 1 Detail A Dimension: Symbol A A1 A2 b c D E E1 e e1 L L1 L2 R R1 θ˚ θ1˚ July 2007 Min 0.90 0.30 0.08 0.30 0.10 0.10 0˚ 5˚ Millimeter Typ 1.15 2.90 2.80 1.60 0.95 1.90 0.45 0.60 0.25 4˚ 10˚ Max 1.45 0.15 1.30 0.50 0.22 Min 0.036 0.011 0.003 0.60 0.020 0.25 8˚ 15˚ 0.004 0.004 0˚ 5˚ www.picsemi.com © 2007 Power IC. All Rights Reserved. Inch Typ 0.045 0.114 0.110 0.063 0.037 0.075 0.018 0.024 0.010 4˚ 10˚ Max 0.057 0.006 0.051 0.020 0.009 0.024 0.010 8˚ 15˚ 11 PL0300 DISCLAIMERS LIFE SUPPORT Power IC’s products are NOT designed to be used as components in devices intended to support or sustain human life. The use of Power IC’s products in components intended for surgical implants into the body or other applications, in which failure of Power IC’s products could create a situation where personal death or injury may occur, is NOT authorized without the express written approval of Power IC’s Chief Executive Officer. Power IC will NOT be held liable for any damages or claims resulting from the use of its products in medical applications. MILITARY Power IC’s products are NOT designed for use in military applications. The use of Power IC’s products in military applications is NOT authorized without the express written approval of Power IC’s Chief Executive Officer. Power IC will NOT be held liable for any damages or claims resulting from the use of its products in military applications. RIGHT TO MAKE CHANGES Power IC reserves the right to change this document and/or this product without notice. Customers are advised to consult their Power IC sales representative before ordering. July 2007 www.picsemi.com © 2007 Power IC. All Rights Reserved. 12