(Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO FEATURES 16 SEL0^ XIN 2 15 SEL1^ XOUT 3 14 GNDBUF SEL2^ 4 13 QBAR OE_CTRL 5 12 VDDBUF VCON 6 11 Q GNDANA 7 10 GNDBUF LP 8 9 LM OE_CTRL 15 VCON 16 SEL1^ 14 SEL0^ SEL2^ 11 10 9 PL580-3X 1 2 3 4 LM The PL580-3X is a monolithic low jitter and low phase noise VCXO, capable of 0.4ps RMS phase jitter and CMOS, LVDS, or PECL outputs, covering a wide frequency output range up to 320MHz. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. The frequency selector pads of PL580-3X enable output frequencies of (2, 4, 8, or 16) * F XIN . The PL580-3X is designed to address the demanding requirements of high performance applications such as SONET, GPS, Video, etc. 12 13 GNDBUF DESCRIPTION XOUT VDDANA 16-pin TSSOP XIN • • • • • • • • 1 PL580-3X • VDDANA LP • Less than 0.4ps RMS (12KHz-20MHz) phase jitter for all frequencies . Less than 25ps (typ.) peak to peak jitter for all frequencies. Low phase noise output (@ 1MHz frequency offset ∗ -144dBc/Hz for 155.52MHz ∗ -140dBC/Hz for 311.04MHz 19MHz-40MHz crystal input. 38MHz-320MHz output. Available in PECL, LVDS, or CMOS outputs. No external varicap required. Output Enable selector. Wide pull range (+/-200ppm). 3.3V operation. Available in 3x3 QFN or 16-pin TSSOP packages. GNDANA • PACKAGE PIN ASSIGNMENT 8 GNDBUF 7 QBAR 6 VDDBUF 5 Q 3x3 QFN Note1: QBAR is used for single ended CMOS output. Note2: ^ Denotes internal pull up resistor. BLOCK DIAGRAM VCON VARICAP XIN XOUT XTAL OSC VCO Divider Phase Detector Charge Pump + Loop Filter VCO (F XiN x16) Performance Tuner Output Divider (1,2,4,8) QBAR Q OE 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 1 (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO OUTPUT ENABLE LOGICAL LEVELS Part # PL580-38 (PECL) PL580-35 (PECL) PL580-37 (CMOS) PL580-39 (LVDS) OE State 0 (Default) Output enabled 1 Tri-state 0 Tri-state 1 (Default) Output enabled PIN DESCRIPTIONS TSSOP Pin number 3x3mm QFN Pin number Type VDDANA 1 11 P VDD for analog Circuitry. XIN 2 12 I Crystal input pin. (See Crystal Specifications on page 4). XOUT 3 13 O Crystal output pin. (See Crystal Specifications on page 4). SEL2 4 14 I Output frequency Selector pin. OE_CTRL 5 15 I Output enable control pin. (See OE_CTRL Logic Levels). VCON 6 16 I Voltage control input. GNDANA 7 1 P Ground for analog circuitry. LP 8 2 - LM 9 3 - GNDBUF 10 4 P GND connection for output buffer circuitry. Q 11 5 O PECL or LVDS output. VDDBUF 12 6 P VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. QBAR 13 7 O Complementary PECL, LVDS, Or single ended CMOS output. GNDBUF 14 8 P GND connection for output buffer circuitry. SEL1 15 9 I Output frequency Selector pin. SEL0 16 10 I Output frequency Selector pin. Name Description Tuning inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between LP and adjacent LM pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 2 (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO FREQUENCY SELECTION TABLE SEL2 SEL1 SEL0 Selected Multiplier/Output Frequency 0 0 0 VCO Max* 0 0 1 VCO Min* 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Fin x 2 1 0 1 Fin x 8 1 1 0 Fin x 16 1 1 1 Fin x 4 All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0. * Special Test Modes to help selecting the inductor value for the target output frequency. PERFORMANCE TUNING & INDUCTOR VALUE SELECTION Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor values for your application. In addition, the chart below could be used as a reference for quick inductor value selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance enhancement of your custom board design, please follow the following instruction: Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max” represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock in the middle of its tuning range with maximum margin on either side. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 3 (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR SYMBOL CONDITIONS MIN. F XIN Parallel Fundamental Mode at VCON = 0V at VCON = 1.65V at VCON = 3.3V AT cut AT cut 19 C L (xtal) C 0 /C 1 (xtal) RE TYP. MAX. UNITS 40 MHz 17.7 9.5 5.4 pF 250 30 Ω Note: Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note, that frequency pulling and oscillator gain may decrease. 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity VCON pin input impedance VCON modulation BW SYMBOL T VCXOSTB CONDITIONS From power valid F XIN = 19 – 40MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V MIN. TYP. MAX. UNITS 10 ms 500 ppm 150 ppm ppm/V % ±200 10 0V ≤ VCON ≤ 3.3V, -3dB 60 25 80 kΩ kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 4 (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current, Dynamic (with Loaded Outputs) Operating Voltage I DD CONDITIONS PECL/LVDS/CMOS MIN. MAX. 38MHz<Fout<100MHz 65/45/30 100MHz<Fout<320MHz 80/60/40 2.97 45 45 45 V DD @ 50% V DD (CMOS) @ 1.25V (LVDS) @ V DD – 1.3V (PECL) Output Clock Duty Cycle TYP. Short Circuit Current 50 50 50 3.63 55 55 55 ±50 UNITS mA V % mA Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load. 5. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS 155.52MHz 311.04MHz 0.4 0.4 0.5 0.5 ps Integrated jitter RMS Integrated 12 kHz to 20 MHz Period jitter RMS With capacitive decoupling between VDD and GND. Over 10,000 cycles. 77.76MHz 155.52MHz 2.5 3 4 5 311.04MHz 4 7 With capacitive decoupling between VDD and GND. Over 10,000 cycles. 77.76MHz 155.52MHz 18 20 30 30 311.04MHz 25 35 Period jitter Peak-toPeak ps ps 6. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier (typical) FREQ. @10Hz @100Hz @1kHz @10kHz @100kHz @1M @10M 77.76MHz -66 -96 -124 -134 -132 -145 -149 155.52MHz -62 -92 -120 -132 -128 -144 -150 311.04MHz -59 -86 -116 -129 -124 -140 -148 UNITS dBc/Hz Note: Phase Noise measured at VCON = 0V. 7. CMOS Electrical Characteristics PARAMETERS Output drive current SYMBOL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V MIN. TYP. 30 30 MAX. UNITS mA mA Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 0.7 ns Output Clock Rise/Fall Time 20%-80% with 50Ω Load 0.3 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 5 (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO 8. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV ΔV OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 Ω (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change ΔV OS 0 3 25 mV Power-off Leakage I OXD ±1 ±10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND V DD = 0V V 9. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 6 (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO 10. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 11. PECL Switching Characteristics PARAMETERS SYMBOL FREQ. Clock Rise & Fall Times CONDITIONS <150MHz tr & tf @20/80% - PECL @80/20% - PECL >150MHz <320MHz Clock Rise & Fall Times PECL Levels Test Circuit OUT TYP. MAX. 0.2 0.5 0.7 UNITS ns 0.2 0.4 0.55 PECL Output Skew OUT VDD 50Ω MIN. 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 7 (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO LAYOUT RECOMMENDATIONS PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to PL580 as short as possible, as well as keeping all other traces as far away from it as possible. - Place the crystal as close as possible to both crystal pins of the device. This will reduce the cross-talk between the crystal and the other signals. - Separate crystal pin traces from the other signals on the PCB, but allow ample distance between the two crystal pin traces. - Place a 0.01µF~0.1µF decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or ‘stripline’, to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually ‘striplines’ are designed for 50Ω impedance and CMOS outputs usually have lower than 50Ω impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the ‘stripline’ trace. - Please contact PhaseLink for the application note on how to design outputs driving long traces or the Gerber files for the PL580 layout. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 8 (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO PACKAGE INFORMATION 16-PIN SSOP 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 C e B L 16-PIN 3x3 QFN 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 9 (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL580-3X X C L R PART NUMBER R= TAPE & REEL NONE= TUBE L= GREEN PACKAGE NONE= REGULAR PACKAGE PACKAGE TYPE O=TSSOP-16L Q= QFN-16L Order Number PL580-35OCL PL580-35OCL-R PL580-35QCL PL580-35QCL-R PL580-37OCL PL580-37OCL-R PL580-37QCL PL580-37QCL-R PL580-38OCL PL580-38OCL-R PL580-38QCL PL580-38QCL-R PL580-39OCL PL580-39OCL-R PL580-39QCL PL580-39QCL-R TEMPERATURE C=COMMERCIAL I=INDUSTRAL Marking Package Option P580-35OCL P580-35OCL P580-35QCL P580-35QCL P580-37OCL P580-37OCL P580-37QCL P580-37QCL P580-38OCL P580-38OCL P580-38QCL P580-38QCL P580-39OCL P580-39OCL P580-39QCL P580-39QCL TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package) TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package) TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package) TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 10