PLL130-07 High Speed Translator Buffer to CMOS (Selectable Drive) FEATURES • • CMOS output Selectable Drive capability (15pF or 30pF output load). Single AC coupled input (min. 100mV swing). Input range from DC to 200 MHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC and 3x3mm QFN. (TOP VIEW) GND 1 REF_IN 2 GND 3 VDD 4 PLL130-07 • • • • PIN CONFIGURATION 8 DRIV_SEL^ 7 VDD 6 GND 5 CLK_OUT VDD VDD GND 12 11 10 9 14 GND 15 OE^ 16 PLL130-07 1 2 3 4 GND GND REF_IN 13 GND DRIV_SEL^ GND The PLL130-07 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 200MHz. It provides CMOS output with 15pF output load drive capability. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion from sine wave to CMOS. VDD DESCRIPTION 8 CLK_OUT 7 VDD 6 N/C 5 GND Note: ^ denotes internal pull up BLOCK DIAGRAM REF_IN Input Amplifier CLK_OUT 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1 PLL130-07 High Speed Translator Buffer to CMOS (Selectable Drive) PIN DESCRIPTION Name 8pin SOIC Pin number GND 1,3,6 VDD 3x3mm QFN Pin number Type Description P Ground. 4,7 1,2,4,5, 9,14,15 7,10,11,12 P DRIV_SEL 8 13 I REF_IN 2 3 I CLK_OUT OE 5 N/A 8 16 O I Power supply. Drive Select input: ‘1’ for standard drive, ‘0’ for hi-drive output. Internal pull-up (default is ‘1’). Reference input signal. The frequency of this signal will be reproduced at the output (after translation to CMOS level). CMOS clock output. Output enable (‘1’ for enable). Internal pull-up (default is ‘1’). ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model V DD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. AC Specifications PARAMETERS Input Frequency Input signal swing Output Frequency CONDITIONS REF_IN input MIN. 0 100 0 TYP. MAX. UNITS 200 MHz mV MHz 200 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2 PLL130-07 High Speed Translator Buffer to CMOS (Selectable Drive) 3. CMOS Output Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage Output Low Voltage Output High Voltage at CMOS level V OH V OL I OH = -12mA I LO = 12mA 2.4 V OHC I OH = -4mA V DD – 0.4 At TTL level (High drive*) At TTL level (Standard drive) Output drive current TYP. MAX. UNITS 0.4 V V V 36 12 51 17 MIN. TYP. mA mA * Note: High Drive CMOS is selectable through DRIV_SEL selector input on pin 8(SOIC) or 13(QFN). 4. CMOS Switching Characteristics PARAMETERS Output Clock Rise/Fall Time Output Clock Rise/Fall Time (High Drive*) SYMBOL CONDITIONS 0.8V 0.3V 0.8V 0.3V ~ ~ ~ ~ 2.0V 3.0V 2.0V 3.0V with with with with 10 15 10 15 pF pF pF pF load load load load 1.15 3.7 0.5 1.5 MAX. UNITS ns * Note: High Drive CMOS is selectable through DRIV_SEL selector input on pin 8(SOIC) or 13(QFN). 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 3 PLL130-07 High Speed Translator Buffer to CMOS (Selectable Drive) PACKAGE INFORMATION 8 PIN ( dimensions in mm ) Narrow SOIC Symbol Min. Max. A 1.47 1.73 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 4.95 E 3.80 4.00 H 5.80 6.20 L 0.38 e 1.27 1.27 BSC E H D A A 1 C L e B 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 4 PLL130-07 High Speed Translator Buffer to CMOS (Selectable Drive) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL130-07 x C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE S=SOIC; Q=QFN Order Number Marking Package Option PLL130-07QC-R PLL130-07QC PLL130-07SC-R PLL130-07SC P130-07QC P130-07QC P130-07SC P130-07SC QFN - Tape and Reel QFN - Tube SOIC -Tape and Reel SOIC - Tube PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 5