PLL502-26 High Pull-Range VCXO (27MHz) with integrated Audio PLL FEATURES • • • • • Low phase noise 27MHz VCXO (-135 dBc at 10kHz offset). Integrated variable capacitors. Wide pull range (+/- 250 ppm). Low jitter (RMS): 10ps period. Integrated audio Phase Locked Loop. Audio clock output (ideal for 8.192MHz, 11.2896MHz, 12.288MHz). 27MHz crystal input. Audio Reference clock input. 3.3V operation. Available in 16-Pin SOIC. DESCRIPTION N/C* 1 VDD_PLL 2 VDD_VCXO 3 XIN 4 XOUT 5 VCON 6 GND_VCXO 7 GND_PLL 8 PLL502-26 • • • • • PIN CONFIGURATION 1 6 1 5 1 4 1 3 1 2 1 1 1 0 N/C* 9 REF_Audio GND_27MHz OUT_27MHz VDD_27MHz VDD_Audio OUT_Audio GND_Audio Note: * Pins reserved for future DAC integration The PLL502-26 is a low cost, high pull-range and low phase noise VCXO, providing less than -135dBc at 10kHz offset at 27MHz. It also integrates an Audio clock phase locked loop ideal for the 8.192MHz, 11.2896MHz and 12.288MHz audio outputs, starting from an audio reference clock. Its very high pull range makes it ideal for Digital Video applications, allowing users to save board space and cost. OUTPUT RANGE OUTPUT FREQUENCY RANGE VCXO Audio 27MHz 8.192MHz – 12.288MHz OUTPUT TYPE CMOS CMOS BLOCK DIAGRAM VCON VARICAP XIN XOUT XTAL OSC OUT_27MHz 10X PLL OUT_Audio REF_Audio 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 1 PLL502-26 High Pull-Range VCXO (27MHz) with integrated Audio PLL PIN DESCRIPTIONS Name Number Type Description N/C 1,16 VDD_PLL 2 P VDD power supply pin for PLL circuitry. This pin should be decoupled separately from other VDD. VDD_VCXO 3 P VDD power supply pin for VCXO circuitry. This pin should be decoupled separately from other VDD. XIN 4 I Crystal input. See Crystal Specifications on page 4. XOUT 5 O Crystal output. See Crystal Specifications on page 4. VCON 6 I Voltage Control input. GND_VCXO 7 P GND connection for VCXO circuitry. GND_PLL 8 P GND connection for VCXO circuitry. REF_Audio 9 I Audio Reference Clock input. GND_Audio 10 P GND connection for Audio clock output buffer circuitry. OUT_Audio 11 O Audio clock output. VDD_Audio 12 P VDD power supply pin for Audio clock output buffer. This pin should be decoupled separately from other VDD. VDD_27MHz 13 P VDD power supply pin for 27MHz output clock. This pin should be decoupled separately from other VDD. OUT_27MHz 14 O 27MHz VCXO output clock. GND_27MHz 15 P GND connection for 27MHz output buffer circuitry. No connection. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 2 PLL502-26 High Pull-Range VCXO (27MHz) with integrated Audio PLL 2. AC Electrical Specifications PARAMETERS Input Crystal Frequency Audio Reference Clock Output Clock Rise/Fall Time Output Clock Duty Cycle SYMBOL CONDITIONS MIN. REF_Audio 45 27 2 50 MIN. TYP. 0.65 0.3V ~ 3.0V with 15 pF load Measured @ 50% V DD TYP. MAX. UNITS 55 MHz MHz ns % MAX. UNITS 1.5 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity VCON pin input impedance VCON modulation BW SYMBOL T VCXOSTB CONDITIONS From power valid F XIN = 12 – 27MHz; XTAL C 0 /C 1 < 250 0V ≤ VIN ≤ 3.3V VCON=1.65V ±1.65V 10 ms 500 ppm 150 ppm ppm/V % ±250 10 2000 25 0V ≤ VIN ≤ 3.3V, -3dB kΩ kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. Jitter and Phase Noise Specification PARAMETERS RMS Period Jitter (1 sigma – 10,000 samples) Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier CONDITIONS with capacitive decoupling between VDD and GND. 27MHz @100Hz offset 27MHz @1kHz offset 27MHz @10kHz offset 27MHz @100kHz offset 27MHz @1MHz offset MIN. TYP. MAX. UNITS 3 ps -85 -115 -135 -140 -150 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 3 PLL502-26 High Pull-Range VCXO (27MHz) with integrated Audio PLL 5. DC Specification PARAMETERS SYMBOL Supply Current, Dynamic, with Loaded Outputs Operating Voltage I DD V DD I OH I OL Output drive current Short Circuit Current VCXO Control Voltage CONDITIONS MIN. F XIN = 12 - 27MHz Ouput load of 10pF V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V TYP. MAX. UNITS 30 35 mA 3.63 V mA mA mA V 2.97 10 10 ±50 VCON 0 3.3 6. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Capacitance Rating C0/C1 ESR SYMBOL F XIN C L (xtal) RS MIN. TYP. MAX. 27 9.5 250 30 UNITS MHz pF Ω Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 4 PLL502-26 High Pull-Range VCXO (27MHz) with integrated Audio PLL PACKAGE INFORMATION 16 PIN Narrow SOIC ( mm ) SOIC E Symbol Min. Max. A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 9.80 10.00 E 3.80 4.00 H 5.80 6.20 L 0.40 e 1.27 1.27 BSC H D A A1 C e L B ORDERING INFORMATION PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL502-26 S C PART NUMBER TEMPERATURE C=COMMERCIAL PACKAGE TYPE S=SOIC Order Number Marking Package t PLL502-26SC PLL502-26SC-R P502-26SC P502-26SC SOIC - Tube SOIC (Tape & Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 5