PLL520-28/-29 Low Phase Noise VCXO (for 120-200MHz Fund Xtal) FEATURES VDD 1 16 N/C XIN 2 15 N/C XOUT 3 14 GND N/C 4 13 CLKC N/C 5 12 VDD OE 6 11 CLKT VCON 7 10 N/C GND 8 9 N/C VDD N/C N/C XIN 12 13 11 10 9 N/C 15 OE 16 BLOCK DIAGRAM P520-2x 1 2 3 4 GND 14 GND XOUT GND The PLL520-28/-29 are a family of VCXO IC’s specifically designed to pull high frequency fundamental crystals. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input. Their very low jitter makes them ideal for the most demanding timing requirements. VDD DESCRIPTION VCON 120MHz to 200MHz Fundamental Mode Crystal. Output range: 120 – 200MHz (no PLL). Low Injection Power for crystal 50uW. Sub 0.5pS RMS phase jitter ( 12kHz to 20MHz ). PECL (PLL520-28) or LVDS output (PLL520-29). Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3mm QFN). PLL 520-2x • • • • • • • • PIN CONFIGURATION (Top View) 8 GND 7 CLKC 6 VDD 5 CLKT OE VCON Oscillator XIN XOUT Amplifier w/ integrated varicaps Q Q OUTPUT ENABLE LOGICAL LEVELS Part # PLL520-28 PLL520-29 PLL520-28/-29 OE 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled OE input: Logical states defined by PECL levels for PLL520-28 Logical states defined by CMOS levels for PLL520-29 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1 PLL520-28/-29 Low Phase Noise VCXO (for 120-200MHz Fund Xtal) PIN DESCRIPTIONS Name TSSOP Pin number 3x3mm QFN Pin number Type XIN 2 13 I Crystal input. See Crystal Specifications on page 2. XOUT 3 14 I Crystal output. See Crystal Specifications on page 2. OE 6 16 I Output enable pin. See Output Enable Logic Levels on page 1. VCON 7 1 I Voltage control input. GND 8, 14 2,3,4,8 P Ground. CLKT 11 5 O True output PECL (PLL520-28) or LVDS (PLL520-29) CLKC 13 7 O Complementary output PECL (PLL520-28) or LVDS (PLL520-29). N/C 4,5,9,10,15,16 9,10,15 - Not connected. VDD 1, 12 6,11,12 P +3.3V power supply. Description ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model V DD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation Frequency SYMBOL CONDITIONS CX+ CXC0 120MHz to 200MHz (VDD=3.3V) γ OF Fund. MIN. MAX. 120 2 2 2 300 200 UNITS pF MHz 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PLL520-28/-29 Low Phase Noise VCXO (for 120-200MHz Fund Xtal) 3. Voltage Control Crystal Oscillator (3.3V) PARAMETERS SYMBOL VCXO Stabilization Time * T VCXOSTB CONDITIONS MIN. From power valid F XIN = 100 – 200MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V VCON = 0 to 3.3V VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW TYP. MAX. UNITS 10 ms 200* ppm ±100* 4 – 18* 10* 65 60 0V ≤ VCON ≤ 3.3V, -3dB ppm pF % ppm/V kΩ kHz 25 Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current (Loaded Outputs) Operating Voltage I DD CONDITIONS MIN. TYP. PECL/LVDS V DD 2.97 45 45 @ 1.25V (LVDS) @ V DD – 1.3V (PECL) Output Clock Duty Cycle 50 50 ±50 Short Circuit Current MAX. UNITS 100/80 mA 3.63 55 55 V % mA 5. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. Period jitter RMS Period jitter peak-to-peak At 155.52MHz, with capacitive decoupling between VDD and GND. 2.5 18.5 Accumulated jitter RMS At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz 2.5 Accumulated jitter peak-to-peak Integrated jitter RMS at 155MHz MAX. UNITS ps ps 24 0.3 ps 6. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier FREQUENCY 155.52MHz @10Hz @100Hz @1kHz @10kHz @100kHz UNITS -75 -95 -125 -140 -145 dBc/Hz Note: Phase Noise measured at VCON = 0V 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PLL520-28/-29 Low Phase Noise VCXO (for 120-200MHz Fund Xtal) 7. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change ∆V OD V OH V OL V OS Power-off Leakage I OXD Output Short Circuit Current I OSD CONDITIONS V OD R L = 100 Ω (see figure) MIN. TYP. MAX. UNITS 247 -50 355 454 50 1.6 0.9 1.125 0 ∆V OS V out = V DD or GND V DD = 0V 1.4 1.1 1.2 3 1.375 25 mV mV V V V mV ±1 ±10 uA -5.7 -8 mA 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4 PLL520-28/-29 Low Phase Noise VCXO (for 120-200MHz Fund Xtal) 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. V OH V OL R L = 50 Ω to (V DD – 2V) (see figure) V DD – 1.025 Output High Voltage Output Low Voltage MAX. UNITS V DD – 1.620 V V 10. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time tr tf CONDITIONS MIN. @20/80% - PECL @80/20% - PECL PECL Levels Test Circuit OUT MAX. UNITS 0.6 0.5 1.5 1.5 ns ns PECL Output Skew VDD 50Ω TYP. OUT 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5 PLL520-28/-29 Low Phase Noise VCXO (for 120-200MHz Fund Xtal) PACKAGE INFORMATION 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 C e B L 3x3mm QFN 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6 PLL520-28/-29 Low Phase Noise VCXO (for 120-200MHz Fund Xtal) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL520-2x O C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE O=TSSOP Q=QFN Order Number Marking Package Option PLL520-28OC PLL520-28OC-R PLL520-28QC PLL520-28QC-R P520-28OC P520-28OC P520-28QC P520-28QC TSSOP - Tube TSSOP - Tape & Reel QFN - Tube QFN - Tape & Reel PLL520-29OC PLL520-29OC-R PLL520-29QC PLL520-29QC-R P520-29OC P520-29OC P520-29QC P520-29QC TSSOP - Tube TSSOP - Tape & Reel QFN - Tube QFN - Tape & Reel PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7