TI TIB82S105BC

TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
•
•
•
•
•
•
N PACKAGE
50-MHz Clock Rate
(TOP VIEW)
Power-On Preset of All Flip-Flops
CLK
I7
I6
I5
I4
I3
I2
I1
I0
Q7
Q6
Q5
Q4
GND
6-Bit Internal State Register With 8-Bit
Output Register
Power Dissipation . . . 600 mW Typical
Programmable Asynchronous Preset or
Output Control
Functionally Equivalent to, but Faster Than
82S105A†
description
The TIB82S105BC is a TTL field-programmable
state machine of the Mealy type. This state
machine (logic sequencer) contains 48 product
terms (AND terms) and 14 pairs of sum terms (OR
terms). The product and sum terms are used to
control the 6-bit internal state register and the 8-bit
output register.
The state and output registers are positive-edgetriggered S/R flip-flops. These registers are
unconditionally preset high during power up.
Pin19 can be used to preset both registers or, by
blowing the proper fuse, be converted to an output
control function.
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
I8
I9
I10
I11
I12
I13
I14
I15
PRE/OE
Q0
Q1
Q2
Q3
I5
I6
I7
CLK
VCC
I8
I9
FN PACKAGE
(TOP VIEW)
I4
I3
I2
I1
I0
Q7
Q6
4
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I10
I11
I12
I13
I14
I15
PRE/OE
Q5
Q4
GND
Q3
Q2
Q1
Q0
The outputs of the internal state register (P0 – P5)
are fed back and combined with the 16 inputs
(I0 – I15) to form the AND array. In addition a single
sum term is complemented and fed back to the
AND array, which allows any of the product terms
to be summed, complemented, and used as an
input to the AND array.
1
The TIB82S105BC is characterized for operation
from 0°C to 75°C.
† Power-up preset and asynchronous preset functions are not identical to 82S105A. See Recommended Operating Conditions.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
functional block diagram (positive logic)
PRE/OE
EN
S
C1
CLK
≥1
48 x 29
&
45 x 48
I0 – I15
16 x
16
16
8
1S
8
8x
I=1
8
1R
16
48
6x
C1
6
S
6
6
6
1S
6
1R
6
denotes fused inputs
timing diagram
VCC
PRE
tsu
Optional
OE
I0 – I15
tsu
CLK
Internal
State Registers
P0 – P5
Q0 – Q7
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6x
I=1
Q0 – Q7
TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
logic diagram (positive logic)
9
8
7
6
5
4
3
2
27
26
25
24
23
22
21
20
0
74
518
592
1110
1184
1702
1776
2294
2368
2886
P
2960
3478
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
First Fuse Number
Increment
0
Actual Fuse
Number
4
8
12
3552
I
16
19
20
PRE/OE
24
P
E
28
32
P0
P1
P2
P3
P4
P5
36
40
44
C
1S
C1
1R S
48
1S
C1
1R S
1S
C1
1R S
52
N
1S
C1
1R S
1S
C1
1R S
56
1S
C1
1R S
1S
C1
1R S
60
1S
C1
1R S
1S
C1
1R S
64
Q
1S
C1
1R S
1S
C1
1R S
68
1S
C1
1R S
1S
C1
1R S
72
73
1S
C1
1R S
P0
P1
P2
P3
P4
P5
18
Q0
17
Q1
16
Q2
15
Q3
13
Q4
12
Q5
11
Q6
10
Q7
1
CLK
NOTES: 1. All AND gate inputs with a blown link float to the high level.
2. All OR gate inputs with a blown link float to the low level.
3. Fuse numbers = First fuse number + Increment
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3
TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 4: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
Low-level output current
High-level input voltage
NOM
MAX
UNIT
5
5.25
V
5.5
V
2
0.8
High-level output current
fclock
Clock frequency†
tw
Pluse duration
tsu
Setup time before CLK↑,
1 thru 48 product terms
tsu
th
MIN
4.75
mA
24
mA
1 thru 48 product terms without C-array ‡
0
50
1 thru 48 product terms with C-array
0
30
Clock high or low
10
Preset
15
Without C-array
15
With C-array
30
V
– 3.2
MHz
ns
ns
Setup time, Preset low (inactive) before CLK↑§
8
ns
Hold time, input after CLK↑
0
ns
TA
Operating free-air temperature
0
25
75
°C
† The maximum clock frequency is independent of the internal programmed configuration. If an output is fed back externally to an input, the
maximum clock frequency must be calculated.
‡ The C-array is the single sum term that is complemented and fed back to the AND array.
§ After Preset goes inactive, normal clocking resumes on the first low-to-high clock transition.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
II = – 18 mA
IOH = – 3.2 mA
VOL
IOZH
VCC = 4.75 V,
VCC = 5.25 V,
IOL = 24 mA
VO = 2.7 V
IOZL
II
VCC = 5.25 V,
VCC = 5.25 V,
VO = 0.4 V
VI = 5.5 V
IIH
IIL
IO‡
VCC = 5.25 V,
VCC = 5.25 V,
VI = 2.7 V
VI = 0.4 V
VCC = 5.25 V,
VCC = 5.25 V,
PRE/OE at GND,
VO = 2.25 V
VI = 4.7 V,
Outputs open
ICC
MIN
2.4
TYP†
MAX
UNIT
– 1.2
V
3
0.37
– 30
120
V
0.5
V
20
µA
–20
µA
25
µA
20
µA
– 0.25
mA
–112
mA
180
mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FROM
(INPUT)
fmax§
TO
(OUTPUT)
MIN
TYP†
Without C array
50
70
With C array
30
45
TEST CONDITION
MAX
UNIT
MHz
tpd
tpd
CLK↑
Q
R1 = 500 Ω,
8
15
ns
PRE↑
Q
R2 = 500 Ω,
12
20
ns
tpd
VCC↑
Q
See Figure 5
0
10
ns
ten
tdis
OE↓
Q
10
20
ns
OE↑
Q
5
10
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions hace been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
§ fmax is independent of the internal programmed configuration and the number of product terms used.
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
Programmable Logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
POST OFFICE BOX 655303
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5
TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
diagnostics
A diagnostics mode is provided with these devices that allows the user to inspect the contents of the state
register. When I0 (pin 9) is held at 10 V, the state register bits P0 – P5 will appear at the Q0 – Q5 outputs and
Q6 – Q7 will be high. The contents of the output register will remain unchanged.
VIH
I1 – I15
VIL
10 V
8V
VIH
I0
VIL
th
VIH
CLK
VIL
tsu
Internal
State Register
tw
VOH
PS
NS
VOL
P0 – P5
tpd
tpd
VOH
Q0 – Q7
Qn
Qn + 1
Qn + 1
VOL
tpd
Optional
OE
0V
PS = Present state, NS = Next state
Figure 1. Diagnostic Waveforms
6
NS
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• DALLAS, TEXAS 75265
TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
test array
A test array that consists of product lines 48 and 49 has been added to these devices to allow testing prior to
programming. The test array is factory programmed as shown in Table 1. Testing is accomplished by connecting
Q0 – Q7 to I8 – I15, PRE/OE to GND, and applying the proper input signals as shown in Figure 2. Product lines
48 and 49 must be deleted during user programming to avoid interference with the programmed logic function.
Table 1. Test Array Program
OPTION PRE/OE
AND
INPUT
(In)
PRODUCT
LINE
H
OR
PRESENT STATE
(PS)
NEXT STATE
(NS)
OUT
(Qn)
C C 1 1 1 1 1 1
5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0
48
X – H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L
49
– X L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H
5V
VCC
0V
tw
VIH
CLK
VIL
tsu
th
VIH
I0 – I7
VIL
tpd
tpd
tpd
VOH
Q0 – Q7
VOL
Internal
State Register
HIGH
P0 – P5
LOW
Figure 2. Test Array Waveforms
Table 2. Test Array Deleted
OPTION PRE/OE
AND
INPUT
(In)
PRODUCT
LINE
H
OR
PRESENT STATE
(PS)
NEXT STATE
(NS)
OUT
(Qn)
C C 1 1 1 1 1 1
5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0
48
– – H H H H H H H H H H H H H H H H H H H H H H – – – – – – – – – – – – – –
49
– X L L L L L L L L L L L L L L L L L L L L L L – – – – – – – – – – – – – –
X = Fuse intact, – = Fuse blown
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7
TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
TIB82S105B, 82S105A COMPARISON
The Texas Instruments TIB82S105B is a 16 × 48 × 8 Field-Programmable Logic Sequencer that is functionally
equivalent to the Signetics 82S105A. However, the TIB82S105B is designed for a maximum speed of 50 MHz with
the preset function being made conventional. As a result the TIB82S105B differs from the 82S105A in speed and in
the preset recovery function.
The TIB82S105B is a high-speed version of the original 82S105A. The TIB82S105B features increased switching
speeds with no increase in power. The maximum operating frequency is increased from 20 MHz to 50 MHz and does
not decrease as more product terms are connected to each sum (OR) line. For instance, if all 48 product tems were
connected to a sum line on the original 82S105A, the fmax would be about 15 MHz. The fmax for the TIB82S105B
remains at 50 MHz regardless of the programmed configuration. In addition, the preset recovery sequence was
changed to a conventional recovery sequence, providing quicker clock recovery times. This is explained in the
following paragraph.
The TIB82S105B and the 82S105A are equipped with power-up preset and asynchronous preset functions. The
power-up preset causes the registers to go high during power up. The asynchronous preset inhibits clocking and
causes the registers to go high whenever the preset pin is taken high. After a power-up preset occurs, the minimum
setup time from power up to the first clock pulse must be met in order to assure that clocking is not inhibited. In a similar
manner after an asynchronous preset, the preset input must return low (inactive) for a given time, tsu, before clocking.
The Signetics 82S105A was designed in such a way that after both power-up preset and asynchronous preset it
requires that a high-to-low clock transition occur before a clocking transition (low-to-high) will be recognized. This is
shown in Figure 3. The Texas Instruments TIB82S105B does not require a high-to-low clock transition before clocking
can be resumed, it only requires that the preset be inactive 8 ns (preset inactive-state setup time) before the clock
rising edge. See Figure 4.
The TIB82S105B, with an fmax of 50 MHz, is ideal for systems in which the state machine must run several times faster
than the system clock. It is recommended that the TIB82S105B be used in new designs. However, if the TIB82S105B
is used to replace the 82S105A, then the customer must understand that clocking will begin with the first
clock rising edge after preset.
Table 3. Speed Differences
PARAMETER
fmax
tpd, CLK to Q
8
82S105A
SIGNETICS
TIB82S105B
TI ONLY
20 MHz
50 MHz
20 ns
15 ns
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• DALLAS, TEXAS 75265
TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
VCC
tsu
tsu
PRE
CLK
Registers
Figure 3. 82S105A Preset Recovery Operation
VCC
tsu
PRE
CLK
Registers
Figure 4. TIB82S105B Preset Recovery Operation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TIB82S105BC
16 × 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
5V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3.5 V
Timing
Input
1.5 V
3.5 V
High-Level
Pulse
1.5 V
1.5 V
0.3 V
0.3 V
tw
th
tsu
3.5 V
Data
Input
1.5 V
1.5 V
0.3 V
(see Note B)
3.5 V
Low-Level
Pulse
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
3.5 V
1.5 V
Input
1.5 V
0.3 V
tpd
tpd
In-Phase
Output
1.5 V
VOH
1.5 V
VOL
tpd
tpd
Out-of-Phase
Output
(see Note D)
1.5 V
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
0.3 V
(see Note B)
Output
Control
(low-level
enabling)
1.5 V
1.5 V
0.3 V
(see Note B)
ten
tdis
≈ 3.3 V
Waveform 1
S1 Closed
(see Note C)
1.5 V
VOL + 0.5 V
VOL
tdis
ten
Waveform 2
S1 Open
(see Note C)
VOH
1.5 V
VOH – 0.5 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 5. Load Circuit and Voltage Waveforms
10
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TIB82S105BCFN
OBSOLETE
PLCC
FN
28
TBD
Call TI
Call TI
TIB82S105BCN
OBSOLETE
PDIP
N
28
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI008 – OCTOBER 1994
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
A
24
13
0.560 (14,22)
0.520 (13,21)
1
12
0.060 (1,52) TYP
0.200 (5,08) MAX
0.610 (15,49)
0.590 (14,99)
0.020 (0,51) MIN
Seating Plane
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.125 (3,18) MIN
0.010 (0,25) M
PINS **
0°– 15°
0.010 (0,25) NOM
24
28
32
40
48
52
A MAX
1.270
(32,26)
1.450
(36,83)
1.650
(41,91)
2.090
(53,09)
2.450
(62,23)
2.650
(67,31)
A MIN
1.230
(31,24)
1.410
(35,81)
1.610
(40,89)
2.040
(51,82)
2.390
(60,71)
2.590
(65,79)
DIM
4040053 / B 04/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MS-011
Falls within JEDEC MS-015 (32 pin only)
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MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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