POWER LP3981

Preliminary
Datasheet
LP3981
300mA,Ultra-low noise, Small Package
Ultra-Fast CMOS LDO Regulator
General Description
Features
The LP3981 is designed for portable RF and
wireless applications with demanding performance
and space requirements. The LP3981 performance
is optimized for battery-powered systems to deliver
ultra low noise and low quiescent current. A noise
bypass pin is available for further reduction of
output noise. Regulator ground current increases
only slightly in dropout, further prolonging the
battery life. The LP3981 also works with low-ESR
ceramic capacitors, reducing the amount of board
space necessary for power applications, critical in
hand-held wireless devices. The LP3981 consumes
less than 0.01µA in shutdown mode and has fast
turn-on time less than 50µs. The other features
include ultra low dropout voltage, high output
accuracy, current limiting protection, and high
ripple rejection ratio. Available in the 5-lead of
SOT23-5 packages.
Ordering Information
LP3981 -
□ □ □ □
F: Pb-Free
Package Type
B5: SOT23-5
Output Voltage Type
12: 1.2V
15: 1.5V
18: 1.8V
25: 2.5V
28: 2.8V
30: 3.0V
33: 3.3V
50: 5.0V
300mA Output Current, 550mA Peak Current
High PSSR:-73dB at 1KHz 
< 0.01uA Standby Current When Shutdown
Available in SOT23-5 Package TTL-Logic-Controlled Shutdown Input Ultra-Fast Response in Line/Load transient Current Limiting and Thermal Shutdown
Protection
Quick start-up (typically 50uS)
Applications
Marking Information
5
Please see website.
+
NC
4
1uF
2
SHDN
GND
+
3
OUT
1.2V, 1.5V, 1.8V, 2.5V, 2.8V 3.0V and 3.3V Fixed
SOT-25(Top View)
Vout
IN
Low Dropout : 220mV @ 300mA Pin Configurations
Typical Application Circuit
1
2V- 6.5V Input Voltage Range
Portable Media Players/MP3 players
Cellular and Smart mobile phone
LCD
DSC Sensor
Wireless Card
□
Vin
Ultra-Low-Noise for RF Application LP3981 – 01 Ver. 1.1 Datasheet
Feb.-2008
Page 1 of 8
Preliminary
Datasheet
LP3981
Functional Pin Description
Pin Name
EN
Pin Function
Chip Enable (Active High). Note that this pin is high impedance. There should be a pull low
100kΩ resistor connected to GND when the control signal is floating.
NC
NC
GND
Ground
VOUT
VIN
Output Voltage
Power Input Voltage
Function Block Diagram
Absolute Maximum Ratings
Supply Input Voltage-------------------------------------------------------------------------------------------------------------6V
Power Dissipation, PD @ TA = 25°C
SOT-25 --------------------------------------------------------------------------------------------------------400mW
Package Thermal Resistance
SOT-25, θJA ---------------------------------------------------------------------------------------------------------------250°C/W
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------------260°C
Storage Temperature Range -------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------------2kV
MM(Machine-Mode)-----------------------------------------------------------------------------------------------------------200V
Recommended Operating Conditions
Supply Input Voltage------------------------------------------------------------------------------------------------2.5V to 5.5V
EN Input Voltage ------------------------------------------------------------------------------------------------------0V to 5.5V
Operation Junction Temperature Range -----------------------------------------------------------------−40°C to 125°C
Operation Ambient TemperatureRange--------------------------------------------------------------------−40°C to 85°C
LP3981 – 01 Ver. 1.1 Datasheet
Feb.-2008
Page 2 of 8
Preliminary
Electrical Characteristics
Datasheet
LP3981
(VIN = VOUT + 1V, CIN = COUT = 1µF, CBP = 22nF, TA = 25° C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Output Voltage Accuracy
ΔVOUT
IOUT = 1mA
−2
--
+2
%
Output Current
Iout
VEN=VIN,VIN>2.5V
Current Limit
ILIM
RLOAD = 1Ω
Quiescent Current
IQ
VEN ≥ 1.2V, IOUT = 0mA
360
IOUT = 200mA, VOUT >
Dropout Voltage
VDROP
2.8V
ΔVLINE
Load Regulation
ΔLOAD
1mA < IOUT < 300mA
Standby Current
ISTBY
VEN = GND, Shutdown
EN Input Bias Current
IIBSD
VEN = GND or VIN
EN Threshold
Voltage
Logic-High
VIH
Power Supply
Rejection Rate
Start-Up
PSRR
f = 10kHz
LP3981 – 01 Ver. 1.1 Datasheet
COUT = 1µF,
TSD
Feb.-2008
170
200
μA
220
300
0.3
%
0.6
%
0.01
1
μA
0.01
100
nA
0.4
V
1.2
100
uVRMS
−73
IOUT = 10mA
Thermal Shutdown Temperature
120
Shutdown
200mA COUT = 1µF
f = 100Hz
75
VIN = 3V to 5.5V,
10Hz to 100kHz, IOUT =
Output Noise Voltage
mA
5.5V, IOUT = 1mA
VIN = 3V to 5.5V,
Voltage
400
VIN = (VOUT + 1V) to
Line Regulation
VIL
mA
mV
IOUT = 300mA, VOUT >
2.8V
Logic-Low
300
−70
165
dB
°C
Page 3 of 8
Preliminary
Typical Operating Characteristics
LP3981 – 01 Ver. 1.1 Datasheet
Feb.-2008
Datasheet
LP3981
Page 4 of 8
Preliminary
LP3981 – 01 Ver. 1.1 Datasheet
Feb.-2008
Datasheet
LP3981
Page 5 of 8
Preliminary Datasheet
Applications Information
Like any low-dropout regulator, the external capacitors
LP3981
Start-up Function Enable Function
used with the LP3981 must be carefully selected for
regulator stability and performance. Using a capacitor
whose value is > 1µF on the LP3981 input and the
amount of capacitance can be increased without limit.
The input capacitor must be located a distance of not
more than 0.5 inch from the input pin of the IC and
returned to a clean analog ground. Any good quality
ceramic or tantalum can be used for this capacitor. The
capacitor with larger value and lower ESR (equivalent
series
resistance)
provides
better
PSRR
and
line-transient response. The output capacitor must meet
both requirements for minimum amount of capacitance
and ESR in all LDOs application. The LP3981 is designed
specifically to work with low ESR ceramic output
capacitor in space-saving and performance consideration.
Using a ceramic capacitor whose value is at least 1µF
with ESR is > 25mΩ on the LP3981 output ensures
stability. The LP3981 still works well with output capacitor
of other types due to the wide stable ESR range. Figure 1
shows the curves of allowable ESR range as a function of
load current for various output capacitor values. Output
capacitor of larger capacitance can reduce noise and
improve load transient response, stability, and PSRR.
The LP3981 features an LDO regulator enable/disable
function. To assure the LDO regulator will switch on, the
EN turn on control level must be greater than 1.2 volts.
The LDO regulator will go into the shutdown mode when
the voltage on the EN pin falls below 0.4 volts. For to
protecting
the
system,
the
LP3981
have
a
quick-discharge function. If the enable function is not
needed in a specific application, it may be tied to VIN to
keep the LDO regulator in a continuously on state.
Bypass Capacitor and Low Noise
Connecting a 22nF between the BP pin and GND pin
significantly reduces noise on the regulator output, it is
critical that the capacitor connection between the BP pin
and GND pin be direct and PCB traces should be as short
as possible. There is a relationship between the bypass
The output capacitor should be located not more than 0.5
capacitor value and the LDO regulator turn on time. DC
inch from the VOUT pin of the LP3981 and returned to a
leakage on this pin can affect the LDO regulator output
clean analog ground.
noise and voltage regulation performance.
Thermal Considerations
Thermal protection limits power dissipation in LP3981.
When the operation junction temperature exceeds 165°C,
the OTP circuit starts the thermal shutdown function turn
the pass element off. The pass element turn on again
after the junction temperature cools by 30°C. For continue
operation, do not exceed absolute maximum operation
junction temperature 125°C.
LP3981 – 01 Ver. 1.1 Datasheet
Feb.-2008
Page 6 of 8
Preliminary Datasheet
LP3981
The power dissipation definition in device is :
PD = (VIN−VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = ( TJ(MAX) − TA ) /θJA
Where TJ(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and
the θJA is the junction to ambient thermal resistance. For
recommended
operating
conditions specification
of
LP3981, where TJ(MAX) is the maximum junction
temperature of the die (125°C) and TA is the maximum
ambient temperature. The junction to ambient thermal
resistance (θJA is layout dependent) for Sot23-5 package
is 250°C/W.
PD(MAX) = (125°C−25°C) / 250 = 400mW (Sot23-5)
PD(MAX) = (125°C−25°C) / 165 = 606mW
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA.
LP3981 – 01 Ver. 1.1 Datasheet
Feb.-2008
Page 7 of 8
Preliminary
Datasheet
LP3981
Packaging Information
LP3981 – 01 Ver. 1.1 Datasheet
Feb.-2008
Page 8 of 8