PROTEC PLC497_07

05100
PLC497
ULTRA LOW CAPACITANCE TVS ARRAY
APPLICATIONS
✔ Low Voltage Wireless Equipment
✔ Sensor & Control Circuits
✔ Ethernet - 10/100 Base T
✔ FireWire
IEC COMPATIBILITY (EN61000-4)
✔ 61000-4-2 (ESD): Air - 15kV, Contact - 8kV
✔ 61000-4-4 (EFT): 40A - 5/50ns
✔ 61000-4-5 (Surge): 24A, 8/20µs - Level 2(Line-Ground) & Level 3(Line-Line)
SOT-23
F E AT U R E S
✔
✔
✔
✔
✔
✔
250 Watts Peak Pulse Power per Line (tp = 8/20µs)
Unidirectional Configuration
ESD Protection > 25 kilovolts
Low Clamping Voltage < 5 Volts
Ultra Low Capacitance: 2.5pF
RoHS Compliant
MECHANICAL
CHARACTERISTICS
✔ Molded JEDEC SOT-23 Package
✔ Weight 8 milligrams (Approximate)
✔ Available in Lead-Free Pure-Tin Plating(Annealed)
✔ Solder Reflow Temperature:
Pure-Tin - Sn, 100: 260-270°C
✔ Consult Factory for Leaded Device Availability
✔ Flammability Rating UL 94V-0
✔ 8mm Tape and Reel Per EIA Standard 481
✔ Marking: Marking Code
PIN CONFIGURATION
1
3
2
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PLC497
DEVICE CHARACTERISTICS
MAXIMUM RATINGS @ 25°C Unless Otherwise Specified
PARAMETER
Peak Pulse Power (tp = 8/20µs) - See Figure 1
Operating Temperature
Storage Temperature
SYMBOL
VALUE
UNITS
PPP
250
Watts
TL
-55 to 150
°C
TSTG
-55 to 150
°C
ELECTRICAL CHARACTERISTICS PER LINE
PART
NUMBER
PLC497
DEVICE
MARKING
LC
RATED
STAND-OFF
VOLTAGE
V WM
VOLTS
@ 1mA
V(BR)
VOLTS
MAXIMUM
REVERSE
LEAKAGE
CURRENT
(See Note 1)
@VWM
ID
µA
1.0
1.3
20
MINIMUM
BREAKDOWN
VOLTAGE
(See Note 1)
@ 25°C Unless Otherwise Specified
INVERSE
BLOCKING
LEAKAGE
CURRENT
(See Note 2)
@8/20µs
VC@IPP
MAXIMUM
WORKING
INVERSE
BLOCKING
VOLTAGE
(See Note 2)
V WIB
VOLTS
@VWIB IR
µA
@0V, 1MHz
C
pF
5.0V @ 50A
75
1.0
2.5
MAXIMUM
CLAMPING
VOLTAGE
(See Note 1)
(See Fig. 2)
MAXIMUM
CAPACITANCE
(See Note 3)
Note 1: Apply positive voltage from pin2 to 1.
Note 2: Apply positive voltage from pin 1 to 2.
Note 3: Capcitance from pin 1 to 2 < 2.5pF.
FIGURE 1
PEAK PULSE POWER VS PULSE TIME
IPP - Peak Pulse Current - % of IPP
PPP - Peak Pulse Current - Watts
10,000
1,000
250W, 8/20µs Waveform
100
10
0.01
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FIGURE 2
PULSE WAVE FORM
120
tf
100
TEST
WAVEFORM
PARAMETERS
tf = 8µs
td = 20µs
Peak Value IPP
80
e-t
60
40
td = t I /2
PP
20
0
1
10
100
td - Pulse Duration - µs
1,000
10,000
2
0
5
10
15
t - Time - µs
20
25
30
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PLC497
GRAPHS
FIGURE 3
POWER DERATING CURVE
100
Peak Pulse Power
8/20µs
% Of Rated Power
80
60
40
20
Average Power
0
0
25
50
75
100
125
TL - Lead Temperature - °C
150
FIGURE 4
OVERSHOOT & CLAMPING VOLTAGE FOR PLC497
5 Volts per Division
35
25
15
5
-5
ESD Test Pulse: 25 kilovolt, 1/30ns (waveshape)
FIGURE 5
TYPICAL CLAMPING VOLTAGE VS PEAK PULSE CURRENT FOR PLC497
VC - Clamping Voltage - Volts
16
12
8
4
0
0
2
4
6
8
10
12
14
16
18
IPP - Peak Pulse Current - Amps
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PLC497
APPLICATION NOTE
The PLC497 is an ultra low capacitance, bidirectional array that is designed to protect I/O or high speed data lines from the damaging effects of ESD
or EFT. This product has a surge capability of 250 Watts PPP per line for an 8/20µs wave form and offers ESD protection > 40kV.
DIFFERENTIAL-MODE CONFIGURATION (Figure 1)
The PLC497 is designed to protect one unidirectional line. Figure 1 shows a typical differential-mode (line to line) I/O port protection circuit application.
To achieve bidirectional protection, two PLC497 units are placed in parallel with opposing polarities within the circuit layout.
Circuit connectivity is as follows:
✔ Pins 1 and 2 of each device connected to datalines
✔ Pin 3 is not connected
COMMON-MODE CONFIGURATION (Figure 2)
The PLC497 can provide protection for sensor circuit applications. Figure 2 is a typical common-mode (line to ground) sensor circuit application. To
achieve bidirectional protection in this application, a second pair of TVS devices is added in parallel with opposing polarities where pins 2 are
connected to the line, pins 1 connected to ground and pins 3 unconnected.
Circuit connectivity is as follows:
✔ Pins 1 each device connected to datalines
✔ Pins 2 each device connected to ground
✔ Pin 3 is not connected
Figure 1. Typical Differential-Mode i/o Port Protection Circuit
LINE 1 IN
LINE 1 OUT
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
1
2
Circuit board layout is critical for Electromagnetic
Compatibility (EMC) protection. The following guidelines
are recommended:
✔
The protection device should be placed near the
input terminals or connectors, the device will divert
the transient current immediately before it can be
coupled into the nearby traces.
✔
The path length between the TVS device and the
protected line should be minimized.
✔
All conductive loops including power and ground
loops should be minimized.
✔
The transient current return path to ground should
be kept as short as possible to reduce parasitic
inductance.
✔
Ground planes should be used whenever possible.
For multilayer PCBs, use ground vias.
3
3
2
1
LINE 2 IN
LINE 2 OUT
Figure 2. Typical Common-Mode Sensor Protection Circuit
1
2
3
SENSOR
1
2
3
4
CIRCUITRY
1
2
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2
3
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PLC497
SOT-23 PACKAGE OUTLINE & DIMENSIONS
PACKAGE OUTLINE
SOT-23
A
L
0º - 10º
3
B
1
S
PACKAGE DIMENSIONS
2
K
J
MILLIMETERS
MIN
MAX
DIM
V
A
B
C
D
G
H
J
K
L
S
V
G
C
D
H
2.80
1.20
0.89
0.37
1.78
0.013
0.085
0.45
0.89
2.10
0.45
3.04
1.40
1.11
0.50
2.04
0.100
0.177
0.60
1.02
2.50
0.60
INCHES
MIN
MAX
0.1102
0.0472
0.0350
0.0150
0.0701
0.0005
0.0034
0.0180
0.0350
0.0830
0.0177
0.1197
0.0551
0.0440
0.0200
0.0807
0.0040
0.0070
0.0236
0.0401
0.0984
0.0236
NOTES
MOUNTING PAD
1.
2.
3.
4.
0.037” (0.95mm)
Dimensioning and tolerances per ANSI Y14.5M, 1985.
Controlling Dimension: Inches
Pin 3 is the cathode (Unidirectional Only).
Dimensions are exclusive of mold flash and metal burrs.
TAPE & REEL ORDERING NOMENCLATURE
1. Surface mount product is taped and reeled in accordance
with EIA-481.
2. Suffix-T7 = 7 Inch Reel - 3,000 pieces per 8mm tape,
i.e., PLC497-T7.
3. Suffix-T13 = 13 Inch Reel - 10,000 pieces per 8mm tape,
i.e., PLC497-T13.
4. Suffix - LF = Lead-Free, Pure-Tin Plating,
i.e., PLC497-LF-T7.
0.079” (2.00mm)
0.033” (0.85mm)
0.033” (0.85mm)
Outline & Dimensions: Rev 1 - 11/01, 06012
COPYRIGHT © ProTek Devices 2007
SPECIFICATIONS: ProTek reserves the right to change the electrical and or mechanical characteristics described herein without notice (except JEDEC).
DESIGN CHANGES: ProTek reserves the right to discontinue product lines without notice, and that the final judgement concerning selection and specifications is
the buyer’s and that in furnishing engineering and technical assistance, ProTek assumes no responsibility with respect to the selection or specifications of such
products.
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ProTek Devices
2929 South Fair Lane, Tempe, AZ 85282
Tel: 602-431-8101 Fax: 602-431-2288
E-Mail: [email protected]
Web Site: www.protekdevices.com
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