PT6520 LCD Driver IC DESCRIPTION PT6520 is a dot matrix LCD driver IC. The bit addressable display data which is sent from a microcomputer is stored in a build-in display data RAM and generates the LCD signal. The PT6520 incorporates innovative circuit design strategies to assure very low current dissipation and a wide range of operating voltages. The PT6520 permits the user to implement high-performance handy systems operating from a miniature battery. APPLICATIONS FEATURES • • • • • • • • • • • CMOS technology 8-bit data interface 61 segment output 16 common output Duty cycle – PT6520 – 1/16 ~ 1/32 2560 bits built-in display data RAM Master/Slave operation Low power: 30μW LCD voltage: 3.5 ~ 13V Power supply: 2.4 ~ 7V Available in 100 pins, QFP & C.O.B. • Peripheral devices • LCD modules • Electronic instruments BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6520 SYSTEM BLOCK DIAGRAM V1.9 2 July 2010 PT6520 ORDER INFORMATION Valid Part Number Package Type Top Code PT6520 100 Pin, QFP PT6520/PT6520-Q PT6520-H C.O.B. - PIN CONFIGURATION V1.9 3 July 2010 PT6520 PIN DESCRIPTION Pin Name DB0 ~ DB7 Function OSC2 FR SEG0 ~ SEG60 COM0 ~ COM15 COM31 ~COM16 M/S VDD VSS Data input Selection display data or instructions. High: Display data. Low: Instruction. Reset the system and selects the interface type for a 68 port/80 port MPU. High: 68 port MPU interface. Low: 80 port MPU interface. (edge trigger) Oscillation input pin Read/Write Enable signal when a 68 port MPU is connected. (Active-Low read enable signal when an 80 port MPU is connected) Read/Write select signal when a 68 port MPU is connected. High: read select. Low: write select. (Active-Low writes enable input when an 80 port MPU is connected. Rising edge sensing) Oscillation output pin LCD Frame (AC-conversion) signal input/output Segment output for driving the LCD Common output for driving the LCD Common output for driving the LCD Master/Slave select signal 5V power supply 0V power supply (GND level) V1, V2, V3, V4, V5 Power supplies for driving the LCD, VDD>V1>V2>V3>V4>V5 A0 RES OSC1 E/RD RW/WR Note: This is an example of PT6520 family pin assignment. The modified pin names are given below. Product Name PT6520 V1.9 Pin/Pad Number 74 OSC1 75 OSC2 96 ~ 100, 1~ 11 COM0 ~ COM15 4 93 M/S 94 V4 95 V1 July 2010 PT6520 INPUT/OUPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below: INPUT PIN: A0, E, R/W, DB0~DB7, M/S INPUT/OUTPUT PIN: FR OUTPUT PIN: COM0 TO COM15 OUTPUT PIN: SG0~SG60 V1.9 5 July 2010 PT6520 FUNCTION DESCRIPTION DISPLAY COMMANDS (Based on the 80 port MPU; the RD and WR commands differ for the 68 port MPU) RD WR A0 D7 D6 D5 D4 D3 D2 D1 0 1 1 1 Display ON/OFF 1 0 0 1 0 1 2 Display START Line 1 0 0 1 1 0 3 Page Address Set 1 0 0 1 0 1 4 Column (segment) Address Set 1 0 0 0 Write Display Data 1 0 1 Write Data 7 Read Display Data 0 1 1 Read Data 9 Static Drive ON/OFF 1 0 0 0 0 1 1 0 0 ON/OFF 6 1 0 ACC Status Read ADC Select 1 D0 Function Switches the entire display ON or OFF, 0/1 regardless of the Display RAM’s data or the internal status. * Determines the line of RAM data to be Display START Address displayed at the display’s top line (0-31) (COM0) 1 1 0 Page (0-3) 0 Sets the page of the Display RAM in the page address register. Sets the column address of the Display RAM in the column address register. Column address(0-79) 5 8 0 BUSY 1 RESET Command 0 0 0 Read the status. Busy 1: Busy (internal processing) 0: Ready status ADC 1: Rightward (forward) output 0: Leftward (reverse) output ON/OFF 1: Display OFF 0: Display ON RESET 1: Resetting. 0: Normal Writes the data on the data bus These commands access a to RAM previously-specified Reads data address of the Display from the RAM, after which the Display RAM column address is onto the data incremented by one. bus. 1 1 0 0 0 0 0 1 0 Used to reverse the correspondence between the Display RAM’s column address and segment driver output 0/1 ports 0: Rightward (forward)output 1: Leftward (reverse) output 0 Selects normal display operation or static all-lit drive display operation. 0/1 1: Static drive (power save)* 0: Normal display operation Selects the duty factor for driving LCD cells. 0/1 1: 1/32 duty, 0: 1/16 duty 10 Duty Select 1 0 0 1 0 1 0 1 0 0 11 Read Modify Write 1 0 0 1 1 1 0 0 0 0 0 Increments column address counter by 1 when display is written. (This is not done when data is read) 12 End 1 0 0 1 1 1 0 1 1 1 0 Cancels the Ready Modify Write mode. 0 Resets the display START line to the 1st line in the register. Resets the column address counter to 0 and page address to 0. 13 V1.9 Reset 1 0 0 1 1 1 0 6 0 0 1 July 2010 PT6520 RECOMMENDED SOFTWARE FLOWCHART Notes: 1. Command 1: Display On/Off Commands 2. When IC power is applied for the first time, the contents of the Display RAM are not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting. V1.9 7 July 2010 PT6520 CURSOR BLINKING SEQUENCE Page Address Set Column Address Set Read Modify Write Dummy Read Data Read Data Write NO Modify Ended End V1.9 8 July 2010 PT6520 END TIMING MPU INTERFACE (1)80-FAMILY MPU (2)68-FAMILY MPU V1.9 9 July 2010 PT6520 TYPICAL CONNECTIONS WITH LCD PANEL (FULL DOT LCD PANEL: 1 CHARACTER = 6 X 8 DOTS) (1) DUTY 1/16, 10 CHARACTER X 2 LINES (2) DUTY 1/32, 20 CHARACTERS X 4 LINES LCD DRIVER INTERCONNECTIONS PT6520 – PT6520 V1.9 10 July 2010 er d A n mul o C CDA D0=O 00 H 10 Page 3 Page 2 Page 1 Page 0 3A 3B 51 41 94 84 7 GES 6 GES 5 GES 3 4 GES GES 2 GES 1 GES D0=I 4FH 4E SEG Pin GES 0 60 70 3C 31 ES 06 40 50 20 30 4D 4C 11 GES 85 GES 95 V1.9 1/16 Start Associated Line (ex.) Assignment (In this example, the display start line is set at address 08) 00H 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Line address Display Area 4B 4A Page Address DATA D0 D1 D2 D3 D1 , D2=0 , 0 D4 D5 D6 D7 D0 D1 D2 D3 0,1 D4 D5 D6 D7 D0 D1 D2 D3 1,0 D4 D5 D6 D7 D0 D1 D2 D3 1,1 D4 D5 D6 D7 Common output COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 PT6520 RELATIONSHIP BETWEEN DISPLAY DATA RAM LOCATIONS AND ADDRESSES (DISPLAY START LINE: 08) July 2010 PT6520 TIMING CHART READ/WRITE TIMING FOR THE 80-PORT MPU READ/WRITE TIMING FOR THE 68-PORT MPU RESET TIMING FOR 80-PORT/68-PORT DISPLAY V1.9 12 July 2010 PT6520 ABSOLUTE MAXIMUM RATING (Unless otherwise stated, Ta=25℃, VDD=0V) Parameter Symbol Supply voltage (1) VSS Supply voltage (2) V5 Supply voltage (3) V1, V2, V3, V4 Input voltage VI Output voltage VO Power dissipation PD Rating -8.0 to 0.3 -16.5 to 0.3 V5 to 0.3 VSS –0.3 to 0.3 VSS –0.3 to 0.3 250 Unit V V V V V mW Operating temperature Topr -40 to 85 ℃ Storage temperature Tstg -65 to 150 ℃ Soldering temperature Tsol 260°C for 10 s (at leads) - V1.9 13 July 2010 PT6520 DC CHARACTERISTICS (Unless otherwise stated, VDD=0V, VSS=-5/-3V, Ta=25℃) Parameter Operating voltage (1) (Note 1) Recommended Potential Recommended Operating voltage (2) Potential Symbol VSS V5 Potential V1, V2 Potential V3, V4 High input voltage Low input voltage Condition Max. Unit -5.5 -5.0 -4.5 V -7.0 - -2.4 V -13 - -3.5 V -13 - - V 0.6xV5 - VDD V V1, V2 V V3, V4 V5 - 0.4xV5 VSS=-5V VSS+2.0 - VDD VIHC VSS=-5V 0.2xVSS - VDD VIHT VSS=-3V 0.2xVSS - VDD VIHC VSS=-3V 0.2xVSS - VDD VILT VSS=-5V VSS - VSS+0.8 VILC VSS=-5V VSS - 0.8xVSS VILT VSS=-3V VSS - 0.85xVS S VILC VSS=-3V VSS - 0.8xVSS IOH=-3.0mA VSS+2.4 - - IOH=-2.0mA VSS+2.4 - - - - VOHT Low output voltage Typ. VIHT VOHC1 VSS=-5V High output voltage Min. VOHC2 IOH=-120μA 0.2xVSS IOH=-2mA 0.2xVSS VOHC1 VSS=-3V IOH=-2mA 0.2xVSS VOHC2 IOH=-50μA 0.2xVSS VOHT VOLT IOL=3.0mA - - VSS+0.4 VOLT1 VSS=-5V IOL=2.0mA - - VSS+0.4 VOLT2 IOL=120μA - - VOLT IOL=2mA 0.8xVSS VOLC1 VSS=-3V IOL=2mA 0.8xVSS VOLC2 IOL=50μA 0.8xVSS Applicable Pin VSS V5 (Note 2, 3) (Note 2, 3) V (Note 2, 3) (Note 2, 3) V OSC2 (Note 4, 5) V OSC2 (Note 4, 5) V OSC2 (Note 4, 5) V OSC2 (Note 4, 5) 0.8xVSS Input leak current ILI -1 - 1 μA (Note 6) Output leak current ILO -3 - 3 μA (Note 7) V5=-5.0V VSS=-5V - 5 7.5 V5=-3.5V VSS=-5V KΩ - 10 50 SEG0~60 COM0~15 (Note 9) - 0.05 1 μA VDD fCL=2KHz - 2.0 5.0 Rf=1MΩ - 9.5 15 fCL=2KHz - 1.5 4.5 Rf=1MΩ - 6.0 12 - 300 500 150 300 5.0 8 LCD driver ON resistance Static current consumption Dynamic current dissipation RON IDDQ V1.9 CS=CL=VDD During display V5=-5.0V During VSS=-5V IDD (1) During display V5=-5V VSS =-3V IDD (2) Input terminal capacity Ta=25°C CIN μA During access Tcyc=200KHz, VS5=-5V VSS=-3V, During access Tcyc=200KHz, VSS=-3V - Ta=25°C, f=1MHz 14 VDD(Note 10) μA μA VDD(Note 8) pF All input terminals July 2010 PT6520 Parameter Symbol Oscillation frequency Fosc Hysteresis VH Condition Min. Typ. Max. Rf=1.2MΩ±5% VSS=-5.0V 12 17 25 Rf=1.2MΩ±5% VSS=-3.0V 11 16 27 0.05VSS 0.1VSS - Unit Applicable Pin KHz OSC2(Note 5, 6) V (Note 2, 3, 4, 5) Notes: 1. A wide range of operating voltages is guaranteed, except in case of abrupt voltage fluctuations during MPU access. 2. A0, D0~D7, E, R/W pins 3. CL, FR, M/S and RES pins 4. D0~D7 5. FR 6. A0, E (or RD), R/W (or WR), M/S and RES. 7. When D0 to D7 and FR are high impedance. 8. During continual writer access at a frequency of tcyc. Current consumption during access is effectively proportional to the access frequency. 9. For a voltage differential of 0.1V between input (V1,…, V4) and output (COM, SEG) pins. All voltages within specified operating voltage range. 10. PT6520 only. Does not include transient currents due to stray and panel capacitances. V1.9 15 July 2010 PT6520 AC CHARACTERISTICS READ/WRITE TIMING FOR THE 80-PORT MPU (Ta=25℃, VDD=0V, VSS=-5V) Parameter Signal Address hold time Symbol tAH8 A0, CS Address set-up time tAW8 System cycle time tCYC8 WR, RD Control pulse width tCC Data set-up time tDS8 Data hold time tDH8 RD access time Output disable time V1.9 D0~D7 tACC8 tOH8 16 Condition VSS=-5V VSS=-3V VSS=-5V VSS=-3V VSS=-5V VSS=-3V VSS=-5V VSS=-3V VSS=-5V VSS=-3V VSS=-5V VSS=-3V VSS=-5V VSS=-3V CL=100pF CL=100pF, VSS=-3V Min. 10 20 20 40 1000 2000 250 500 100 200 40 80 10 Typ. - Max 120 250 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 - 120 ns July 2010 PT6520 READ/WRITE TIMING FOR THE 68-PORT MPU (Ta=25℃, VDD=0V, VSS=-5V) Parameter Signal Symbol System cycle time Min. 1000 2000 20 40 10 30 80 160 10 20 10 Typ. - Max 60 Unit ns ns ns ns ns ns ns ns ns ns ns 20 - 120 ns - - 200 ns - - 400 ns 250 400 150 250 - - ns ns ns ns Min. Typ. Max Unit VSS=-5V 1 - 750 μs VSS=-3V 1.5 - 1000 μs VSS=-5V 1 - - μs VSS=-3V 1.5 - - μs VSS=-5V 1 - - μs VSS=-3V 1.5 - - μs tCYC6 A0, CS, R/W Address set-up time tAW6 Address hold time tAH6 Control pulse width tDS6 Data set-up time tDH6 D0~D7 Data hold time tOH6 RD access time tACC6 READ Enable disable time E WRITE Condition VSS=-5V VSS=-3V VSS=-5V VSS=-3V VSS=-5V VSS=-3V VSS=-5V VSS=-3V VSS=-5V VSS=-3V CL=100pF VSS=-5V CL=100pF VSS=-3V CL=100pF VSS=-5V CL=100pF VSS=-3V VSS=-5V VSS=-3V tew VSS=-5V VSS=-3V Note: tCYC6 indicates the cycle during which CS/E are high; it does not indicate are cycle of the E signal. CONTROL TIMING FOR 80-PORT/68-PORT MPU (Ta=25℃, VDD=0V, VSS=-5V) Parameter Signal Symbol Reset time RES tR Reset time (68-Port) RES tR1 Reset time (80-Port) RES tR2 Condition Notes: 1. The input timing of the FR delay time is determined by the PT6520 (Slave) 2. The output timing of the FR delay time is determined by the PT6520 (Master) V1.9 17 July 2010 PT6520 PAD LAYOUT (PT6520D*A) 1 95 100 90 85 80 5 75 Y 10 70 X 15 65 4.07mm 20 60 25 55 30 35 40 45 50 3.44mm AI PAD Chip Specification Chip size Chip thickness Pad size V1.9 Dimension (mm) 3.44 x 4.07 0.400+0.025 0.095 x 0.095 18 July 2010 PT6520 PAD COORDINATES OF PT6520D*A (Coordinate unit: um) Pin no. Name X 1 COM5 76.4 2 COM6 76.4 3 COM7 76.4 4 COM8 76.4 5 COM9 76.4 6 COM10 76.4 7 COM11 76.4 8 COM12 76.4 9 COM13 76.4 10 COM14 76.4 11 COM15 76.4 12 SEG60 76.4 13 SEG59 76.4 14 SEG58 76.4 15 SEG57 76.4 16 SEG56 76.4 17 SEG55 76.4 18 SEG54 76.4 19 SEG53 76.4 20 SEG52 76.4 21 SEG51 76.4 22 SEG50 76.4 23 SEG49 76.4 24 SEG48 76.4 25 SEG47 76.4 26 SEG46 76.4 27 SEG45 76.4 28 SEG44 76.4 29 SEG43 76.4 30 SEG42 76.4 31 SEG41 275.4 32 SEG40 425.4 33 SEG39 575.4 34 SEG38 725.4 V1.9 Y 3535.2 3420.2 3305.2 3190.2 3075.2 2960.2 2845.2 2730.2 2615.2 2500.2 2385.2 2270.2 2155.2 2040.2 1925.2 1810.2 1695.2 1580.2 1465.2 1350.2 1235.2 1120.2 1005.2 890.2 775.2 660.2 545.2 430.2 315.2 200.2 76.4 76.4 76.4 76.4 Pin no. Name X 35 SEG37 875.4 36 SEG36 1025.4 37 SEG35 1175.4 38 SEG34 1325.4 39 SEG33 1475.4 40 SEG32 1625.4 41 SEG31 1775.4 42 SEG30 1925.4 43 SEG29 2075.4 44 SEG28 2225.4 45 SEG27 2375.4 46 SEG26 2525.4 47 SEG25 2675.4 48 SEG24 2825.4 49 SEG23 2975.4 50 SEG22 3125.4 51 SEG21 3365.4 52 SEG20 3365.4 53 SEG19 3365.4 54 SEG18 3365.4 55 SEG17 3365.4 56 SEG16 3365.4 57 SEG15 3365.4 58 SEG14 3365.4 59 SEG13 3365.4 60 SEG12 3365.4 61 SEG11 3365.4 62 SEG10 3365.4 63 SEG9 3365.4 64 SEG8 3365.4 65 SEG7 3365.4 66 SEG6 3365.4 67 SEG5 3365.4 68 SEG4 3365.4 19 Y 76.4 76.4 76.4 76.4 76.4 76.4 76.4 76.4 76.4 76.4 76.4 76.4 76.4 76.4 76.4 76.4 200.2 315.2 430.2 545.2 660.2 775.2 890.2 1005.2 1120.2 1235.2 1350.2 1465.2 1580.2 1695.2 1810.2 1925.2 2040.2 2155.2 Pin no. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name SEG3 SEG2 SEG1 SEG0 A0 OSC1 OSC2 E(RD#) R/W(WR#) Vss DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vdd RES# FR V5 V3 V2 M/S V4 V1 COM0 COM1 COM2 COM3 COM4 X 3365.4 3365.4 3365.4 3365.4 3365.4 3365.4 3365.4 3365.4 3365.4 3365.4 3365.4 3365.4 3013.8 2833.8 2653.8 2473.8 2293.8 2113.8 1933.8 1753.8 1573.8 1282.7 1167.7 1052.7 937.7 822.7 707.7 592.7 477.7 362.7 247.7 132.7 Y 2270.2 2385.2 2500.2 2615.2 2781.9 2896.9 3011.9 3126.9 3241.9 3356.9 3471.9 3586.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 3996.9 July 2010 PT6520 PACKAGE INFORMATION 100 PINS, QFP Symbol A A1 A2 b c D D1 E E1 e L1 θ Min. 0.25 2.55 0.22 0.11 Nom. 2.70 0.30 23.20 BSC 20.00 BSC 17.20 BSC 14.00 BSC 0.65 BSC 1.60 REF 3.5° 0° Max. 3.40 0.50 2.90 0.33 0.23 7° Notes: 1. Refer to JEDEC MO-112 GC-1 2. All dimensions are in millimeter. V1.9 20 July 2010 PT6520 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.9 21 July 2010