Displays AND-TFT-8PA 480 x 468 Pixels LCD Color Monitor N/A The AND-TFT-8PA is a compact full color TFT LCD module, whose driving board is capable of converting composite video signals to the proper interface of LCD panel and is suitable for security, car TV, portable DVD, GPS, multimedia applications and other AV system applications. This device consists of a TFT-LCD module that has 480 x 468 pixels on a 8 inch diagonal screen which is normally white in the display mode. Features • Compatible with NTSC and PAL system • Pixel in stripe configuration • 8 inch diagonal screen • High brightness • Slim and compact • Imager Reversion: Up/Down and Left/Right • Anti-glare surface treatment • Support multi-display mode (If you use this mode, you must use a specially made timing controller.) • RoHS compliant Mechanical Characteristics Item Specification Unit Screen Size 8 diagonal inch Outline Dimensions 172.4(W) x 132.0 (H) x 6.6 (D)(typ.) mm Active Area 161.28 (W) x 117.94 (H) mm Surface Treatment Anti-glare – Weight 232 ± 15 g stripe – 0.112 (W) x 0.252 (H) mm 480 x 468 dot Normally white – Pixel Configuration Pixel Pitch Display Format Display Mode Absolute Maximum Rating (GND = 0V, Ta = 25°C) Symbol Item Remarks Absolute Maximum Rating Unit Min. Max. VDD2 +9.0 +15 VDD1 -0.3 +7.0 VCC -0.3 +6.0 VGH- VEE -0.3 +40.0 H Level VGH -0.3 +25.0 L Level VEE -16 +0.3 +4 +13 V VR-, VG-, VB- 0 5.5 V Storage Temperature – -30 +80 °C Operation Temperature – -20 +70 °C Supply Voltage for Source Driver Supply Voltage for Gate Driver Analog Signal Input Level VR+, VG+, VB+ Note 1 Note 2 V V Note 1: VR, VG, VB means analog input voltage. Note 2: Optical characteristics are measured under Ta=+25ºC. 1/28/08 Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085 Tel: 408.523.8200 • Fax: 408.733.1287 • [email protected] • www.purdyelectronics.com 1 Displays Power Consumption AND-TFT-8PA (Ta = 25°C) Item Specifications Typ. Max. Symbol Conditions Hi level IGH VGH = +20V 0.3814 0.4768 mA Low level IEE VEE = -8V 0.4112 0.5141 mA Supply Current for Source Driver (Digital) IDD1 VDD1 = +3.3V 2.0245 2.5306 mA Supply Current for Source Driver (Analog) IDD2 VDD2 = +13V 5 6.24 mA Supply Current for Gate Driver (Digital) ICC VCC = +3.3V Supply Current for Gate Driver LCD Panel Power Consumption (Note 1) – Backlight lamp Power Consumption (Note 2) – Note 1: The power consumption for backlight is not included. Note 2: Backlight lamp power consumption is calculated by IL x VL. – – Units 0.1 0.2 mA 78.75 3.6 98.60 – mW W Remarks Note 1 Note 2 Recommended Driving Conditions for TFT-LCD Panel Item Supply Voltage for Source Driver Supply Voltage for Gate Driver Symbol Analog VDD2 +12 +13 +14 Logic VDD1 +3.0 +3.3 +3.6 H Level VGH +18 +20 +22 L Level VEE -9 -8 -7 Logic VCC +3.0 +3.3 +3.6 +4.0 – Digital Input Voltage Digital Output Voltage Unit V V+, AC – 11.6 11.9 12.2 V V-, AC – +4.0 – OP-P V-, LOW 1.6 1.9 2.2 V H Level VIH 0.7 – VDD1 L Level VIL -0.3 – 0.3 H Level VOH 0.7 – VDD1 L Level VOL -0.3 – 0.3 VR-, VG-, VB(Analog Video -) Remarks V V+, HIGH VR+, VG+, VB+ (Analog Video +) Analog Signal Input Level Specifications Min. Typ. Max. OP-P V V DC Component of VCOM Note 1 Note 1: Purdy strongly suggests that the VCOM DC level shall be adjustable, and the adjustable level range is 5.2V ± 0.3V, every module’s VCOM DC level shall be carefully adjusted to show a best image performance. VCOM VCOM DC 4.9 5.2 5.5 V Backlight Driving (JST BHSR-02VS-1, Pin No.: 2) Pin No. Symbol Description Remarks 1 VL1 Input terminal (Hi voltage side) Wire color: pink 2 VL2 Input terminal (Low voltage side) Wire color: white Note 1 Note 1: Low voltage side of backllight inverter connects with Ground of inverter circuits. 1/28/08 Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085 Tel: 408.523.8200 • Fax: 408.733.1287 • [email protected] • www.purdyelectronics.com 2 Displays Optical Specifications (Ta = 25°C) Item Horizontal Viewing Angle Vertical Contrast Ratio (Note 1) Response Time Brightness (Note 2) Uniformity White Chromaticity (Note 2) Lamp Life Time +25 °C AND-TFT-8PA Rise Fall Specifications Typ. Max. 50 – 15 – 35 – Symbol Conditions θ = 21, θ = 22 θ = 12 θ = 11 CR > 10 CR At optimized Viewing Angle 200 350 – Tr Tf θ=0 – – 15 25 30 50 – Center point 300 350 – U x – 70 0.270 75 0.300 – 0.330 0.300 – 0.330 30,000 0.360 – y – θ=0 – Min. 45 10 30 Unit deg ms cd/m2 % – hrs Note 1: CR = Luminance when Testing point is White Luminance when Testing point is Black Contrast Ratio is measured in optimum common electrode voltage Note 2: Topcon BM-7(fast) luminance meter 2° field of view is used in the testing (after 20~30 minutes operation). Lamp Current : 6mA; Inverter model: TDK-347 Block Diagram 1/28/08 Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085 Tel: 408.523.8200 • Fax: 408.733.1287 • [email protected] • www.purdyelectronics.com 3 Displays AND-TFT-8PA Recommended Driving Conditions for Backlight Item Symbol Lamp Voltage VL 540 600 660 Vrms Lamp Current IL Note1 4 6 8 mA Lamp Frequency PL Note 2 30 60 80 KHz VS Note 3 – – 920 Vrms VS Note 3 – – 1100 Vrms Starting Voltage (25 °C) (Reference Value) Starting Voltage (0 °C) (Reference Value) Remark Ta = 25°C Specifications Unit Min. Typ. Max. Note 1: In order to satisfy the quality of B/L, no matter use what kind of inverter, the output lamp current must between Min. and Max. to avoid the abnormal display image caused by B/L. Note 2: The waveform of lamp driving voltage should be as closed to a perfect sine wave as possible.’ Note 3: The “Max of kick of voltage” means the minimum voltage of inverter to turn on the CCFL and it should be applied to the lamp for more than 1 second to start up. Otherwise the lamp may not be turned on. Interface Pin Assignment Connector: Pin #. Symbol I/O Function 1 STH2 I/O Start pulse for source driver 2 OEH I Output enable for source driver 3 POL I Polarity control for column inversion MOD 4 I Simultaneous/sequential mode select Remark Note 2 5 R/L I Left/Right Control for source driver Note 2 6 VDD1 – Supply voltage of logic circuit for source driver Note 7 7 CPH3 I Sample and shift clock for source driver 8 CPH2 I Sample and shift clock for source driver 9 CPH1 VSS1 I Sample and shift clock for source driver 10 – Ground of logic circuit for source driver 11 VDD2 – Supply voltage of analog circuit for source driver 12 13 14 VBVGVRVSS2 I I I Video input B for negative polarity Video input G for negative polarity Video input R for negative polarity – Ground for analog circuit for source driver I I I Video input B for positive polarity Video input G for positive polarity Video input R for positive polarity – Ground for analog circuit for source driver 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 VB+ VG+ VR+ VSS2 I/O I I I I I I I/O I/O – 30 STH1 VCOM OE1 OE2 OE3 U/D CKV STVD STVU VCC VEE 31 32 1/28/08 Note 6 – Start pulse for source driver Voltage for common electrode Output enable for gate driver Output enable for gate driver Output enable for gate driver Up/Down Control for gate drive Shift clock for gate driver Vertical start pulse Vertical start pulse Power supply for gate driver circuit Negative power gate driver Note 2 Note 1 Note 1 Note 3 Note 4 VGH – Positive power gate driver Note 5 GND – Ground for gate driver Note 1 Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085 Tel: 408.523.8200 • Fax: 408.733.1287 • [email protected] • www.purdyelectronics.com 4 Displays AND-TFT-8PA Note 1 U/D STVD STVU Scanning Direction Vcc Input Output Up to Down GND Output Input Down to Up R/L STH1 STH2 Scanning Direction Vcc Input Output Left to Right GND Output Input Right to Left Note 2 Note 3: VCC Typ. = +3.3V Note 4: VEE Typ. = -8V Note 5: VGH Typ. = +20V Note 6: VDD2 Typ. = +13V Note 7: VDD1 Typ. = +3.3V Pixel Arrangement and input connector pin no. 1/28/08 Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085 Tel: 408.523.8200 • Fax: 408.733.1287 • [email protected] • www.purdyelectronics.com 5 Displays AND-TFT-8PA Timing Characteristics of Input Signals Characteristics Symbol Min. Typ. Max. Unit Rising Time tr – – 10 ns Falling Time tf – – 10 ns High and low level pulse width tCPH 9.2 9.6 10.0 MHz CPH1 ~CPH3 CPH pulse duty tCWH 30 50 70 % CPH1 ~ CPH3 STH setup time tSUH 20 – – ns STH1, STH2 STH hold time tHDH 20 – – ns STH1, STH2 STH pulse width tSTH – 1 – tCPH STH1, STH2 STH period tH 61.5 63.5 65.5 µs STH1, STH2 OEH pulse width tOEH – 3.47 – µs OEH Samplle and hold disable time tDIS1 – 7.43 – µs OEV pulse width tOEV – 52.3 – µs OEV CKV pulse width tCKV – 15.8 – µs CKV Horizontal display start tSH – 0 – tCPH /3 Horizontal display timing range tDH – 480 – tCPH STV pusle width tSTV – 1.5 – tH Horizontal lines per field tV 256 262 268 tH Vertical display start tSV – 3 – tH Vertical display timing range tDV – 234 – tH Distance from OEH to STVD (odd field) tDIS2 – 33.9 – µs Distance from OEH to STVD (evenfield) tDIS3 – 2.2 – µs OE (1, 2, 3) pulse width 1 Poev1 – 4.2 – µs OE (1, 2, 3) pulse width 2 Poev2 – 81.6 – µs Distance from CKV to OE1 Tfa1 – 14.9 – µs Distance from OE1 to another OE2 Tra2 – 18.1 – µs DIstance from OE2 to another OE3 Tra3 – 18.1 – µs Distance2 from POL to STVD(u) Tpol – 2 – tH 1/28/08 Remarks STVD, STVU Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085 Tel: 408.523.8200 • Fax: 408.733.1287 • [email protected] • www.purdyelectronics.com 6 Displays AND-TFT-8PA Dimensional Outline General mechanical tolerance = 0.5mm 1/28/08 Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085 Tel: 408.523.8200 • Fax: 408.733.1287 • [email protected] • www.purdyelectronics.com 7