P4C1024 HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM FEATURES High Speed (Equal Access and Cycle Times) — 15/20/25/35 ns (Commercial) — 20/25/35/45 ns (Industrial) — 20/25/35/45/55/70/85/100/120 ns (Military) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages —32-Pin 300 mil DIP and SOJ —32-Pin 400 mil SOJ —32-Pin 600 mil Ceramic DIP —32-Pin 400 mil Ceramic DIP —32-Pin Solder Seal Flatpack —32-Pin LCC (450 x 500 mil) —32-Pin Ceramic SOJ DESCRIPTION The P4C1024 is a 1,048,576-bit high-speed CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 15 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1024 is a member of a family of PACE RAM™ products offering fast access times. FUNCTIONAL BLOCK DIAGRAM The P4C1024 device provides asynchronous operations with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. PIN CONFIGURATION DIP (P300, C10, C11), SOJ (J300, J400, CJ1), SOLDER SEAL FLATPACK (FS-3) SIMILAR LCC (L6) Document # SRAM124 REV A Revised October 2005 P4C1024 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Ambient Temperature Military –55°C to +125°C –40°C to +85°C Industrial Commercial 0°C to +70°C GND VCC 0V 0V 0V 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% Symbol Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Parameter Symbol Conditions Typ. Unit CIN Input Capacitance COUT Output Capacitance VOUT = 0V VIN = 0V 8 pF 10 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter VIH Input High Voltage VIL Input Low Voltage VHC VLC CMOS Input High Voltage VCD VOL VOH P4C1024 Min Max 2.2 VCC +0.5 Test Conditions –0.5(3) 0.8 P4C1024L Unit Min Max 2.2 VCC +0.5 V –0.5(3) 0.8 VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 CMOS Input Low Voltage –0.5(3) Input Clamp Diode Voltage VCC = Min., IIN = –18 mA Output Low Voltage IOL = +8 mA, VCC = Min. (TTL Load) Output High Voltage IOH = –4 mA, VCC = Min. (TTL Load) VCC = Max. Mil. Input Leakage Current VIN = GND to VCC Ind./Com’l. 0.2 –0.5(3) V V 0.2 V –1.2 –1.2 V 0.4 0.4 V 2.4 2.4 V –10 –5 +10 +5 –5 n/a +5 n/a µA –10 –5 +10 +5 –5 n/a +5 n/a µA ___ ___ 25 n/a mA ISB ___ ___ 35 Standby Power Supply Current (TTL Input Levels) CE1 ≥ VIH or Mil. CE2 ≤VIL, Ind./Com’l. VCC= Max, f = Max., Outputs Open ___ ___ ___ ___ 2 n/a mA ISB1 CE1 ≥ VHC or Mil. CE2 ≤VLC, Ind./Com’l. VCC= Max, f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC 25 Standby Power Supply Current (CMOS Input Levels) ILI ILO Output Leakage Current VCC = Max., CE = VIH, VOUT = GND to VCC Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended Document # SRAM124 REV A Mil. Ind./Com’l. 30 20 periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 14 P4C1024 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Commercial ICC Dynamic Operating Current* Industrial Military -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Unit 190 160 150 145 N/A N/A N/A N/A N/A N/A mA N/A 175 165 160 155 N/A N/A N/A N/A N/A mA N/A 150 140 135 130 125 115 110 105 100 mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH DATA RETENTION CHARACTERISTICS (P4C1024L, Military Temperature Only) Symbol Parameter Test Condition VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V Data Retention Time or VIN ≤ 0.2V tR † Min Typ.* VCC= 2.0V 3.0V Max VCC= 2.0V 3.0V 2.0 Operation Recovery Time V 50 CE1 ≥ VCC – 0.2V or Unit 200 400 600 µA ns tRC§ ns *TA = +25°C § tRC = Read Cycle Time † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM124 REV A Page 3 of 14 P4C1024 AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tRC Read Cycle Time tAA Address Access Time 15 20 25 35 45 55 70 85 100 120 ns tAC Chip Enable Access Time 15 20 25 35 45 55 70 85 100 120 ns tOH Output Hold from Address Change 3 3 3 3 3 3 3 3 3 3 ns tLZ Chip Enable to Output in Low Z 3 3 3 3 3 3 3 3 3 3 ns tHZ tOE 15 20 Chip Disable to Output in High Z Output Enable Low to Data Valid tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 25 35 45 55 70 85 100 120 ns 8 9 11 15 20 25 30 35 40 50 ns 7 9 11 15 20 25 30 35 40 50 ns 0 0 7 0 0 9 0 12 0 11 0 20 0 15 0 20 0 20 0 20 0 25 0 25 0 30 0 30 0 35 0 35 0 40 0 40 ns 50 0 45 ns ns 50 ns OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 1 (OE Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. Document # SRAM124 REV A 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. Page 4 of 14 P4C1024 TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) CE1, CE2 CONTROLLED)(5,7,10) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE Notes: 9. READ Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM124 REV A 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. Page 5 of 14 P4C1024 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time 15 20 25 35 45 55 70 85 100 120 ns tCW Chip Enable Time to End of Write 12 15 18 22 30 35 45 50 60 75 ns tAW Address Valid to End of Write 12 15 20 25 35 45 60 70 85 100 ns 0 0 0 0 0 0 0 0 0 0 ns 12 15 18 22 25 30 40 45 55 70 ns tAS tWP Address Set-up Time Write Pulse Width tAH Address Hold Time 0 0 0 0 0 0 0 0 0 0 ns tDW Data Valid to End of Write 7 8 10 15 20 25 30 35 45 60 ns tDH Date Hold Time 0 0 0 0 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 8 3 10 3 11 3 15 3 18 3 20 3 25 3 30 3 40 3 50 3 ns ns WE CONTROLLED)(11) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state. Document # SRAM124 REV A 14. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 6 of 14 P4C1024 CE CONTROLLED)(11) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE TRUTH TABLE AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Mode Input Rise and Fall Times 3ns Standby H X X X High Z Standby Input Timing Reference Level 1.5V Standby X L X X High Z Standby Output Timing Reference Level 1.5V DOUT Disabled L H H H High Z Active Read Write L H H DOUT L H L X L High Z Active Active See Fig. 1 and 2 Output Load Figure 1. Output Load CE1 CE2 OE WE I/O Power Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1024, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long highinductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. Document # SRAM124 REV A To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 7 of 14 P4C1024 ORDERING INFORMATION SELECTION GUIDE The P4C1024 is available in the following temperature, speed and package options. Te m pe ra ture Ra nge Commercial Industrial Military Temperature Military Processed* Pa cka ge Spe e d 15 20 25 35 45 Plastic DIP (300 mil) -15P3C -20P3C -25P3C -35P3C N/A Plastic SOJ (300 mil) -15J3C -20J3C -25J3C -35J3C N/A Plastic SOJ (400 mil) -15J4C -20J4C -25J4C -35J4C N/A Plastic DIP (300 mil) N/A -20P3I -25P3I -35P3I -45P3I Plastic SOJ (300 mil) N/A -20J3I -25J3I -35J3I -45J3I Plastic SOJ (400 mil) N/A -20J4I -25J4I -35J4I -45J4I Ceramic DIP (600 mil) N/A -20C6M -25C6M -35C6M -45C6M Ceramic DIP (400 mil) N/A -20C4M -25C4M -35C4M -45C4M Solder Seal Flatpack N/A -20FSM -25FSM -35FSM -45FSM LCC (450 x 550 mil) N/A -20LM -25LM -35LM -45LM Ceramic SOJ N/A -20CJM -25CJM -35CJM -45CJM Ceramic DIP (600 mil) N/A -20C6MB -25C6MB -35C6MB -45C6MB Ceramic DIP (400 mil) N/A -20C4MB -25C4MB -35C4MB -45C4MB Solder Seal Flatpack N/A -20FSMB -25FSMB -35FSMB -45FSMB LCC (450 x 550 mil) N/A -20LMB -25LMB -35LMB -45LMB Ceramic SOJ N/A -20CJMB -25CJMB -35CJMB -45CJMB * Military temperature range with MIL-STD-883, Class B compliance. N/A = Not Available Document # SRAM124 REV A Page 8 of 14 P4C1024 Temperature Range Commercial Industrial Military Temperature Package 55 70 85 100 120 Plastic DIP (300 mil) N/A N/A N/A N/A N/A Plastic SOJ (300 mil) N/A N/A N/A N/A N/A Plastic SOJ (400 mil) N/A N/A N/A N/A N/A Plastic DIP (300 mil) N/A N/A N/A N/A N/A Plastic SOJ (300 mil) N/A N/A N/A N/A N/A Plastic SOJ (400 mil) N/A N/A N/A N/A N/A Ceramic DIP (600 mil) -55C6M -70C6M -85C6M -100C6M -120C6M Ceramic DIP (400 mil) -55C4M -70C4M -85C4M -100C4M -120C4M Solder Seal Flatpack -55FSM -70FSM -85FSM -100FSM -120FSM LCC (450 x 550 mil) -55LM -70LM -85LM -100LM -120LM Ceramic SOJ Military Processed* Speed -55CJM -70CJM -85CJM -100CJM -120CJM Ceramic DIP (600 mil) -55C6MB -70C6MB -85C6MB -100C6MB -120C6MB Ceramic DIP (400 mil) -55C4MB -70C4MB -85C4MB -100C4MB -120C4MB Solder Seal Flatpack -55FSMB -70FSMB -85FSMB -100FSMB -120FSMB LCC (450 x 550 mil) Ceramic SOJ -55LMB -70LMB -85LMB -100LMB -120LMB -55CJMB -70CJMB -85CJMB -100CJMB -120CJMB * Military temperature range with MIL-STD-883, Class B compliance. N/A = Not Available Document # SRAM124 REV A Page 9 of 14 P4C1024 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J300 SOJ SMALL OUTLINE IC PACKAGE (300 mil) 32 (300 mil) Min Max 0.128 0.148 0.082 0.016 0.020 0.007 0.010 0.820 0.830 0.050 BSC 0.335 BSC 0.295 0.305 0.267 BSC 0.025 - J400 SOJ SMALL OUTLINE IC PACKAGE (400 mil) 32 (400 mil) Min Max 0.128 0.148 0.082 0.015 0.020 0.007 0.013 0.820 0.830 0.050 BSC 0.435 0.445 0.395 0.405 0.370 BSC 0.025 - Document # SRAM124 REV A Page 10 of 14 P4C1024 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α Pkg # # Pins Symbol A b c D E E1 E2 E3 e L Q S S1 M N P300 PLASTIC DUAL IN-LINE PACKAGE 32 (300 mil) Min Max 0.200 0.015 0.014 0.022 0.048 0.054 0.008 0.014 1.580 1.620 0.270 0.300 0.300 0.310 0.100 BSC 0.320 0.390 0.120 0.140 0° 15° FS-3 SOLDER SEAL FLAT PACKAGE 32 Min Max 0.097 0.125 0.015 0.019 0.003 0.009 0.830 0.400 0.420 0.450 0.180 0.030 0.050 BSC 0.250 0.370 0.020 0.045 0.045 0.000 0.0015 32 Document # SRAM124 REV A Page 11 of 14 P4C1024 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C10 SIDEBRAZED DUAL IN-LINE PACKAGE (600 mil) 32 (600 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.680 0.510 0.620 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - C11 SIDEBRAZED DUAL IN-LINE PACKAGE (400 mil) 32 (400 mil) Min Max 0.232 0.014 0.023 0.038 0.065 0.008 0.018 1.700 0.350 0.410 0.400 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - Document # SRAM124 REV A Page 12 of 14 P4C1024 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE Pkg # # Pins Symbol A A1 A2 B B1 B2 B3 D D1 E E1 E2 e e1 e2 j S S1 L6 RECTANGULAR LEADLESS CHIP CARRIER 32 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.442 0.458 0.300 BSC 0.150 BSC 0.458 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 7 9 CJ1 CERAMIC SOJ SMALL OUTLINE IC PACKAGE 32 Min Max 0.120 0.165 0.088 0.120 0.070 REF 0.010 REF 0.030R TYP 0.020 REF 0.025 0.045 0.816 0.838 0.750 REF 0.419 0.431 0.430 0.445 0.360 0.380 0.050 BSC 0.038 TYP 0.005 0.005 TYP 0.030 0.040 0.020 TYP Document # SRAM124 REV A Page 13 of 14 P4C1024 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM124 P4C1024 HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid Document # SRAM124 REV A DESCRIPTION OF CHANGE Page 14 of 14