P4C1258 ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell Three-State Outputs High Speed (Equal Access and Cycle Times) – 15/20/25/35 ns (Commercial/Industrial) TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Low Power Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP, SOJ Single 5V±10% Power Supply Data Retention with 2.0V Supply DESCRIPTION The P4C1258 is a 262,144-bit ultra high speed static RAM organized as 64K x 4. The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION The P4C1258 is available in a 24-pin 300 mil DIP or SOJ packages providing excellent board level densities. DIP (P4) SOJ (J4) Document # SRAM123 REV OR 1 Revised October 2005 P4C1258 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Industrial Commercial Ambient Temperature GND VCC –40°C to +85°C 0°C to +70°C 0V 0V 5.0V ± 10% 5.0V ± 10% Symbol Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Typ. Unit VIN = 0V 5 pF VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter Test Conditions P4C1258 Min Max Unit VIH Input High Voltage 2.2 VCC +0.5 V VIL Input Low Voltage –0.5(3) 0.8 V VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD Input Clamp Diode Voltage VCC = Min., IIN = 18 mA VOL VOH Output Low Voltage (TTL Load) Output High Voltage (TTL Load) VCC –0.2 VCC +0.5 –0.5 IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. ILI Input Leakage Current ILO Output Leakage Current ISB CE ≥ VIH Standby Power Supply Current (TTL Input Levels) VCC = Max ., f = Max., Outputs Open ISB1 Standby Power Supply Current (CMOS Input Levels) VIN = GND to VCC VCC = Max., CE = VIH VOUT = GND to VCC CE ≥ VHC VCC = Max., f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Document # SRAM123 REV OR (3) V 0.2 V –1.2 V 0.4 V 2.4 V –5 +5 µA –5 +5 µA ___ 35 mA ___ 10 mA 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 9 P4C1258 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current* Temperature Range Commercial Industrial Unit –15 –20 –25 –35 160 125 115 110 mA 170 135 120 115 mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL DATA RETENTION CHARACTERISTICS Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Test Conditions Min Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V V 2.0 CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V Unit 10 15 1500 2000 µA 0 ns tRC§ ns *TA = +125°C tRC = Read Cycle Time § † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM123 REV OR Page 3 of 9 P4C1258 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -15 Min -25 -20 Max Min Max Min 20 25 -35 Max Min Max Unit tRC Read Cycle Time tAA Address Access Time 15 20 25 35 ns tAC Chip Enable Access Time 15 20 25 35 tOH Output Hold from Address Change 2 2 2 2 ns ns tLZ Chip Enable to Output in Low Z 2 3 3 3 ns tHZ Chip Disable to Output in High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 15 0 0 15 25 ns ns 0 0 20 ns 11 10 9 8 35 35 ns TIMING WAVEFORM OF READ CYCLE NO. 1(5) TIMING WAVEFORM OF READ CYCLE NO. 2(6) Notes: 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. Document # SRAM123 REV OR 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 of 9 P4C1258 AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -15 -20 -25 -35 Min Max Min Max Min Max Min Max Unit tWC Write Cycle Time 13 20 25 35 ns tCW Chip Enable Time to End of Write 12 15 18 25 ns tAW Address Valid to End of Write 12 15 18 25 ns tAS Address Set-up Time 0 0 0 0 ns tWP Write Pulse Width 12 15 18 25 ns tAH Address Hold Time from End of Write 0 0 0 0 ns tDW Data Valid to End of Write 7 8 10 15 ns tDH Data Hold Time 0 0 0 0 ns tWZ Write Enable to Output in High Z tDW Output Active from End of Write 6 2 8 2 10 2 15 3 ns ns WE CONTROLLED) (9) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. Document # SRAM123 REV OR 12. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. Page 5 of 9 P4C1258 CE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Mode CE WE Output Power Standby Input Rise and Fall Times 3ns Standby H X High Z Input Timing Reference Level 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L DIN Active Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1258, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high Document # SRAM123 REV OR frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 6 of 9 P4C1258 ORDERING INFORMATION SELECTION GUIDE The P4C1258 is available in the following temperature, speed and package options. Temperature Range Commercial Industrial Package Speed 15 20 25 35 Plastic DIP -15PC -20PC -25PC -35PC Plastic SOJ -15JC -20JC -25JC -35JC Plastic DIP -15PI -20PI -25PI -35PI Plastic SOJ -15JI -20JI -25JI -35JI Document # SRAM123 REV OR 1513 10 Page 7 of 9 P4C1258 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α J4 SOJ SMALL OUTLINE IC PACKAGE 24 (300 mil) Min Max 0.128 0.148 0.082 0.016 0.020 0.007 0.010 0.620 0.630 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - P4 PLASTIC DUAL IN-LINE PACKAGE 24 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.230 1.280 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° Document # SRAM123 REV OR Page 8 of 9 P4C1258 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM123 P4C1258 ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE OR Oct-05 JDB Document # SRAM123 REV OR DESCRIPTION OF CHANGE New Data Sheet Page 9 of 9