P4C198/P4C198L, P4C198A/P4C198AL ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS FEATURES Output Enable & Chip Enable Control Functions – Single Chip Enable P4C198 – Dual Chip Enable P4C198A Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military) Common Inputs and Outputs Fully TTL Compatible Inputs and Outputs Low Power Operation (Commercial/Military) Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP – 24-Pin 300 mil SOJ – 28-Pin 350 x 550 mil LCC 5V ± 10% Power Supply Data Retention, 10 µA Typical Current from 2.0V P4C198L/198AL (Military) DESCRIPTION The P4C198/L and P4C198A/L are 65,536-bit ultra highspeed static RAMs organized as 16K x 4. Each device features an active low Output Enable control to eliminate data bus contention. The P4C198/L also have an active low Chip Enable (the P4C198A/L have two Chip Enables, both active low) for easy system expansion. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained with supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS Access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption to a low 715 mW active, 193 mW standby. The P4C198/L and P4C198A/L are available in 24-pin 300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC packages providing excellent board level densities. DIP (P4, C4, D4), SOJ (J4) LCC (L5) P4C198 (P4C198A) P4C198 (P4C198A) Document # SRAM113 REV A 1 Revised October 2005 P4C198/198L, P4C198A/198AL MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C Symbol Ambient Temperature Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA VCC = 5.0V, TA = 25°C, f = 1.0MHz VCC Symbol 0V 0V 0V 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% CIN –55°C to +125°C 0°C to +70°C Commercial –40°C to +85°C Industrial Unit TBIAS GND Military Value CAPACITANCES(4) RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Parameter COUT Parameter Conditions Typ. Unit Input Capacitance VIN = 0V 5 pF Output Capacitance VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter P4C198 / 198A Min Max Test Conditions VIH Input High Voltage 2.2 VIL Input Low Voltage –0.5(3) V HC CMOS Input High Voltage VLC CMOS Input Low Voltage V CD Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) VOL VOH P4C198L / 198AL Unit Min Max VCC +0.5 2.2 VCC +0.5 V 0.8 –0.5(3) 0.8 VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 –0.5 (3) VCC = Min., IIN = –18 mA IOL = +10 mA, VCC = Min. IOL = +8 mA, VCC = Min. 0.5 IOH = –4 mA, VCC = Min. 2.4 VCC = Max. 0.2 –0.5 (3) –1.2 Mil. V 0.2 V –1.2 V 0.4 V V 0.5 0.4 V V 2.4 –10 –5 +10 +5 –5 n/a +5 n/a µA –10 –5 +10 +5 –5 n/a +5 n/a µA ISB CE1, CE2 ≥ VIH Mil. Standby Power Supply VCC = Max ., Ind./Com’l. Current (TTL Input Levels) f = Max., Outputs Open ___ ___ 40 35 ___ ___ 40 n/a mA CE1, CE2 ≥ VIH Mil. VCC = Max., Ind./Com’l. f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC ___ ___ 20 15 ___ ___ 1.5 n/a mA ISB1 Standby Power Supply Current (CMOS Input Levels) ILI Input Leakage Current ILO Output Leakage Current VIN = GND to VCC Ind./Com’l. VCC = Max., CE = VIH, VOUT = GND to VCC Mil. Ind./Com’l. n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM ratingconditions for extended periods may affect reliability. Document # SRAM113 REV A 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 13 P4C198/198L, P4C198A/198AL POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current* Temperature Range Commercial –10 –12 –15 –20 –25 –35 –45 180 170 160 155 150 N/A N/A mA Industrial N/A 180 170 160 155 150 N/A mA Military N/A N/A 170 160 155 150 145 mA Unit *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. 198: CE = VIL, OE = VIH 198A: CE1 = VIL, CE2 = VIL. OE = VIH DATA RETENTION CHARACTERISTICS (P4C198L/P4C198AL Military Temperature Only) Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Test Condition Min Typ.* VCC= 2.0V 3.0V Max VCC= 2.0V 3.0V 2.0 V 10 CE ≥VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V Unit 15 600 900 µA 0 ns tRC§ ns *TA = +25°C § tRC = Read Cycle Time † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM113 REV A Page 3 of 13 P4C198/198L, P4C198A/198AL AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -10 -12 -15 -20 -25 -35 -45 Sym. Parameter tRC Read Cycle Time tAA Address Access Time 10 12 15 20 25 35 45 ns tAC Chip Enable Access Time 10 12 15 20 25 35 45 ns tOH Output Hold from Address Change 2 2 2 2 2 2 2 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 2 2 2 ns tHZ Chip Disable to Output in High Z 6 7 8 10 10 14 15 ns tOE Output Enable Low to Data Valid 6 7 9 12 15 25 30 ns tOLZ Output Enable to Output in Low Z Min Max Min 10 tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 12 2 tOHZ Output Disable to Output in High Z Max Min Max Min Max Min Max Min Max Min Max Unit 15 2 2 6 0 7 0 10 20 2 9 0 12 25 2 9 0 15 35 2 10 0 20 45 2 14 0 25 ns ns 15 0 35 ns ns 45 ns OE controlled)(5) READ CYCLE NO.1 (OE Notes: 5. WE is HIGH for READ cycle. Document # SRAM113 REV A Page 4 of 13 P4C198/198L, P4C198A/198AL READ CYCLE NO. 2 (ADDRESS Controlled)(5,6) CE(12) Controlled)(5,7,8) READ CYCLE NO. 3 (CE Notes: 6. CE (CE1 CE2 for P4C198A/L) and OE are LOW READ cycle. 7. OE is LOW for the cycle. 8. ADDRESS must be valid prior to, or coincident with CE (CE1 and CE2 for P4C198A/L) transition LOW. 9. Transition is measured ± 200mV from steady state voltage prior to change, with loading as specified in Figure 1. Document # SRAM113 REV A 10. Read Cycle Time is measured from the last valid address to the first transitioning address. 11. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them (P4C198A/L). 12. CE1, CE2 for P4C198A/L. Page 5 of 13 P4C198/198L, P4C198A/198AL AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. -10 Parameter -12 Min Max Min -15 -20 -25 -35 -45 Unit Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time 10 12 13 15 20 30 40 ns tCW Chip Enable Time to End of Write 7 8 10 15 20 30 35 ns tAW Address Valid to End of Write 8 8 10 15 20 25 35 ns tAS Address Set-up Time 0 0 0 0 0 0 0 ns tWP Write Pulse Width 8 9 10 12 20 25 35 ns tAH Address Hold Time from End of Write 0 0 0 0 0 0 0 ns tDW Data Valid to End of Write 7 6 7 10 13 15 20 ns tDH Data Hold Time 0 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 7 3 6 3 7 3 8 3 10 3 10 3 15 3 ns ns WRITE CYCLE NO. 1 (With OE high) Document # SRAM113 REV A Page 6 of 13 P4C198/198L, P4C198A/198AL WE CONTROLLED)(13,14) WRITE CYCLE NO. 2 (WE 1520 08 CE(12) CONTROLLED)(13,14) WRITE CYCLE NO. 3 (CE Notes: 13. CE (CE1, CE2 for P4C198A/L) and WE must be LOW for WRITE cycle. 14. OE is LOW for this WRITE cycle. Document # SRAM113 REV A 15. If CE (CE1 or CE2 for P4C198A/L) goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 16. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 7 of 13 P4C198/198L, P4C198A/198AL TRUTH TABLES P4C198/L P4C198A/L CE WE OE Mode H X X Standby L H H L H L L CE1 CE2 WE OE High Z H X X X Standby High Z Output Inhibit High Z X H X X Standby High Z L READ DOUT L L H H Output Inhibit High Z X WRITE DIN L L H L READ DOUT L L L X WRITE DIN Output Mode Output AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C198/L and P4C198A/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high Document # SRAM113 REV A frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 8 of 13 P4C198/198L, P4C198A/198AL ORDERING INFORMATION SELECTION GUIDE The P4C198 and P4C198A are available in the following temperature, speed and package options. Temperature Range Commercial Industrial Military Temperature Military Processed* Package Speed (ns) 10 12 15 20 25 35 45 Plastic DIP -10PC -12PC -15PC -20PC -25PC N/A N/A Plastic SOJ -10JC -12JC -15JC -20JC -25JC N/A N/A Plastic DIP N/A -12PI -15PI -20PI -25PI -35PI N/A Plastic SOJ N/A -12JI -15JI -20JI -25JI -35JI N/A Side Brazed DIP N/A N/A -15CM -20CM -25CM -35CM -45CM CERDIP N/A N/A -15DM -20DM -25DM -35DM -45DM LCC N/A N/A -15LM -20LM -25LM -35LM -45LM Side Brazed DIP N/A N/A -15CMB -20CMB -25CMB -35CMB -45CMB CERDIP N/A N/A -15DMB -20DMB -25DMB -35DMB -45DMB LCC N/A N/A -15LMB -20LMB -25LMB -35LMB -45LMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not available Document # SRAM113 REV A Page 9 of 13 P4C198/198L, P4C198A/198AL Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 α C4 SIDE BRAZED DUAL IN-LINE PACKAGE 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - D4 CERDIP DUAL IN-LINE PACKAGE 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0° 15° Document # SRAM113 REV A Page 10 of 13 P4C198/198L, P4C198A/198AL Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE J4 SOJ SMALL OUTLINE IC PACKAGE 24 (300 mil) Min Max 0.128 0.148 0.082 0.016 0.020 0.007 0.010 0.620 0.630 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - L5 RECTANGULAR LEADLESS CHIP CARRIER 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 Document # SRAM113 REV A Page 11 of 13 P4C198/198L, P4C198A/198AL Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α P4 PLASTIC DUAL IN-LINE PACKAGE 24 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.230 1.280 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° Document # SRAM113 REV A Page 12 of 13 P4C198/198L, P4C198A/198AL REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM113 P4C198 / P4C198L, P4C198A / P4C198AL ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid Document # SRAM113 REV A DESCRIPTION OF CHANGE Page 13 of 13