QIMONDA HYB18T512400AF-3S

January 2007
HYB18T512400AF(L)
HYB18T512800AF(L)
HYB18T512160AF(L)
512-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.71
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
HYB18T512400AF(L), HYB18T512800AF(L), HYB18T512160AF(L)
Revision History: 2007-01, Rev. 1.71
Page
Subjects (major changes since last revision)
All
Qimonda update
All
Adapted internet edition
108
Modified AC Timing Parameters
Previous Revision: 2006-05, Rev. 1.7
57
Changed “Read” to “Write” in condition 4.
57
Removed text “Maximum power up interval for VDD / VDDQ is specified
As 20.0 ms. The power interval is defined as the amount of time it takes for VDD / VDDQ to power-up From 0 V
to 1.8 V ± 100 mV” from condition 1.
Previous Revision: 2005-08, Rev. 1.6
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03062006-CPCN-4867
2
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit DDR2 SDRAM product family and describes its main characteristics.
1.1
Features
The 512-Mbit DDR2 SDRAM offers the following key features:
• 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18)
compatible I/O
• DRAM organisations with 4, 8 and 16 data in/outputs
• Double Data Rate architecture: two data transfers per
clock cycle, four internal banks for concurrent operation
• CAS Latency: 3, 4 and 5
• Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe
operation
• Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
command and data bus efficiency
• Off-Chip-Driver impedance adjustment (OCD) and OnDie-Termination (ODT) for better signal quality.
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving PowerDown modes
• Average Refresh Period 7.8 µs at a TCASE lower than
85 °C, 3.9 µs between 85 °C and 95 °C
• High Temperature Self Refresh Mode is supported
• Full and reduced Strength Data-Output Drivers
• 1KByte page size for × 4 & × 8, 2 KByte page size for × 16
• Lead-free Packages: P-TFBGA-60 for × 4 & × 8
components, P-TFBGA-84 for × 16 components
• RoHS Compliant Products1)
TABLE 1
Performance table for –3(S)
Product Type Speed Code
–3
–3S
Unit
Speed Grade
DDR2–667C 4–4–4
DDR2–667D 5–5–5
—
333
333
MHz
333
266
MHz
200
200
MHz
12
15
ns
12
15
ns
45
45
ns
57
60
ns
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.71, 2007-01
03062006-CPCN-4867
3
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 2
Performance table for –3
Product Type Speed Code
–3
Unit
Speed Grade
DDR2–667C 4–4–4
—
333
MHz
333
MHz
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
200
MHz
12
ns
12
ns
45
ns
57
ns
TABLE 3
Performance table for –3S
Product Type Speed Code
–3S
Unit
Speed Grade
DDR2–667D 5–5–5
—
333
MHz
266
MHz
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
200
MHz
15
ns
15
ns
45
ns
60
ns
TABLE 4
High Performance for DDR2–400B and DDR2–533C
Product Type Speed Code
–3.7
–5
Unit
Speed Grade
DDR2–533C 4–4–4
DDR2–400B 3–3–3
—
266
200
MHz
266
200
MHz
200
200
MHz
15
15
ns
15
15
ns
45
40
ns
60
55
ns
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
Rev. 1.71, 2007-01
03062006-CPCN-4867
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
4
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
1.2
Description
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 16-bit address bus for × 4 and × 8 organised components
and a 15-bit address bus for × 16 components is used to
convey row, column and bank address information .
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The DDR2 SDRAM is available in P-TFBGA package.
The 512-Mbit DDR2 DRAM is a high-speed Double-DataRate-Two CMOS Synchronous DRAM device containing
536,870,912 bits and internally configured as a quad-bank
DRAM. The 512-Mbit device is organized as either 32 Mbit ×
4 I/O × 4 banks, 16 Mbit × 8 I/O × 4 banks or 8 Mbit × 16 I/O
× 4 banks× chip. These synchronous devices achieve high
speed transfer rates starting at 400 Mbit/sec/pin for general
applications. See Table 1, Table 2 and Table 3 for
performance figures.
The device is designed to comply with all DDR2 DRAM key
features.
1. Posted CAS with additive latency,
2. Write latency = read latency - 1,
3. Normal and weak strength data-output driver,
Rev. 1.71, 2007-01
03062006-CPCN-4867
5
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
1.3
Ordering Information
This chapter contains the Ordering Information.
TABLE 5
Ordering Information for RoHS compliant products
Part Number
Org. Speed
CAS RCD RP3)
Latencies
Clock
(MHz)
CAS1) RCD2) RP3)
Latencies
Clock
(MHz)
Package
HYB18T512400AF–5
×4
3–3–3
200
—
—
P-TFBGA-60
HYB18T512800AF–5
×8
HYB18T512160AF–5
×16
HYB18T512400AF–3.7
×4
HYB18T512800AF–3.7
×8
HYB18T512160AF–3.7
×16
P-TFBGA-84
HYB18T512400AFL–3.7
×4
P-TFBGA-60
HYB18T512800ALF–3.7
×8
HYB18T512160AFL–3.7
×16
HYB18T512400AF–3
×4
HYB18T512800AF–3
×8
HYB18T512160AF–3
×16
HYB18T512400AF–3S
×4
HYB18T512800AF–3S
×8
HYB18T512160AF–3S
×16
DDR2–400
1)
2)
P-TFBGA-84
DDR2–533
4–4–4
266
200
P-TFBGA-60
P-TFBGA-84
DDR2–667
4–4–4
333
3–3–3
200
5–5–5
333
4–4–4
266
P-TFBGA-60
P-TFBGA-84
P-TFBGA-60
P-TFBGA-84
1) CAS: Column Adress Strobe
2) RCD: Row Column Delay
3) RP: Row Precharge
Note: For product nomenclature see Chapter 9 of this data sheet
Rev. 1.71, 2007-01
03062006-CPCN-4867
3–3–3
6
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
2
Pin Configuration
This chapter contains the pin configuration.
2.1
Pin Configuration for TFBGA–60 TFBGA–84
The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and Buffer Type
columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package is depicted in Figure 1
for × 4, Figure 2 for × 8 and Figure 3 for × 16.
TABLE 6
Pin Configuration of DDR2 SDRAM
Pin#
Name
Pin
Type
Buffer
Type
Function
SSTL
Clock Signal CK, Complementary Clock Signal CK
Clock Signals ×4/×8 organization
E8
CK
I
F8
CK
I
SSTL
F2
CKE
I
SSTL
Clock Enable
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
Clock Signals ×16 organization
J8
CK
I
SSTL
K8
CK
I
SSTL
K2
CKE
I
SSTL
Clock Enable
Note: See functional description in x4/x8 organization
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Control Signals ×4/×8 organizations
F7
RAS
I
SSTL
G7
CAS
I
SSTL
F3
WE
I
SSTL
G8
CS
I
SSTL
Chip Select
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Control Signals ×16 organization
K7
RAS
I
SSTL
L7
CAS
I
SSTL
K3
WE
I
SSTL
L8
CS
I
SSTL
Chip Select
Address Signals ×4/×8 organizations
G2
BA0
I
SSTL
G3
BA1
I
SSTL
Rev. 1.71, 2007-01
03062006-CPCN-4867
Bank Address Bus 1:0
7
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin#
Name
Pin
Type
Buffer
Type
Function
H8
A0
I
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
H3
A1
I
SSTL
H7
A2
I
SSTL
J2
A3
I
SSTL
J8
A4
I
SSTL
J3
A5
I
SSTL
J7
A6
I
SSTL
K2
A7
I
SSTL
K8
A8
I
SSTL
K3
A9
I
SSTL
H2
A10
I
SSTL
AP
I
SSTL
K7
A11
I
SSTL
L2
A12
I
SSTL
L8
A13
I
SSTL
Address Signal 13
Note: x4/x8 512 Mbit components
NC
—
—
Note: and x 16 512 Mbit components
Bank Address Bus 1:0
Address Signals ×16 organization
L2
BA0
I
SSTL
L3
BA1
I
SSTL
L1
NC
—
—
M8
A0
I
SSTL
M3
A1
I
SSTL
M7
A2
I
SSTL
N2
A3
I
SSTL
N8
A4
I
SSTL
N3
A5
I
SSTL
N7
A6
I
SSTL
P2
A7
I
SSTL
P8
A8
I
SSTL
P3
A9
I
SSTL
M2
A10
I
SSTL
AP
I
SSTL
P7
A11
I
SSTL
R2
A12
I
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
Data Signals ×4/×8 organization
C8
DQ0
I/O
SSTL
C2
DQ1
I/O
SSTL
D7
DQ2
I/O
SSTL
D3
DQ3
I/O
SSTL
Rev. 1.71, 2007-01
03062006-CPCN-4867
Data Signal 3:0
8
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin#
Name
Pin
Type
Buffer
Type
Function
D1
DQ4
I/O
SSTL
Data Signal 7:4
D9
DQ5
I/O
SSTL
B1
DQ6
I/O
SSTL
B9
DQ7
I/O
SSTL
Data Signals ×16 organization
G8
DQ0
I/O
SSTL
G2
DQ1
I/O
SSTL
H7
DQ2
I/O
SSTL
H3
DQ3
I/O
SSTL
H1
DQ4
I/O
SSTL
H9
DQ5
I/O
SSTL
F1
DQ6
I/O
SSTL
F9
DQ7
I/O
SSTL
C8
DQ8
I/O
SSTL
C2
DQ9
I/O
SSTL
D7
DQ10
I/O
SSTL
D3
DQ11
I/O
SSTL
D1
DQ12
I/O
SSTL
D9
DQ13
I/O
SSTL
B1
DQ14
I/O
SSTL
B9
DQ15
I/O
SSTL
Data Signal 15:0
Data Strobe ×4/×8 organizations
B7
DQS
I/O
SSTL
A8
DQS
I/O
SSTL
Data Strobe
Data Strobe ×8 organisation
B3
RDQS
O
SSTL
A2
RDQS
O
SSTL
Read Data Strobe
Data Strobe ×16 organization
B7
UDQS
I/O
SSTL
A8
UDQS
I/O
SSTL
F7
LDQS
I/O
SSTL
E8
LDQS
I/O
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
Data Mask ×4/×8 organizations
B3
DM
I
SSTL
Data Mask
Data Mask Upper/Lower Byte
Data Mask ×16 organization
B3
UDM
I
SSTL
F3
LDM
I
SSTL
Power Supplies ×4×8×16 organization
A9,C1,C3,C7,C VDDQ
9
Rev. 1.71, 2007-01
03062006-CPCN-4867
PWR
—
I/O Driver Power Supply
9
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin#
Name
VDD
A7,B2,B8,D2,D VSSQ
A1
Pin
Type
Buffer
Type
Function
PWR
—
Power Supply
PWR
—
I/O Driver Power Supply
PWR
—
Power Supply
AI
—
I/O Reference Voltage
PWR
—
Power Supply
PWR
—
Power Supply
PWR
—
Power Supply
PWR
—
Power Supply
8
A3,E3
VSS
Power Supplies ×4/×8 organizations
E2
E1
E9,H9,L1
E7
J1,K9
VREF
VDDL
VDD
VSSDL
VSS
Power Supplies ×16 organization
VREF
E9, G1, G3, G7, VDDQ
AI
—
I/O Reference Voltage
PWR
—
I/O Driver Power Supply
VDDL
E1, J9, M9, R1 VDD
E7, F2, F8, H2, VSSQ
PWR
—
Power Supply
PWR
—
Power Supply
PWR
—
I/O Driver Power Supply
PWR
—
Power Supply
PWR
—
Power Supply
—
Not Connected
—
Not Connected
—
Not Connected
SSTL
On-Die Termination Control
SSTL
On-Die Termination Control
J2
G9
J1
H8
J7
A3,
E3,J3,N1,P9
VSSDL
VSS
Not Connected ×4/×8 organization
G1, L3,L7, L8
NC
NC
Not Connected ×4 organization
A2, B1, B9, D1, NC
D9
NC
Not Connected ×16 organization
A2, E2, L1, R3, NC
R7, R8
NC
Other Pins ×4/×8 organizations
F9
ODT
I
Other Pins ×16 organization
K9
ODT
Rev. 1.71, 2007-01
03062006-CPCN-4867
I
10
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
TABLE 8
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.71, 2007-01
03062006-CPCN-4867
11
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
2.1.1
TFBGA Ball Out Diagrams
This chapter contains the TFBGA Ball Out Diagrams.
FIGURE 1
Pin Configuration for × 4 components, PG-TFBGA-60 (top view)
$
6664
'46
6''4
'0
%
'46
6664
1&
'4
6''4
&
6''4
'4
6''4
1&
6664 '4
'
'4
6664
1&
6''/
65()
666
(
966'/
&.
6''
&.(
:(
)
5$6
&.
2'7
%$
%$
*
&$6
&6
$$
3
$
+
$
$
$
$
-
$
$
$
$
.
$
$
$
1&
/
1&
1&$
6''
1&
666
1&
6664 6''4
1&
666
6''
6''
666
0337
Notes
2. Ball position L8 is A13 for 512-Mbit and is Not Connected
on 256-Mbit
1. VDDL and VSSDL are power and ground for the DLL. VDDL is
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS,
and VSSQ are isolated on the device.
Rev. 1.71, 2007-01
03062006-CPCN-4867
12
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
FIGURE 2
Pin Configuration for × 8 components, PG-TFBGA-60-24
6''
1&
5'46
666
'4
6664 6''4
$
6664
'46
6''4
'0
5'46
%
'46
6664
'4
'4
6''4
&
6''4
'4
6''4
'4
6664 '4
'
'4
6664
'4
6''/
65()
666
(
966'/
&.
6''
&.(
:(
)
5$6
&.
2'7
%$
%$
*
&$6
&6
$$
3
$
+
$
$
$
$
-
$
$
$
$
.
$
$
$
1&
/
1&
1&$
1&
666
6''
6''
666
0337
4. VDDL and VSSDL are power and ground for the DLL. VDDL is
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS,
and VSSQ are isolated on the device.
5. Ball position L8 is A13 for 512-Mbit and is Not Connected
on 256-Mbit.
Notes
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is disabled
3. When enabled, RDQS & RDQS are used as strobe
signals during reads.
Rev. 1.71, 2007-01
03062006-CPCN-4867
13
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
FIGURE 3
Pin Configuration for × 16 components, PG-TFBGA-84-8
$
6664
8'46
6''4
8'0
%
8'46
6664
'4
'4
6''4
&
6''4
'4
6''4
'4
6664
'4
'
'4
6664
'4
6''
1&
666
(
6664
/'46
6''4
'4
6664
/'0
)
/'46
6664
'4
6''4
'4
6''4
*
6''4
'4
6''4
'4
6664
'4
+
'4
6664
'4
6''/
65()
666
-
966
'/
&.
6''
&.(
:(
.
5$6
&.
2'7
%$
%$
/
&$6
&6
$
$3
$
0
$
$
$
$
1
$
$
$
$
3
$
$
$
1&
5
1&
1&
6''
.#
666
'4
6664
6''4
1&
666
6''
6''
666
0337
Notes
2. LDM is the data mask signal for DQ[7:0], UDM is the data
mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL. VDDL is
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS,
and VSSQ are isolated on the device.
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is
data strobe for DQ[7:0]
Rev. 1.71, 2007-01
03062006-CPCN-4867
14
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
2.2
512 Mbit DDR2 Addressing
This chapter contents the table for the 512 Mbit DDR2 Addressing.
TABLE 9
DDR2 Addressing for × 4 Organization
1)
Configuration
128Mb x 4
Note
Bank Address
BA[1:0]
—
Number of Banks
4
—
Auto-Precharge
A10 / AP
—
Row Address
A[13:0]
—
Column Address
A11, A[9:0]
—
Number of Column Address Bits
11
2)
Number of I/Os
4
—
Page Size [Bytes]
1024 (1K)
3)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
TABLE 10
DDR2 Addressing for × 8 Organization
1)
Configuration
64Mb x 8
Bank Address
BA[1:0]
—
Number of Banks
4
—
Auto-Precharge
A10 / AP
—
Row Address
A[13:0]
—
Column Address
A[9:0]
—
Number of Column Address Bits
10
2)
Number of I/Os
8
—
Page Size [Bytes]
1024 (1K)
3)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
Rev. 1.71, 2007-01
03062006-CPCN-4867
15
Note
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 11
DDR2 Addressing for × 16 Organization
Configuration
32Mb x 161)
Note
Bank Address
BA[1:0]
—
Number of Banks
4
—
Auto-Precharge
A10 / AP
—
Row Address
A[12:0]
—
Column Address
A[9:0]
—
Number of Column Address Bits
10
2)
Number of I/Os
16
—
Page Size [Bytes]
2048 (2K)
3)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
Rev. 1.71, 2007-01
03062006-CPCN-4867
16
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
3
Functional Description
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Z
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TABLE 12
Mode Register Definition (BA[2:0] = 000B)
Field
Bits
Type1)
Description
BA2
16
reg. addr.
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B
BA2 Bank Address
BA1
15
Bank Address [1]
BA1 Bank Address
0B
BA0
14
Bank Address [0]
0B
BA0 Bank Address
A13
13
Address Bus [13]
Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration
0B
A13 Address bit 13
PD
12
w
Active Power-Down Mode Select
0B
PD Fast exit
1B
PD Slow exit
WR
[11:9]
w
Write Recovery 2)
Note: All other bit combinations are illegal.
001B
010B
011B
100B
101B
WR 2
WR 3
WR 4
WR 5
WR 6
DLL
8
w
DLL Reset
0B
DLL No
1B
DLL Yes
TM
7
w
Test Mode
0B
TM Normal Mode
1B
TM Vendor specific test mode
Rev. 1.71, 2007-01
03062006-CPCN-4867
17
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Field
Bits
Type1)
Description
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
011B
100B
101B
110B
111B
CL 3
CL 4
CL 5
CL 6
CL 7
BT
3
w
Burst Type
0B
BT Sequential
BT Interleaved
1B
BL
[2:0]
w
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.
Rev. 1.71, 2007-01
03062006-CPCN-4867
18
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
%$ %$ %$ $ $ $
$
$
$
$
$
$
$
$
$
$
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TABLE 13
Extended Mode Register Definition (BA[2:0] = 001B)
1)
Field
Bits
Type
BA2
16
reg. addr.
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B
BA2 Bank Address
BA1
15
Bank Address [1]
BA1 Bank Address
0B
BA0
14
Bank Address [0]
0B
BA0 Bank Address
A13
13
w
Address Bus [13]
Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration
0B
A13 Address bit 13
Qoff
12
Output Disable
0B
QOff Output buffers enabled
1B
QOff Output buffers disabled
RDQS
11
Read Data Strobe Output (RDQS, RDQS)
0B
RDQS Disable
1B
RDQS Enable
DQS
10
Complement Data Strobe (DQS Output)
0B
DQS Enable
1B
DQS Disable
OCD
[9:7]
Program
Rev. 1.71, 2007-01
03062006-CPCN-4867
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
19
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Field
Bits
Type1)
Description
AL
[5:3]
—
Additive Latency
Note: All other bit combinations are illegal.
000B
001B
010B
011B
100B
RTT
6,2
AL 0
AL 1
AL 2
AL 3
AL 4
Nominal Termination Resistance of ODT
Note: See Table 24 “ODT DC Electrical Characteristics” on Page 28
00B
01B
10B
11B
RTT ∞ (ODT disabled)
RTT 75 Ohm
RTT 150 Ohm
RTT 50 Ohm
DIC
1
Off-chip Driver Impedance Control
0B
DIC Full (Driver Size = 100%)
1B
DIC Reduced
DLL
0
DLL Enable
0B
DLL Enable
1B
DLL Disable
1) w = write only register bits
Rev. 1.71, 2007-01
03062006-CPCN-4867
20
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
%$ %$ %$ $ $ $
$
$
$
$
$
$
$
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$
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$
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TABLE 14
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B)
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address [2]
Note: BA2 is not available on 256 Mbit and 512 Mbit components
0B
BA2 Bank Address
BA1
15
Bank Adress [1]
1B
BA1 Bank Address
BA0
14
Bank Adress [0]
0B
BA0 Bank Address
A
[13:8]
w
Address Bus [13:8]
Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration
0B
SRF
[7]
w
Address Bus [7]
Note: When DRAM is operated at 85 °C ≤ TCASE < 95 °C the extended self refresh rate must
be enabled by setting bit A7 to "1" before the self refresh mode can be entered.
0B
1B
A
[6:0]
w
A [13:8] Address bits
A7 disable
A7 enable, adapted self refresh rate for TCASE > 85 °C
Address Bus [6:0]
0B
A [6:0] Address bits
1) w = write only
Rev. 1.71, 2007-01
03062006-CPCN-4867
21
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
%$ %$ %$ $ $ $
$
$
$
$
$
$
$
$
$
$
$
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GG
U
03%7
TABLE 15
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B)
1)
Field
Bits
Type
Description
BA2
16
reg.addr
Bank Address [2]
Note: BA2 is not available on 256 Mbit and 512 Mbit components
BA1
15
Bank Adress [1]
1B
BA1 Bank Address
BA0
14
Bank Adress [0]
BA0 Bank Address
1B
A
[13:0]
0B
w
BA2 Bank Address
Address Bus [13:0]
Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration
0B
A [13:0] Address bits
1) w = write only
Rev. 1.71, 2007-01
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 16
ODT Truth Table
Input Pin
EMRS(1) Address Bit A10
EMRS(1) Address Bit A11
×4 components
DQ[3:0]
X
DQS
X
DQS
0
DM
X
X
×8 components
DQ[7:0]
X
DQS
X
DQS
0
X
RDQS
X
1
RDQS
0
1
DM
X
0
×16 components
DQ[7:0]
X
DQ[15:8]
X
LDQS
X
LDQS
0
UDQS
X
UDQS
0
LDM
X
UDM
X
X
X
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
Rev. 1.71, 2007-01
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 17
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
×00
0, 1, 2, 3
0, 1, 2, 3
×01
1, 2, 3, 0
1, 0, 3, 2
×1 0
2, 3, 0, 1
2, 3, 0, 1
×1 1
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
8
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Notes
32Mb x 16 organization (CA[9:0]); Page Size = 2 KByte;
Page Length = 1024
2. Order of burst access for sequential addressing is “nibblebased” and therefore different from SDR or DDR
components
1. Page Size and Length is a function of I/O organization:
128Mb x 4 organization (CA[9:0], CA11); Page Size = 1
KByte; Page Length = 2048 64Mb x 8 organization
(CA[9:0]); Page Size = 1 KByte; Page Length = 1024
Rev. 1.71, 2007-01
03062006-CPCN-4867
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
4
Truth Tables
This chapter contains the truth tables.
TABLE 18
Command Truth Table
Function
CKE
CS RAS
CAS WE BA0
BA1
A[12:11]
A10 A[9:0]
Note1)2)3)
Previous
Cycle
Current
Cycle
(Extended) Mode
Register Set
H
H
L
L
L
L
BA
OP Code
Auto-Refresh
H
H
L
L
L
H
X
X
X
X
4)
Self-Refresh Entry
H
L
L
L
L
H
X
X
X
X
4)6)
Self-Refresh Exit
L
H
H
X
X
X
X
X
X
X
4)6)7)
L
H
H
H
4)5)
Single Bank Precharge
H
H
L
L
H
L
BA
X
L
X
4)5)
Precharge all Banks
H
H
L
L
H
L
X
X
H
X
4)
Bank Activate
H
H
L
L
H
H
BA
Row Address
Write
H
H
L
H
L
L
BA
Column
L
Column
4)5)8)
Write with AutoPrecharge
H
H
L
H
L
L
BA
Column
H
Column
4)5)8)
Read
H
H
L
H
L
H
BA
Column
L
Column
4)5)8)
Read with AutoPrecharge
H
H
L
H
L
H
BA
Column
H
Column
4)5)8)
No Operation
H
X
L
H
H
H
X
X
X
X
4)
Device Deselect
H
X
H
X
X
X
X
X
X
X
4)
Power Down Entry
H
L
H
X
X
X
X
X
X
X
4)9)
L
H
H
H
H
X
X
X
X
X
X
X
4)9)
L
H
H
H
Power Down Exit
L
H
4)5)
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.
6) VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements
Rev. 1.71, 2007-01
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25
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 19
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1)
CKE
Command (N)2) 3)
RAS, CAS, WE
Action (N)2)
Note4)5)
Previous Cycle6)
(N-1)
Current Cycle6)
(N)
L
L
X
Maintain Power-Down
7)8)11)
L
H
DESELECT or NOP
Power-Down Exit
7)9)10)11)
L
L
X
Maintain Self Refresh
8)11)12)
L
H
DESELECT or NOP
Self Refresh Exit
9)12)13)14)
Bank(s) Active
H
L
DESELECT or NOP
Active Power-Down Entry
7)9)10)11)15)
All Banks Idle
H
L
DESELECT or NOP
Precharge Power-Down
Entry
9)10)11)15)
H
L
AUTOREFRESH
Self Refresh Entry
7)11)14)16)
H
H
Refer to the Command Truth Table
Power-Down
Self Refresh
Any State other than
listed above
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
15)
16)
17)
17)
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
CKE must be maintained HIGH while the device is in OCD calibration mode.
Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
requirements
“X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2×tCKE + tIH.
VREF must be maintained during Self Refresh operation.
On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read
commands may be issued only after tXSRD (200 clocks) is satisfied.
Valid commands for Self Refresh Exit are NOP and DESELCT only.
Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
Refresh operations are in progress.
Self Refresh mode can only be entered from the All Banks Idle state.
Must be a legal command as defined in the Command Truth Table.
TABLE 20
Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
Write Inhibit
H
X
1)
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 1.71, 2007-01
03062006-CPCN-4867
26
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
5
AC & DC Operating Conditions
This chapter contains the AC & DC Operating Conditions.
5.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 21 at any time.
TABLE 21
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Parameter
Rating
Unit
Note
Min.
Max.
Voltage on VDD pin relative to VSS
–1.0
+2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on VDDL pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on any pin relative to VSS
–0.5
+2.3
V
1)
°C
1)2)
Storage Temperature
–55
+100
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 22
DRAM Component Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Operating Temperature
Min.
Max.
0
95
Unit
Note
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %
Rev. 1.71, 2007-01
03062006-CPCN-4867
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HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
5.2
DC Characteristics
This chapter describes the DC characteristics.
TABLE 23
Recommended DC Operating Conditions (SSTL_18)
Symbol
VDD
VDDDL
VDDQ
VREF
VTT
1)
2)
3)
4)
Parameter
Rating
Unit
Note
Min.
Typ.
Max.
Supply Voltage
1.7
1.8
1.9
V
1)
Supply Voltage for DLL
1.7
1.8
1.9
V
1)
Supply Voltage for Output
1.7
1.8
1.9
V
1)
Input Reference Voltage
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
2)3)
4)
Termination Voltage
VREF – 0.04
VREF
VREF + 0.04
V
VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to
be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in die dc level of VREF.
TABLE 24
ODT DC Electrical Characteristics
Parameter / Condition
Symbol
Min.
Nom.
Max.
Unit
Note
Termination resistor impedance value for
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Rtt1(eff)
60
75
90
Ω
1)
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Rtt2(eff)
120
150
180
Ω
1)
Termination resistor impedance value for
EMRS(1)(A6,A2)=[1,1]; 50 Ohm
Rtt3(eff)
40
50
60
Ω
1)
2)
+ 6.00
%
1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively.
Rtt(eff) = (VIH(ac) – VIL(ac)) I(I(VIHac) – I(VILac)).
2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) –
Deviation of VM with respect to VDDQ / 2
delta VM
–6.00
—
1) x 100%
TABLE 25
Input and Output Leakage Currents
Symbol
Parameter / Condition
Min.
Max.
Unit
Note
IIL
Input Leakage Current; any input 0 V < VIN < VDD
–2
+2
µA
1)
IOL
Output Leakage Current; 0 V < VOUT < VDDQ
–5
+5
µA
2)
1) all other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
Rev. 1.71, 2007-01
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HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS (and RDQS) signals are internally
disabled and don’t care.
TABLE 26
DC & AC Logic Input Levels
Symbol
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
Parameter
DDR2-400, DDR2-533
DDR2-667
Min.
Max.
Min.
Max.
DC input logic high
VREF + 0.125
–0.3
VDDQ + 0.3
VREF – 0.125
VREF + 0.125
DC input low
–0.3
VDDQ + 0.3
VREF – 0.125
V
AC input logic high
VREF + 0.250
—
VREF + 0.200
—
V
AC input low
—
VREF – 0.250
—
VREF – 0.200
V
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Unit
V
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 27
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Unit
Note
VREF
VSWING.MAX
Input reference voltage
0.5 x VDDQ
V
1)
Input signal maximum peak to peak swing
1.0
V
1)
SLEW
Input signal minimum Slew Rate
1.0
V / ns
2)3)
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to
VIL(ac).MAX for falling edges as shown in Figure 4
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative
transitions.
FIGURE 4
Single-ended AC Input Test Conditions Diagram
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HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 28
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
Min.
Max.
Unit
Note
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
VOX(ac)
DC input signal voltage
–0.3
—
1)
DC differential input voltage
0.25
—
2)
AC differential input voltage
0.5
V
3)
AC differential cross point input voltage
0.5 × VDDQ – 0.175
V
4)
AC differential cross point output voltage
0.5 × VDDQ – 0.125
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
V
5)
1)
2)
3)
4)
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc).
VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac).
The value of is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates
the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
FIGURE 5
Differential DC and AC Input and Output Logic Levels Diagram
VDDQ
VTR
Crossing Point
VID
VIX or VOX
VCP
VSSQ
SSTL18_3
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512-Mbit DDR2 SDRAM
5.4
Output Buffer Characteristics
This chapter describes the Output Buffer Characteristics.
TABLE 29
SSTL_18 Output DC Current Drive
Symbol
IOH
IOL
Parameter
SSTL_18
Output Minimum Source DC Current
–13.4
Unit
Note
mA
1)2)
2)3)
Output Minimum Sink DC Current
13.4
mA
1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and VDDQ – 280 mV.
2) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 3). They are used to test drive current capability to ensure VIH.MIN.
plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.
3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
TABLE 30
SSTL_18 Output AC Test Conditions
Symbol
Parameter
SSTL_18
Unit
Note
VOH
VOL
VOTR
Minimum Required Output Pull-up
VTT + 0.603
VTT – 0.603
0.5 × VDDQ
V
1)
V
1)
V
—
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
1) The SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition
assumes that ± 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an
additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device
(13.4 mA × 45 Ohm = 603 mV).
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HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 31
OCD Default Characteristics
Symbol
Description
Min.
Nominal
—
Output Impedance
—
—
Pull-up / Pull down mismatch
0
—
—
Output Impedance step size
for OCD calibration
0
—
Max.
Unit
Note
Ohms
1)2)
4
Ohms
1)2)3)
1.5
Ohms
4)
1)5)6)7)
Output Slew Rate
1.5
—
5.0
V / ns
1) Absolute Specifications (TOPER; VDD = 1.8 V ± 0.1 V; VDDQ = 1.8 V ± 0.1 V), altering OCD from default state no longer requires DRAM to
SOUT
2)
3)
4)
5)
6)
7)
meet timing, voltage and slew rate specifications on I/O’s.
Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT–VDDQ) / IOH must be less than
23.4 ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7
V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV.
Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the
DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal
conditions.
The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
This is verified by design and characterization but not subject to production test.
Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS
specification.
DRAM output Slew Rate specification applies to 400, 533 and 667 MHz speed bins.
5.5
Input / Output Capacitance
This chapter describes the Input / Output Capacitance.
TABLE 32
Input / Output Capacitance
Symbol
Parameter
DDR2-400 & DDR2-533
DDR2-667
Min.
Max.
Min.
Max.
Unit
CCK
Input capacitance, CK and CK
1.0
2.0
1.0
2.0
pF
CDCK
Input capacitance delta, CK and CK
—
0.25
—
0.25
pF
CI
Input capacitance, all other input-only pins
1.0
2.0
1.0
2.0
pF
CDI
Input capacitance delta, all other input-only pins
—
0.25
—
0.25
pF
CIO
Input/output capacitance,
DQ, DM, DQS, DQS, RDQS, RDQS
2.5
4.0
2.5
3.5
pF
CDIO
Input/output capacitance delta,
DQ, DM, DQS, DQS, RDQS, RDQS
—
0.5
—
0.5
pF
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HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
5.6
Overshoot and Undershoot Specification
This chapter describes the Overshoot and Undershoot Specification.
TABLE 33
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter
DDR2-400
DDR2-533
DD2-667
Unit
Maximum peak amplitude allowed for overshoot area
0.9
0.9
0.9
V
Maximum peak amplitude allowed for undershoot area
0.9
0.9
0.9
V
Maximum overshoot area above VDD
1.33
1.00
0.80
V.ns
Maximum undershoot area below VSS
1.33
1.00
0.80
V.ns
FIGURE 6
AC Overshoot / Undershoot Diagram for Address and Control Pins
9ROWV9
0D[LP
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2YH
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9''
966
0D[LP
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 34
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter
DDR2-400
DDR2-533
DD2-667
Unit
Maximum peak amplitude allowed for overshoot area
0.9
0.9
0.9
V
Maximum peak amplitude allowed for undershoot area
0.9
0.9
0.9
V
Maximum overshoot area above VDDQ
0.38
0.28
0.23
V.ns
Maximum undershoot area below VSSQ
0.38
0.28
0.23
V.ns
FIGURE 7
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
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9''
4
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4
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HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
6
Currents, Specifications,Conditions
This chapter contains the currents, specifications and conditions.
TABLE 35
IDD Measurement Conditions
Parameter
Symbol Note
Operating Current - One bank Active - Precharge
IDD0
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands. Address
and control inputs are switching; Databus inputs are switching.
1)2)3)4)5)
IDD1
1)2)3)4)5)
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD);
CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus
inputs are switching.
6)
6)
Precharge Power-Down Current
IDD2P
All banks idle; CKE is LOW; tCK = tCK(IDD); Other control and address inputs are stable; Data bus inputs are
floating.
1)2)3)4)5)
IDD2N
1)2)3)4)5)
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable, Data
bus inputs are floating.
1)2)3)4)5)
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching,
Data bus inputs are switching.
6)
6)
6)
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs
are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
IDD3P(0)
1)2)3)4)5)
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs
are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
IDD3P(1)
1)2)3)4)5)
Active Standby Current
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
IDD3N
1)2)3)4)5)
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS =
tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching; IOUT = 0 mA.
IDD4R
1)2)3)4)5)
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS =
tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching;
IDD4W
1)2)3)4)5)
Burst Refresh Current
tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
IDD5B
1)2)3)4)5)
Distributed Refresh Current
IDD5D
tCK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)5)
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6)
6)
6)
6)
6)
6)
6)
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HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Parameter
Symbol Note
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus
inputs are floating.
1)2)3)4)5)
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD),
tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs
are stable during deselects; Data bus is switching.
2. Timing pattern:
1)2)3)4)5)
6)
6)7)
DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized.
3) IDD parameter are specified with ODT disabled.
4)
5)
6)
7)
Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
Definitions for IDD: see Table 36
Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7..
A = Activate, RA = Read with Auto-Precharge, D=DESELECT
TABLE 36
Definition for IDD
Parameter
Description
LOW
defined as VIN ≤ VIL(ac).MAX
HIGH
defined as VIN ≥ VIH(ac).MIN
STABLE
defined as inputs are stable at a HIGH or LOW level
FLOATING
defined as inputs are VREF = VDDQ / 2
SWITCHING
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
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512-Mbit DDR2 SDRAM
TABLE 37
IDD Specification for HYB18T512xxxAF(L)
Symbol
–3
–3S
–3.7
–5
DDR2–667
DDR2–667
DDR2–533
DDR2–400
Max.
Max.
Max.
Max.
75
71
65
55
95
90
80
70
IDD1
90
85
75
60
110
104
90
75
IDD2N
IDD2P
IDD2P(L)
IDD2Q
IDD3N
IDD3P(MRS= 0)
IDD3P(MRS= 1)
IDD4R
50
50
40
5.5
5.5
5.5
IDD0
Unit
Note
mA
×4/×8
×16
mA
×4/×8
32
mA
—
5.5
mA
—
×16
—
—
2
—
mA
1)
40
40
30
25
mA
—
50
50
40
35
mA
—
19
19
16
13
mA
2)
6
6
5.5
5.5
mA
3)
130
130
90
70
mA
×4/×8
150
150
115
85
mA
×16
IDD4W
140
140
95
80
mA
×4/×8
170
170
130
110
mA
×16
IDD5B
IDD5D
IDD6
IDD6(L)
IDD7
140
140
130
120
mA
—
6
6
6
6
mA
4)
5.5
5.5
5.5
5.5
mA
4)
—
—
2
—
mA
1)4)
155
147
145
140
mA
×4/×8
240
228
220
210
mA
×16
1)
2)
3)
4)
For LowPower Components
MRS(12)=0
MRS(12)=1
0 ≤ TCASE ≤ 85°C
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HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
7
Electrical Characteristics
This chapter lists the electrical characteristics.
7.1
Speed Grade Definitions
This chapter contains the speed grade definition tables.
TABLE 38
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667C
DDR2–667D
QAG Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3
8
3.75
8
ns
1)2)3)4)
3
8
3
8
ns
1)2)3)4)
45
70000
45
70000
ns
1)2)3)4)5)
57
—
60
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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512-Mbit DDR2 SDRAM
TABLE 39
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
Speed Grade
DDR2–533C
DDR2–400B
IFX Sort Name
–3.7
–5
CAS-RCD-RP latencies
4–4–4
3–3–3
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3.75
8
5
8
ns
1)2)3)4)
3.75
8
5
8
ns
1)2)3)4)
45
70000
40
70000
ns
1)2)3)4)5)
60
—
55
—
ns
1)2)3)4)
15
—
15
—
ns
1)2)3)4)
15
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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512-Mbit DDR2 SDRAM
7.2
AC Timing Parameters
This chapter contains the AC timing parameters.
TABLE 40
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
Min.
Max.
tAC
tCCD
tCH.AVG
tCK.AVG
tCKE
–450
+450
ps
8)
2
—
nCK
—
0.48
0.52
tCK.AVG
9)10)
3000
8000
ps
—
3
—
nCK
11)
tCL.AVG
Auto-Precharge write recovery + precharge time tDAL
Minimum time clocks remain ON after CKE
tDELAY
0.48
0.52
tCK.AVG
9)10)
WR + tnRP
—
nCK
12)13)
tIS + tCK .AVG +
tIH
––
ns
—
tDH.BASE
DQ and DM input pulse width for each input
tDIPW
DQS output access time from CK / CK
tDQSCK
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS-DQ skew for DQS & associated DQ signals tDQSQ
DQS latching rising transition to associated clock tDQSS
175
––
ps
18)19)14)
0.35
—
tCK.AVG —
–400
+400
ps
0.35
—
0.35
—
tCK.AVG —
tCK.AVG —
—
240
ps
15)
– 0.25
+ 0.25
tCK.AVG
16)
tDS.BASE
tDSH
tDSS
tHP
100
––
ps
17)18)19)
16)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
asynchronously drops LOW
DQ and DM input hold time
edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
tHZ
Address and control input hold time
tIH.BASE
Control & address input pulse width for each input tIPW
Address and control input setup time
tIS.BASE
DQ low impedance time from CK/CK
tLZ.DQ
DQS/DQS low-impedance time from CK / CK
tLZ.DQS
MRS command to ODT update delay
tMOD
Mode register set command cycle time
tMRD
OCD drive mode output delay
tOIT
DQ/DQS output hold time from DQS
tQH
DQ hold skew factor
tQHS
Data-out high-impedance time from CK / CK
Rev. 1.71, 2007-01
03062006-CPCN-4867
41
8)
0.2
—
0.2
—
tCK.AVG
tCK.AVG
Min (tCH.ABS,
tCL.ABS)
__
ps
20)
—
tAC.MAX
ps
8)21)
275
—
ps
24)22)
0.6
—
tCK.AVG —
200
—
ps
23)24)
2 x tAC.MIN
ps
8)21)
tAC.MIN
tAC.MAX
tAC.MAX
ps
8)21)
0
12
ns
30)
2
—
nCK
—
0
12
ns
30)
tHP – tQHS
—
ps
25)
—
340
ps
26)
16)
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
Min.
Max.
–
–
7.8
3.9
µs
27)28)
30)
Average periodic refresh Interval
0°C ≤ TCASE ≤ 85°C
85°C ≤ TCASE ≤ 95°C
tREFI
Read preamble
tRPRE
tRPST
tRTP
tWPRE
tWPST
tWR
tWTR
tXARD
tXARDS
0.9
1.1
0.4
0.6
tCK.AVG
tCK.AVG
7.5
—
ns
0.35
—
0.4
0.6
tCK.AVG —
tCK.AVG —
15
—
ns
30)
7.5
—
ns
30)31)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Read postamble
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
—
27)29)
2
—
nCK
—
7 – AL
—
nCK
—
tXP
2
—
nCK
—
tRFC +10
—
ns
30)
Exit self-refresh to read command
tXSNR
tXSRD
200
—
nCK
—
Write command to DQS associated clock edges
WL
RL–1
nCK
—
Exit active power-down mode to read command
(slow exit, lower power)
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 4)5)6)7)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT.
7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
9) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
10) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
Rev. 1.71, 2007-01
03062006-CPCN-4867
42
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 9.
15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 9.
18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
22) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 10.
23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 10.
24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
25) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
26) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
27) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 8 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
28) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
30) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
Rev. 1.71, 2007-01
03062006-CPCN-4867
43
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
FIGURE 8
Method for calculating transitions and endpoint
92+[P9
977[P9
92+[P9
977[P9
W/=
W+=
W535(EHJLQSRLQW
W5367
H
QGSRLQW
92/[P9
977[P9
92/[P9
977[P9
7 7
7 7
W+=W5367
HQGSRLQW 77
W/=W535(
E HJLQSRLQW 7
7
FIGURE 9
Differential input waveform timing - tDS and tDS
'46
'46
W'6
W'+
W'6
W'+
9''4
9,+DFPLQ
9,+GFPLQ
95()GF
9,/GF PD[
9,/DF PD[
966
FIGURE 10
Differential input waveform timing - tlS and tlH
&.
&.
W,6
W,+
W,6
W,+
9''4
9,+DFPLQ
9,+GFPLQ
95()GF
9,/GFPD[
9,/DFPD[
966
Rev. 1.71, 2007-01
03062006-CPCN-4867
44
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 41
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note1)2)3)4)5)
6)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
–500
+500
ps
—
2
—
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
––
ns
8)
DQ and DM input hold time (differential data
strobe)
tDH(base)
225
––
ps
9)
–25
—
ps
10)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
0.35
—
tCK
—
–450
+450
ps
—
0.35
—
tCK
—
—
300
ps
10)
tDQSS
tDS(base)
– 0.25
+ 0.25
tCK
—
100
—
ps
10)
–25
—
ps
10)
tDSH
0.2
—
tCK
—
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
DQ and DM input hold time (single ended data tDH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data tDS1(base)
strobe)
DQS falling edge hold time from CK (write
cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Rev. 1.71, 2007-01
03062006-CPCN-4867
tHP
tHZ
tIH(base)
tIPW
45
—
—
7)17)
11)
MIN. (tCL, tCH)
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
—
—
tAC.MAX
ps
12)
375
—
ps
10)
0.6
—
tCK
—
250
—
ps
10)
2 × tAC.MIN
ps
13)
tAC.MIN
tAC.MAX
tAC.MAX
ps
13)
2
—
tCK
—
0
12
ns
—
tHP –tQHS
—
—
400
ps
—
—
7.8
µs
13)14)
—
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Parameter
Symbol
DDR2–533
Unit
Note1)2)3)4)5)
6)
Min.
Max.
tREFI
tRFC
—
3.9
µs
15)17)
105
—
ns
16)
tRP
tRP
tRPRE
tRPST
tRRD
tRP + 1tCK
—
ns
—
15 + 1tCK
—
ns
—
0.9
1.1
13)
0.40
0.60
tCK
tCK
7.5
—
ns
13)17)
Active bank A to Active bank B command
period
tRRD
10
—
ns
15)21)
Internal Read to Precharge command delay
tRTP
tWPRE
tWPST
tWR
7.5
—
ns
—
0.25
—
—
0.40
0.60
tCK
tCK
15
—
ns
—
tWTR
tXARD
7.5
—
ns
19)
2
—
tCK
20)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
20)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
—
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
—
200
—
—
tCK
tCK
—
tWR/tCK
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
Write recovery time for write with AutoWR
Precharge
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 4)5)6)7)
13)
18)
21)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
Rev. 1.71, 2007-01
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46
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for RoHS compliant
products” on Page 6.
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
TABLE 42
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
–600
+600
ps
—
2
—
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
––
ns
8)
DQ and DM input hold time (differential data
strobe)
tDH(base)
275
––
ps
9)
–25
—
ps
10)
0.35
—
tCK
—
–500
+500
ps
—
0.35
—
tCK
—
—
350
ps
10)
– 0.25
+ 0.25
tCK
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
DQ and DM input hold time (single ended data tDH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
Write command to 1st DQS latching transition tDQSS
—
—
—
7)20)
DQ and DM input setup time (differential data
strobe)
tDS(base)
150
—
ps
10)
DQ and DM input setup time (single ended
data strobe)
tDS1(base)
–25
—
ps
10)
Rev. 1.71, 2007-01
03062006-CPCN-4867
47
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)
Min.
Max.
tDSH
0.2
—
tCK
—
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
—
DQS falling edge hold time from CK (write
cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tHP
tHZ
tIH(base)
tIPW
11)
MIN. (tCL, tCH)
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
tREFI
—
tAC.MAX
ps
12)
475
—
ps
10)
0.6
—
tCK
—
350
—
ps
10)
2 × tAC.MIN
ps
13)
tAC.MIN
tAC.MAX
tAC.MAX
ps
13)
2
—
tCK
—
0
12
ns
—
tHP –tQHS
—
—
450
ps
—
—
7.8
µs
13)14)
—
3.9
µs
15)17)
105
—
ns
16)
tRP
tRP
tRPRE
tRPST
tRRD
tRP + 1tCK
15 + 1tCK
—
ns
—
—
ns
—
0.9
1.1
13)
0.40
0.60
tCK
tCK
7.5
—
ns
13)17)
Active bank A to Active bank B command
period
tRRD
10
—
ns
15)21)
Internal Read to Precharge command delay
tRTP
tWPRE
tWPST
tWR
7.5
—
ns
—
0.25
—
0.60
tCK
tCK
—
0.40
15
—
ns
—
tWTR
tXARD
10
—
ns
19)
2
—
tCK
20)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
20)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
—
Exit Self-Refresh to non-Read command
tXSNR
tRFC +10
—
ns
—
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Rev. 1.71, 2007-01
03062006-CPCN-4867
48
—
13)
18)
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)
Exit Self-Refresh to Read command
tXSRD
Write recovery time for write with AutoWR
Precharge
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 4)5)6)7)
Min.
Max.
200
—
tWR/tCK
—
tCK
tCK
—
21)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for RoHS compliant
products” on Page 6.
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Rev. 1.71, 2007-01
03062006-CPCN-4867
49
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
7.3
ODT AC Electrical Characteristics
This chapter contains the ODT AC electrical characteristics tables.
TABLE 43
ODT AC Characteristics and Operating Conditions for DDR2-667
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Note
Min.
Max.
ODT turn-on delay
2
2
nCK
1)
ODT turn-on
tAC.MAX + 0.7 ns
2 tCK + tAC.MAX + 1 ns
ns
1)2)
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT turn-off delay
2.5
2.5
nCK
1)
ns
1)3)
ns
1)
nCK
nCK
1)
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ODT to Power Down Mode Entry Latency
3
—
ODT turn-off
1)
ODT Power Down Exit Latency
8
—
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800. Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
Rev. 1.71, 2007-01
03062006-CPCN-4867
50
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 44
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Note
Min.
Max.
ODT turn-on delay
2
2
tCK
—
ODT turn-on
tAC.MAX + 1 ns
2 tCK + tAC.MAX + 1 ns
ns
1)
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
—
ODT turn-off delay
2.5
2.5
tCK
—
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
2)
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
—
ODT to Power Down Mode Entry Latency
3
—
—
ODT Power Down Exit Latency
8
—
tCK
tCK
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
Rev. 1.71, 2007-01
03062006-CPCN-4867
51
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
8
Package Dimensions
This chapter contains the package dimensions.
FIGURE 11
Package Outline PG-TFBGA-60
!8
X
!
X
!8
"
!8
#
-).
-!
8
#
’› X
’ - # ! "
’ - #
$U MM
Y PADSWITH OUTB ALL
-IDDLEO FP ACK A GESEDGES
0A CK AGEORIE NTATIONMA RK!
"A DUNITMA RKING "5 0'4&
"
'
! Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.71, 2007-01
03062006-CPCN-4867
0
,!.%
# 3%!4 ).'
52
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
FIGURE 12
Package Outline PG-TFBGA-84
[ $
[ 0
$;
%
0$
;
&
0
$;
0
,1
&
¡ “ [
¡ 0 $ %
&
¡ 0
'
XPP
\ SDGV Z
LWK RXWE DOO
0
LGGOHRISDFN DJHVHGJ HV
3
D FN D JHRULHQWDWLRQP
DUN$
%
DGX QLWP
DUNLQJ %8
0 '
LHVR UWILGXFLDO
Rev. 1.71, 2007-01
03062006-CPCN-4867
53
*3
/$1(
& 6($7 ,1
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
9
Product Nomenclature
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
TABLE 45
Nomenclature Fields and Examples
Example for
DDR2 DRAM
Field Number
1
2
3
4
5
6
HYB
18
T
512
16
7
8
9
10
11
0
A
C
–3.7
––
TABLE 46
DDR2 Memory Components
Field
Description
Values
Coding
1
QIMONDA
Component Prefix
HYB
Constant
2
Interface Voltage [V]
18
SSTL_18
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
256
256 M
512
512 M
5+6
Number of I/Os
7
Product Variations
8
Die Revision
9
10
11
Package,
Lead-Free Status
Speed Grade
N/A for Components
Rev. 1.71, 2007-01
03062006-CPCN-4867
54
1G
1 Gb
40
×4
80
×8
160
× 16
0 .. 9
look up table
A
First
B
Second
C
Third
C
FBGA,
lead-containing
F
FBGA, lead-free
–1.9
DDR2–1066
–2.5F
DDR2–800 5–5–5
–2.5
DDR2–800 6–6–6
–3
DDR2–667 4–4–4
–3S
DDR2–667 5–5–5
–3.7
DDR2–533 4–4–4
–5
DDR2–400 3–3–3
––
––
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Pin Configuration for × 4 components, PG-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration for × 8 components, PG-TFBGA-60-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration for × 16 components, PG-TFBGA-84-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . .
Method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input waveform timing - tDS and tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input waveform timing - tlS and tlH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline PG-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline PG-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.71, 2007-01
03062006-CPCN-4867
55
12
13
14
30
31
34
35
44
44
44
52
53
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Performance table for –3(S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Performance table for –3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Performance table for –3S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
High Performance for DDR2–400B and DDR2–533C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DDR2 Addressing for × 4 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDR2 Addressing for × 8 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDR2 Addressing for × 16 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Mode Register Definition (BA[2:0] = 000B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Extended Mode Register Definition (BA[2:0] = 001B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Differential DC and AC Input and Output Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SSTL_18 Output DC Current Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
OCD Default Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 35
IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
IDD Specification for HYB18T512xxxAF(L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Speed Grade Definition Speed Bins for DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DRAM Component Timing Parameter by Speed Grade - DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DRAM Component Timing Parameter by Speed Grade - DDR2–533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DRAM Component Timing Parameter by Speed Grade - DDR2-400. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ODT AC Characteristics and Operating Conditions for DDR2-667. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . 51
Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Rev. 1.71, 2007-01
03062006-CPCN-4867
135
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Table of Contents
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
5
6
2
2.1
2.1.1
2.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration for TFBGA–60 TFBGA–84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA Ball Out Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
512 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5
5.1
5.2
5.3
5.4
5.5
5.6
AC & DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Currents, Specifications,Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
7.1
7.2
7.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9
Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
27
27
28
29
32
33
34
39
39
41
50
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Rev. 1.71, 2007-01
03062006-CPCN-4867
137
Internet Data Sheet
Edition 2007-01
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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