TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 15V, 75mA High Efficient Buck Converter Check for Samples: TPS62120 , TPS62122 FEATURES 1 • • • • • • • • • • • • • • Wide Input Voltage Range 2V to 15V Up to 96% Efficiency Power Save Mode with 11 µA Quiescent Current Output Current 75mA Output Voltage Range 1.2V to 5.5V Up to 800kHz Switch Frequency Synchronous Converter, no External Rectifier Low Output Ripple Voltage 100% Duty Cycle for Lowest Dropout Small SOT 8 pin (TPS62120) and 2x2 SON 6 pin (TPS62122) Package Internal Soft Start Power Good Open Drain Output TPS62120 Open Drain Output for Output Discharge TPS62120 2.5V Rising / 1.85V Falling UVLO Thresholds APPLICATIONS • • • • DESCRIPTION The TPS6212X device family is a high efficient synchronous step down DC-DC converter optimized for low power applications. It supports up to 75mA output current and allows the use of tiny external inductors and capacitors. The wide operating input voltage range of 2V to 15V supports energy harvesting, battery powered and as well 9V or 12V line powered applications. With its advanced hysteretic control scheme the converter provides power save mode operation. At light loads the converter operates in PFM mode (pulse frequency modulation) and transitions automatically in PWM (pulse width modulation) mode at higher load currents. The Power Save Mode maintains high efficiency over the entire load current range. The hysteretic control scheme is optimized for low output ripple voltage in PFM mode in order to reduce output noise to a minimum. It consumes only 10uA quiescent current from VIN in PFM mode operation. In shutdown mode, the device is turned off. Low Power RF Applications Ultra Low Power Microprocessor Energy Harvesting Industrial Measuring An open drain power good output is available in the TPS62120 and indicates once the output voltage is in regulation. TPS62120 has an additional SGND pin which is connected to GND during shutdown mode. This output can be used to discharge the output capacitor. The TPS62120 is available in a small 3×3 mm2 8 pin SOT 23 package and the TPS62122 in a 2×2 mm2 6 pin SON package. 100 VIN = 5.5 V TPS62120 VIN VOUT = 1.8 V up to 75 mA L 22 mH 80 R1 CIN VIN = 8 V SW 300 kW EN 90 Cff 22 pF FB 4.7 mF R2 240 kW GND VOUT SGND COUT 4.7 mF Efficiency - % VIN = 2.5 V to 15 V VIN = 10 V VIN = 15 V VIN = 12 V 70 60 50 VO = 5 V, R pullup 100kW PG PWR GOOD L = 18 mH, LPS3015, CO = 4.7 mF 40 30 0.1 1 10 IO - Output Current - mA 100 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA –40°C to 85°C (1) (2) (3) PART NUMBER ACTIVE DISCHARGE SWITCH POWER GOOD VOUT PACKAGE PACKAGE DESIGNATOR CODE ORDERING (1) PACKAGE MARKING TPS62120 (2) yes Open Drain adjustable SOT 23-8 DCN TPS62120DCN QTX OFZ TPS62121 yes yes 2V fixed SOT 23-8 DCN samples available TPS62122 (3) no no adjustable DFN 2x2-6 DRV TPS62122DRV For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com The DCN package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel, T suffix for 250 parts per reel. The DRV package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel, T suffix for 250 parts per reel. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE Voltage at VIN (2) Voltage at SW PIN VI I IN MAX –0.3 17 dynamically during switching t < 10µs V 17 static DC V –0.3 6 Voltage at EN PIN (2) –0.3 VIN +0.3, but ≤17 V Voltage on FB Pin –0.3 3.6 V Voltage at PG , VOUT, SGND (2) –0.3 6 V 0.5 mA Current into PG pin ESD rating (3) UNIT MIN HBM Human body model 2 CDM Charge device model 1 Machine model kV 100 V Maximum operating junction temperature, TJ –40 125 °C Storage temperature range, Tstg –65 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal GND. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. THERMAL INFORMATION TPS62120 THERMAL METRIC (1) TPS62122 DCN DRV 8 PINS 6 PINS 114.4 qJA Junction-to-ambient thermal resistance 259.7 qJC(top) Junction-to-case(top) thermal resistance 114.1 73.7 qJB Junction-to-board thermal resistance 185.8 201.9 yJT Junction-to-top characterization parameter 21.6 0.8 yJB Junction-to-board characterization parameter 121.6 94.9 qJC(bottom) Junction-to-case(bottom) thermal resistance n/a 122.7 (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC PackageThermal Metrics application report, SPRA953 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 RECOMMENDED OPERATING CONDITIONS MIN Supply voltage VIN, device in operation Output current capability NOM MAX 2 VIN = 2 V, VOUT = 1.8 V, DCRL = 0.7 Ω 25 VIN ≥ 2.5 V, VOUT = 1.8 V, DCRL = 0.7 Ω 75 15 UNIT V mA Effective inductance 10 22 33 µH Effective output capacitance 1.0 2 33 µF Output voltage range 1.2 5.5 V –40 85 °C –40 125 °C Operating ambient temperature TA (1) , (Unless Otherwise Noted) Operating junction temperature range, TJ (1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (qJA), as given by the following equation: TA(max) = TJ(max) – (qJA × PD(max)). ELECTRICAL CHARACTERISTICS VIN = 8V, VOUT = 1.8V, EN = VIN, TJ = –40°C to 85°C, typical values are at TJ = 25°C (unless otherwise noted), CIN = 4.7µF, L = 22µH, COUT = 4.7µF, see Parameter Measurement Information PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2 15 V 18 µA SUPPLY Input voltage range (1) VIN IQ Quiescent current Device operating IOUT = 0mA, Device not switching, EN = VIN, regulator sleeps 11 IOUT = 0mA, Device switching, VIN = 8 V, VOUT = 1.8V 13 IActive Active mode current consumption VIN = 5.5 V = VOUT, TJ = 25°C, high-side MOSFET switch fully turned on ISD Shutdown current EN = GND, VOUT = SW = 0 V, VIN = 3.6V VUVLO Undervoltage lockout threshold 240 (2) µA 275 µA 0.3 1.2 µA Falling VIN 1.85 1.95 V Rising VIN 2.5 2.61 V 0.8 1.1 V ENABLE, THRESHOLD TH Threshold for detecting high EN 2 V ≤ VIN ≤ 15V, rising edge VIL TH HYS Threshold for detecting low EN 2 V ≤ VIN ≤ 15 V, falling edge IIN Input bias current, EN EN = GND or VIN VIH 0.4 0.6 V 0 50 2.3 3.4 nA POWER SWITCH RDS(ON) high-side MOSFET on-resistance low-side MOSFET on-resistance VIN = 3.6 V VIN = 8V 1.75 2.5 VIN = 3.6 V 1.3 2.5 VIN = 8V 1.2 1.75 250 400 Ω ILIMF Forward current limit MOSFET high-side VIN = 8V, Open loop TSD Thermal shutdown Increasing junction temperature 150 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C (1) (2) 200 mA The typical required supply voltage for startup is 2.5V. The part is functional down to the falling UVLO (Under Voltage Lockout) threshold Shutdown current into VIN pin, includes internal leakage Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 3 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 8V, VOUT = 1.8V, EN = VIN, TJ = –40°C to 85°C, typical values are at TJ = 25°C (unless otherwise noted), CIN = 4.7µF, L = 22µH, COUT = 4.7µF, see Parameter Measurement Information PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REGULATOR tONmin Minimum ON time VIN = 3.6 V, VOUT = 1.8 V 700 ns tOFFmin Minimum OFF time VIN = 3.6 V, VOUT = 1.8 V 60 ns VREF Internal reference voltage 0.8 V VFB Feedback FB voltage comparator threshold Referred to 0.8V internal reference –2.5% (3) Feedback FB voltage line regulation IOUT = 50 mA, IIN Input bias current FB VFB = 0.8 V tStart Regulator start-up time Time from active EN to device starts switching, VIN = 2.6V 0% 2.5% 0.04 (4) tRamp Output voltage ramp time Time to ramp up VOUT = 1.8V, no load ILK_SW Leakage current into SW pin VOUT = VIN = VSW = 1.8 V, EN = GND, device in shutdown mode %/V 0 50 50 150 120 300 1 1.5 nA µs µA POWER GOOD OUTPUT (TPS62120) VTHPG Power Good threshold voltage Rising VFB feedback voltage 93% 95% 97% Falling VFB feedback voltage 87% 90% 93% Current into PG pin I = 500 µA, VOUT > 1.5 V 165 VOL Output low voltage VH Output high voltage Open drain output, external pull up resistor 5.5 V Leakage current into PG pin V(PG) = 1.8V, EN = high, FB = 0.85 V 0 50 nA Leakage into VOUT pin V(OUT) = 1.8 V 0 50 nA Internal power good comparator delay time VOUT = 1.8 V 2 5 µs ILKG TPGDL Current into PG pin I = 100 µA, 1.2 V < VOUT <1.5 V 50 mV SGND OPEN DRAIN OUTPUT (TPS62120) RDSON NMOS drain source resistance SGND = 1.8 V, VIN = 2 V 370 ILKG Leakage current into SGND pin EN = VIN, SGND = 1.8 V 0 (3) (4) 4 Ω 50 nA VOUT +1V ≤ VIN ; VOUT ≤ 5.5V Maximum value not production tested Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 DEVICE INFORMATION PIN ASSIGNMENTS SOT-23 8 pin out DCN PACKAGE (TOP VIEW) SW 1 VOUT 2 FB 3 TH E ER XP M OS A ED L PA D 2x2SON 6 pin out DRV PACKAGE (TOP VIEW) 6 GND VIN 1 8 VOUT 5 VIN GND 2 7 SW 4 EN EN 3 6 PG SGND 4 5 FB PIN FUNCTIONS PIN NAME DRV NO. DCN NO. I/O DESCRIPTION VIN 5 1 PWR VIN power supply pin. GND 6 2 PWR GND supply pin. EN 4 3 IN Pulling this pin to high activates the device. Low level shuts it down. This pin must be terminated. SW 1 7 OUT This is the switch pin and is connected to the internal MOSFET switches. Connect the inductor to this terminal. Do not tie this pin to VIN, VOUT or GND. FB 3 5 IN This is the feedback pin for the regulator. Connect external resistor divider to this pin. SGND – 4 IN This pin is available in TPS62120 only. Open drain output which is turned on during shutdown mode (EN = 0) or VIN is below the UVLO threshold. It connects the SGND pin to GND via an internal MOSFET with typical 370Ω RDS(ON). When the device is enabled (EN = 1), this output is high impedance. To discharge the output capacitor during shutdown mode, connect this pin to VOUT (output capacitor) or leave it open. VOUT 2 8 IN PG – 6 OUT This pin must be connected to the output capacitor. This pin is available in TPS62120 only. Open drain power good output. Connect this terminal via a pull up resistor to a voltage rail up to 5.5V or leave it open. This pin can sink 500µA. Exposed Thermal PAD - Exposed Thermal Pad available only in DRV package option. This pad must be connected to GND. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 5 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN VIN Voltage Reference VREF 0.80 V UVLO Peak Current Limit Comparator VUVLO Limit High Side EN Softstart VIN PMOS Min. On Time VOUT Gate Driver Anti Shoot-Through Control Logic Min. OFF Time SW VREF NMOS VOUT FB Feedback Comparator Thermal Shutdown Integrated Divider in fixed output voltage versions ZeroCurrent Comparator GND Note Output Discharge Note PG PG SGND /EN FB VTHPG UVLO PG Comparator NOTE: Function available in TPS62120 PARAMETER MEASUREMENT INFORMATION VIN = 2 V to 15 V TPS62120 VIN SW R1 CIN 4.7 µ F EN VOUT 1.2 V - 5 V up to 75mA L 18 mH/22 mH COUT 4.7 mF Cff FB R2 GND VOUT SGND PG Rpullup PWR GOOD L = 18 µ H LPS3015 Coilcraft 22 mH LQH3NPN Murata CIN: 4.7µF GRM21B series X5R (0805size) 25V Murata COUT: 4.7µF GRM188 sereis X5R (0603size) 6.3V Murata 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 PARAMETER MEASUREMENT INFORMATION (continued) VIN = 2 V to 15 V TPS62122 VIN SW R1 CIN 4.7 µ F EN VOUT 1.2 V - 5 V up to 75mA L 18 mH/22 mH Cff FB COUT 4.7 mF R2 GND VOUT L = 18 µ H LPS3015 Coilcraft 22 mH LQH3NPN Murata CIN: 4.7µF GRM21B series X5R (0805size) 25V Murata COUT: 4.7µF GRM188 sereis X5R (0603size) 6.3V Murata Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 7 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com TYPICAL CHARACTERISTICS EFFICIENCY vs OUTPUT CURRENT IOUT (VOUT = 5V) EFFICIENCY vs INPUT VOLTAGE VIN (VOUT = 5V) 100 100 IO = 10 mA VIN = 5.5 V 95 VO = 5 V, IO = 25 mA IO = 50 mA 90 VIN = 8 V VIN = 10 V VIN = 15 V IO = 5 mA 85 VIN = 12 V Efficiency - % Efficiency - % 80 L = 18 mH, LPS3015 CO = 4.7mF 90 70 60 IO = 1 mA 80 75 IO = 0.1mA 70 65 50 VO = 5 V, 60 L = 18 mH, LPS3015, CO = 4.7 mF 40 30 0.1 55 50 1 10 IO - Output Current - mA 5 100 6 7 8 9 10 11 VI - Input Voltage - V Figure 2. EFFICIENCY vs OUTPUT CURRENT IOUT (VOUT = 3.3V) EFFICIENCY vs INPUT VOLTAGE VIN (VOUT = 3.3V) 14 15 100 IO = 25 mA 90 VO = 3.3 V, IO = 50 mA L = 18 mH, LPS3015, CO = 4.7 mF 90 IO = 10 mA VIN = 5 V VIN = 3.5 V 80 VIN = 9 V VIN = 12 V IO = 5 mA 80 VIN = 7 V Efficiency - % Efficiency - % 13 Figure 1. 100 70 12 VIN = 15 V 60 IO = 1 mA 70 IO = 0.1 mA 60 50 VO = 3.3 V, L = 18 mH, LPS3015, CO = 4.7 mF 40 30 0.1 1 10 IO - Output Current - mA 50 100 40 3 4 5 6 Figure 3. 8 7 8 9 10 VI - Input Voltage - V 11 12 13 14 15 Figure 4. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT IOUT (VOUT = 3.0V) 100 VIN = 3.5 V EFFICIENCY vs INPUT VOLTAGE VIN (VOUT = 3.0V) 100 VIN = 7 V VIN = 5 V IO = 25 mA 90 VO = 3 V, IO = 50 mA L = 18 mH, LPS3015, CO = 4.7 mF 90 80 70 IO = 1 mA 80 Efficiency - % Efficiency - % VIN = 9 V VIN = 12 V VIN = 15 V 60 IO = 5 mA IO = 10 mA 70 IO = 0.1 mA 60 50 VO = 3 V, L = 18 mH, LPS3015, CO = 4.7 mF 40 30 0.1 1 40 100 3 4 5 6 7 8 9 10 VI - Input Voltage - V 11 12 Figure 5. Figure 6. EFFICIENCY vs OUTPUT CURRENT IOUT (VOUT = 2.0V) EFFICIENCY vs INPUT VOLTAGE VIN (VOUT = 2.0V) 100 VIN = 4 V 90 10 IO - Output Current - mA 50 13 14 15 100 VIN = 2.5 V VO = 2 V, IO = 25 mA VIN = 6 V IO = 50 mA L = 18 mH, LPS3015, CO = 4.7 mF 90 IO = 10 mA 80 70 VIN = 12 V VIN = 8 V Efficiency - % Efficiency - % 80 VIN = 10 V VIN = 15 V 60 IO = 1 mA IO = 5 mA 70 60 50 IO = 0.1 mA VO = 2 V, L = 18 mH, LPS3015, CO = 4.7 mF 40 30 0.1 1 10 IO - Output Current - mA 50 100 40 2 3 4 5 Figure 7. 6 7 8 9 10 11 VI - Input Voltage - V 12 13 14 15 Figure 8. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 9 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT IOUT (VOUT = 1.2V) EFFICIENCY vs INPUT VOLTAGE VIN (VOUT = 1.2V) 100 VIN = 5 V 90 VIN = 3 V VIN = 4 V 100 VIN = 2 V VO = 1.2 V, 90 IO = 10 mA 80 IO = 25 mA L = 18 mH, LPS3015, CO = 4.7 mF IO = 50 mA 80 VIN = 8 V 60 Efficiency - % Efficiency - % 70 VIN = 10 V VIN = 12 V 50 VIN = 15 V 40 70 IO = 1 mA 50 30 VO = 1.2 V, 20 10 0 0.1 1 10 IO - Output Current - mA IO = 0.1 mA 40 L = 18 mH, LPS3015, CO = 4.7 mF 30 20 100 2 3 5 6 8 9 10 11 VI - Input Voltage - V 3.0V OUTPUT VOLTAGE DC REGULATION 2.0V OUTPUT VOLTAGE DC REGULATION 12 13 14 15 2.06 VOUT = 2 V, L = 18 mH LPS3015, COUT = 4.7 mF VIN = 12 V VO - Output Voltage DC - V VIN = 15 V 3.03 VIN = 10 V 3 VIN = 3.5 V L = 18 mH LPS3015, COUT = 4.7 mF 2.04 VIN = 4 V V = 5 V IN VIN = 7 V 2.97 2.94 VIN = 9 V 2.02 VIN = 12 V VIN = 15 V 2 VIN = 2.5 V V = 3 V V = 5 V IN IN VIN = 7 V 1.98 1.96 2.91 0.01 0.1 1 IO - Output Current - mA 10 100 1.94 0.01 0.1 Figure 11. 10 7 Figure 10. VOUT = 3 V, VO - Output Voltage DC - V 4 Figure 9. 3.09 3.06 IO = 5 mA 60 1 IO - Output Current - mA 10 100 Figure 12. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 TYPICAL CHARACTERISTICS (continued) LOW-SIDE SWITCH RESISTANCE RDS(ON) vs VIN QUIESCENT CURRENT vs VIN 3.5 20 16 TA = 85°C 2.5 Iq - Quiescent current - mA RDSon - Low side Switch Resistance - W 18 3 TA = 60°C TA = 25°C TA = -40°C 2 1.5 1 TA = 85°C 14 TA = 60°C 12 TA = 25°C 10 8 TA = -40°C 6 Device enabled and UVLO rising threshold has been tripped 4 0.5 2 0 0 0 2 4 6 8 10 VI - Input Voltage - V 12 14 0 16 2 4 Figure 14. SHUTDOWN CURRENT vs VIN SWITCH FREQUENCY vs OUTPUT CURRENT IOUT (VOUT = 2.0V) 14 16 70 80 900 VIN = 7 V VOUT = 2 V, 1.6 TA = 85°C 800 L = 18 mH LPS3015, COUT = 4.7 mF 700 1.4 TA = 60°C 1.2 1 TA = 25°C 0.8 TA = -40°C 0.6 500 0.2 100 6 8 10 VI - Input Voltage - V 12 14 16 VIN = 3 V VIN = 12 V VIN = 15 V 300 200 4 VIN = 9 V 400 0.4 2 VIN = 5 V 600 f - Frequency - kHz ISD - Shutdown Current - mA 12 Figure 13. 1.8 0 0 6 8 10 VI - Input Voltage - V 0 0 10 20 Figure 15. 30 40 50 IO - Output Current - mA 60 Figure 16. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 11 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCH FREQUENCY vs OUTPUT CURRENT IOUT (VOUT = 3.3V) 900 800 VOUT = 3.3 V, SWITCH FREQUENCY vs OUTPUT CURRENT IOUT (VOUT = 5.0V) 900 VIN = 9 V L = 22 mH LQH3NPN, COUT = 4.7 mF VOUT = 5.0 V, VIN = 7 V 800 700 L = 18 mH LPS3015, COUT = 4.7 mF VIN = 12 V 700 600 f - Frequency - kHz f - Frequency - kHz VIN = 5 V VIN = 12 V 500 VIN = 15 V 400 300 200 VIN = 7 V 500 400 300 VIN = 15 V 200 100 0 0 VIN = 9 V 600 100 10 20 30 40 50 IO - Output Current - mA 60 70 80 0 0 10 20 30 40 50 IO - Output Current - mA 60 Figure 17. Figure 18. VOUT 2.0V OUTPUT RIPPLE VOLTAGE PEAK TO PEAK TYPICAL OPERATION IOUT 60mA 70 80 50 VOUT = 2 V, 45 L = 18 mH, COUT = 4.7 mF VO - Ripple Peak to Peak - mV 40 35 30 VIN = 7 V 25 VIN = 9 V VIN = 12 V VIN = 15 V 20 15 10 5 VIN = 2.5 V 0 0 10 VIN = 3 V 20 VIN = 5 V 30 40 50 IO - Output Current - mA 60 70 80 Figure 19. 12 Figure 20. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 TYPICAL CHARACTERISTICS (continued) TYPICAL OPERATION IOUT 10mA LINE TRANSIENT RESPONSE FOR 3V OUTPUT VOLTAGE Figure 21. Figure 22. LOAD TRANSIENT RESPONSE FOR 3V OUTPUT VOLTAGE AC LOAD REGULATION PERFORMANCE FOR 3V OUTPUT VOLTAGE Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 13 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS62120 SPURIOUS OUTPUT NOISE COUT = 4.7 µF TPS62120 SPURIOUS OUTPUT NOISE COUT = 10 µF VIN = 10V VIN = 5V VIN = 10V VIN = 3.3V 14 VIN = 5V Load = 68R L = 22uH (LQH32PN) COUT = 4.7uF (0603) VOUT = 1.8V VIN = 3.3V Load = 68R L = 22uH (LQH32PN) COUT = 10uF (0805) VOUT = 1.8V Figure 25. Figure 26. AC LOAD REGULATION PERFORMANCE FOR 1.8V OUTPUT VOLTAGE OUTPUT DISCHARGE WITH SGND PIN CONNECTED TO VOUT Figure 27. Figure 28. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 TYPICAL CHARACTERISTICS (continued) STARTUP VOUT = 3.0V POWER GOOD OUTPUT DURING STARTUP Figure 29. Figure 30. STARTUP VOUT 1.8V OUTPUT OVERLOAD PROTECTION Figure 31. Figure 32. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 15 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 16 INPUT VOLTAGE RAMP UP/DOWN STARTUP FROM A HIGH IMPEDANCE SOURCE Figure 33. Figure 34. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 DETAILED DESCRIPTION OPERATION The TPS6212x synchronous step down converter family uses an unique hysteretic PFM/PWM controller scheme which enables switching frequencies of up to 800kHz, excellent transient response and AC load regulation at operation with small output capacitors. At high load currents the converter operates in quasi fixed frequency PWM mode operation and at light loads in PFM (Pulse Frequency Modulation) mode to maintain highest efficiency over the full load current range. In PFM Mode, the device generates a single switch pulse to ramp the inductor current and charge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to achieve a quiescent current of typically 10µA. During this time, the load current is supported by the output capacitor. The duration of the sleep period depends on the load current and the inductor peak current. A significant advantage of TPS6212x compared to other hysteretic controller topologies is its excellent DC and AC load regulation capability in combination with low output voltage ripple over the entire load range which makes this part well suited for audio and RF applications. Main Control Loop The feedback comparator monitors the voltage on the FB pin and compares it to an internal 800mV reference voltage. The feedback comparator trips once the FB voltage falls below the reference voltage. A switching pulse is initiated and the high-side MOSFET switch is turned on. It remains turned on at least for the minimum On Time TONmin of typical 700ns until the feedback voltage is above the reference voltage or the inductor current reaches the high-side MOSFET switch current limit ILIMF. Once the high-side MOSFET switch turns off, the low-side MOSFET switch is turned on and the inductor current ramps down. It is turned on at least for the minimum Off Time TOFFmin of typically 60ns. The low-side MOSFET switch stays turned on until the FB voltage falls below the internal reference and trips the FB comparator again. This will turn on the high-side MOSFET switch for a new switching cycle. If the feedback voltage stays above the internal reference the low-side MOSFET switch is turned on until the zero current comparator trips and indicates that the inductor current has ramped down to zero. In this case, the load current is much lower than the average inductor current provided during one switching cycle. The regulator turns the low-side and high-side MOSFET switches off (high impedance state) and enters a sleep cycle with reduced quiescent current of typically 10uA until the output voltage falls below the internal reference voltage and the feedback comparator trips again. This is called PFM Mode and the switching frequency depends on the load current, input voltage, output voltage and the external inductor value. Once the high-side switch current limit comparator has tripped its threshold of ILIMF, the high-side MOSFET switch is turned off and the low-side MOSFET switch is turned on until the inductor current has ramped down to zero. The minimum On Time TONmin for a single pulse can be estimated to: V TON = OUT ´ 1.3 μs VIN (1) Therefore the peak inductor current in PFM mode is approximately: (VIN - VOUT ) ´ T ILPFMpeak = ON L (2) The transition from PFM mode to PWM mode operation and back occurs at a load current of approximately ½ ILPFMpeak. With: TON: high-side MOSFET switch on time [µs] VIN: Input voltage [V] VOUT: Output voltage [V] L : Inductance [µH] ILPFMpeak : PFM inductor peak current [mA] Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 17 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com The maximum switch frequency can be estimated to: 1 fSWmax » = 770 kHz 1.3 μs (3) 100% DUTY CYCLE LOW DROPOUT OPERATION The device will increase the On Time of the high-side MOSFET switch once the input voltage comes close to the output voltage in order to keep the output voltage in regulation. This will reduce the switch frequency. With further decreasing input voltage VIN the high-side MOSFET switch is turned on completely. In this case the converter provides a low input-to-output voltage difference. This is particularly useful in applications with widely variable supply voltage to achieve longest operation time by taking full advantage of the whole supply voltage span. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: Vinmin = Voutmax + Ioutmax ´ (RDSONmax + R L ) (4) With: IOUTmax = maximum output current RDS(ON)max = maximum P-channel switch RDS(ON). RL = DC resistance of the inductor VOUTmax = nominal output voltage plus maximum output voltage tolerance UNDER-VOLTAGE LOCKOUT The under-voltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the converter from turning on the high-side MOSFET switch or low-side MOSFET under undefined conditions. The UVLO threshold is set to 2.5V typical for rising VIN and 1.85V typical for falling VIN. The hysteresis between rising and falling UVLO threshold ensures proper start up even with high impedance sources. Fully functional operation is permitted for an input voltage down to the falling UVLO threshold level. The converter starts operation again once the input voltage trips the rising UVLO threshold level. SOFT START The TPS6212X has an internal soft-start circuit which controls the ramp up of the output voltage and limits the inrush current during start-up. This limits input voltage drop when a battery or a high-impedance power source is connected to the input of the converter. The soft-start system generates a monotonic ramp up of the output voltage with a ramp of typically 15mV/µs and reaches an output voltage of 1.8V in typically 170µs after EN pin was pulled high. TPS6212X is able to start into a pre biased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value. During start up the device can provide an output current of half of the high-side MOSFET switch current limit ILIMF. Large output capacitors and high load currents may exceed the current capability of the device during start up. In this case the start up ramp of the output voltage will be slower. ENABLE/SHUTDOWN The device starts operation when EN pin is set high and the input voltage VIN has tripped the under voltage lockout threshold UVLO for rising VIN. It starts switching after the regulator start up time tStart of typically 50µs has expired and enters the soft start as previously described. For proper operation, the EN pin must be terminated and must not be left floating. EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.3µA. In this mode, the high-side and low-side MOSFET switches as well as the entire internal-control circuitry are switched off. In TPS62120 the internal N-MOSFET at pin SGND is activated and connects SGND to GND. 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 POWER GOOD OUTPUT The Power Good Output is an open drain output available in TPS62120. The circuit is active once the device is enabled. It is driven by an internal comparator connected to the FB voltage and internal reference. The PG output provides a high level (open drain high impedance) once the feedback voltage exceeds typical 95% of its nominal value. The PG output is driven to low level once the feedback voltage falls below typ. 90% of its nominal value. The PG output is high (high impedance) with an internal delay of typically 2µs. A pullup resistor is needed to generate a high level and limit the current into the PG pin to 0.5mA. The PG pin can be connected via an pull up resistors to a voltage up to 5.5V The PG output is pulled low if the device is enabled but the input voltage is below the undervoltage lockout threshold UVLO or the device is turned into shutdown mode. SGND OPEN DRAIN OUTPUT This is an NMOS open drain output with a typical RDS(on) of 370Ω and can be used to discharge the output capacitor. The internal NMOS connects SGND pin to GND once the device is in shutdown mode or VIN falls below the UVLO threshold during operation. SGND becomes high impedance once the device is enabled and VIN is above the UVLO threshold. If SGND is connected to the output, the output capacitor is discharged through SGND. SHORT-CIRCUIT PROTECTION The TPS6212X integrates a high-side MOSFET switch current limit ILIMF to protect the device against short circuit. The current in the high-side MOSFET switch is monitored by current limit comparator and once the current reaches the limit of ILIMF , the high-side MOSFET switch is turned off and the low-side MOSFET switch is turned on to ramp down the inductor current. The high-side MOSFET switch is turned on again once the zero current comparator trips and the inductor current has become zero. In this case, the output current is limited to half of the high-side MOSFET switch current limit ½ ILIMF. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 19 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com APPLICATION INFORMATION VOUT 1.8 V 25 mA TPS62120 VIN = 2 V to 15 V L 22 µH SW VIN CIN 4.7 µF R1 300 kW EN FB COUT 4.7 µF Cff 22pF R2 240 kW GND VOUT Rpullup100 kW SGND PWR GOOD PG Figure 35. TPS62120 1.8V Output Voltage Configuration VOUT 3.06 V 75 mA TPS62120 VIN = 3.5 V to 15 V L 22 µH SW VIN CIN 4.7 µF R1 510 kW EN FB COUT 4.7 µF Cff 22 pF R2 180 kW GND VOUT Rpullup100 kW SGND PWR GOOD PG Figure 36. TPS62120 3.06V Output Voltage Configuration VOUT = 2.0 V IOUT = 25 mA TPS62122 VIN = 2.1 V to 15 V L 22 µH VIN CIN 4.7 µF EN SW R1 360 kW FB Cff 22 pF COUT 4.7 µF R2 240 kW GND VOUT Figure 37. TPS62122 2.0V Output Voltage Configuration 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 High Impedance Source VOUT 1.8 V 100 µA TPS62120 L 22 µH SW VIN 1 kW DC 12 V R1 300 kW EN CIN 10 µF FB Cff 22 pF COUT 4.7 µF R2 240 kW GND VOUT Rpullup100 kW SGND PWR GOOD PG Figure 38. TPS62120 1.8V VOUT Configuration Powered from a High-Impedance Source OUTPUT VOLTAGE SETTING The output voltage can be calculated to: ( VOUT = VREF ´ 1 + R1 = (VV OUT REF R1 R2 ) with an internal reference voltage VREF typical 0.8 V ) - 1 ´ R2 (5) To minimize the current through the feedback divider network, R2 should be within the range of 82kΩ to 360k. The sum of R1 and R2 should not exceed ~1MΩ, to keep the network robust against noise. An external feed-forward capacitor Cff is required for optimum regulation performance. R1 and Cff places a zero in the feedback loop. 1 fz = = 25 kHz 2 ´ p ´ R1 ´ Cf f (6) The value for Cff can be calculated as: 1 C ff = 2 ´ p ´ R1 ´ 25 kHz (7) Table 1 shows a selection of suggested values for the feedback divider network for most common output voltages. Table 1. Suggested Values for Feedback Divider Network Voltage Setting [V] 3.06 3.29 2.00 1.80 1.20 5.00 R1 [kΩ] 510 560 360 300 180 430 R2 [kΩ] 180 180 240 240 360 82 Cff [pF] 15 22 22 22 27 15 OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) The TPS6212X operates with effective inductance values in the range of 10µH to 33µH and with effective output capacitance in the range of 1µF to 33µF. The device is optimized to operate for an output filter of L = 22µH and COUT = 4.7µF. Larger or smaller inductor/capacitor values can be used to optimize the performance of the device for specific operation conditions. For more details, see the CHECKING LOOP STABILITY section. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 21 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com INDUCTOR SELECTION The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage ripple and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN or VOUT and can be estimated according Equation 8. Equation 9 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 9. This is recommended because during heavy load transient the inductor current will rise above the calculated value. A more conservative way is to select the inductor saturation current according to the high-side MOSFET switch current limit ILIMF. (VIN - VOUT ) DIL = ´ TON L (8) ΔIL ILmax = Ioutmax + 2 (9) With: TON = see equation (3) L = Inductor Value ΔIL = Peak to Peak inductor ripple current ILmax = Maximum Inductor current In DC/DC converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e. quality factor) and by the inductor DCR value. To achieve high efficiency operation, care should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. The total losses of the coil consist of both the losses in the DC resistance R(DC)) and the following frequency-dependent components: • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) • Additional losses in the conductor from the skin effect (current displacement at high frequencies) • Magnetic field losses of the neighboring windings (proximity effect) • Radiation losses The following inductor series from different suppliers have been used with the TPS6212X converters. Table 2. List of Inductors INDUCTANCE [µH] DIMENSIONS [mm3] INDUCTOR TYPE SUPPLIER 22 3 × 3 × 1.5 LQH3NPN Murata 18/22 3 × 3 × 1.5 LPS3015 Coilcraft OUTPUT CAPACITOR SELECTION The unique hysteretic PFM/PWM control scheme of the TPS6212x allows the use of ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At light load currents the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM Mode. 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 TPS62120 TPS62122 www.ti.com SLVSAD5 – JULY 2010 INPUT CAPACITOR SELECTION Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications a 4.7µF to 10µF ceramic capacitor is recommended. The voltage rating and DC bias characteristic of ceramic capacitors need to be considered. The input capacitor can be increased without any limit for better input voltage filtering. For specific applications like energy harvesting a tantalum or tantalum polymer capacitor can be used to achieve a specific DC/DC converter input capacitance. Tantalum capacitors provide much better DC bias performance compared to ceramic capacitors. In this case a 1µF or 2.2µF ceramic capacitor should be used in parallel to provide low ESR. Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce large ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings. Table 3 shows a list of input/output capacitors. Table 3. List of Capacitor CAPACITANCE [µF] SIZE CAPACITOR TYPE USAGE SUPPLIER 4.7 0603 GRM188 series 6.3V X5R COUT Murata 2.2 0603 GRM188 series 6.3V X5R COUT Murata 4.7 0805 GRM21Bseries 25V X5R CIN Murata 10 0805 GRM21Bseries 16V X5R CIN Murata 8.2 B2(3.5 × 2.8 × 1.9) 20TQC8R2M (20V) CIN Sanyo CHECKING LOOP STABILITY The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: • Switching node, SW • Inductor current, IL • Output ripple voltage, VO(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination. As a next step in the evaluation of the regulation loop, the load transient response is tested. During application of the load transient and the turn on of the high-side MOSFET switch, the output capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) × ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when the device operates in PWM mode. During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET RDS(on)) which are temperature dependent, the loop stability analysis should be done over the input voltage range, load current range, and temperature range LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 23 TPS62120 TPS62122 SLVSAD5 – JULY 2010 www.ti.com Use a common Power GND node and a different node for the signal GND to minimize the effects of ground noise. Keep the common path to the GND PIN, which returns the small signal components and the high current of the output capacitors as short as possible to avoid ground noise. The FB divider network and the VOUT line must be connected to the output capacitor. The VOUT pin of the converter should be connected via a short trace to the output capacitor. The FB line must be routed away from noisy components and traces (e.g., SW line). 10.5 mm GND VIN VOUT COUT L CIN 7.9 mm GND R2 R1 CFF RPG EN PG SGND VOUT Figure 39. PCB Layout - DCN Package 11.1 mm GND VOUT CFF 8.1 mm R2 FB R1 VIN COUT EN FB CIN L GND Figure 40. PCB Layout - DRV Package 24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS62120 TPS62122 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS62120DCNR PREVIEW SOT-23 DCN 8 3000 TBD Call TI Call TI Samples Not Available TPS62120DCNT PREVIEW SOT-23 DCN 8 250 TBD Call TI Call TI Samples Not Available TPS62122DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples TPS62122DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS62122DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS62122DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62122DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS62122DRVT SON DRV 6 250 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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