SAMSUNG S3P7235

S3C7238/P7238/C7235/P7235
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the S3C7238/C7235 offer
an excellent design solution for a wide variety of applications that require LCD functions.
Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response
to internal and external events. In addition, the S3C7238/C7235's advanced CMOS technology provides for low
power consumption and a wide operating voltage range.
OTP
The S3C7238/C7235 microcontroller is also available in OTP (One Time Programmable) version,
S3P7238/P7235. S3P7238/P7235 microcontroller has an on-chip 8/16-Kbyte one-time-programmable EPROM
instead of masked ROM. The S3P7238/P7235 is comparable to S3C7238/C7235, both in function and in pin
configuration.
1-1
PRODUCT OVERVIEW
S3C7238/P7238/C7235/P7235
FEATURES
Memory
–
512 × 4-bit RAM
–
8 K × 8-bit ROM (S3C7238/P7238)
–
16 K × 8-bit ROM (S3C7235/P7235)
Bit Sequential Carrier
–
Support 16-bit serial data transfer in arbitrary
format
Interrupts
I/O Pins
–
Three internal vectored interrupts
–
–
–
–
Three external vectored interrupts
–
Two quasi-interrupts
Input only: 8 pins
I/O: 24 pins
Output: 8 pins sharing with segment driver
outputs
LCD Controller/Driver
–
Maximum 16-digit LCD direct drive capability
–
32 segment, 4 common pins
–
Display modes: Static, 1/2 duty (1/2 bias),
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
Memory-Mapped I/O Structure
–
Data memory bank 15
Two Power-Down Modes
–
Idle mode (only CPU clock stops)
–
Stop mode (main or sub system oscillation stops)
8-Bit Basic Timer
Oscillation Sources
–
Programmable interval timer
–
Crystal, ceramic, or RC for main system clock
–
Watchdog timer
–
Crystal or external oscillator for subsystem clock
–
Main system clock frequency: 4.19 MHz (typical)
8-Bit Timer/Counter 0
–
Subsystem clock frequency: 32.768 kHz
–
Programmable 8-bit timer
–
CPU clock divider circuit (by 4, 8, or 64)
–
External event counter
–
Arbitrary clock frequency output
Instruction Execution Times
–
Serial I/O interface clock generator
–
0.95, 1.91, 15.3 µs at 4.19 MHz (main)
–
122 µs at 32.768 kHz (subsystem)
Watch Timer
–
Real-time and interval time measurement
Operating Temperature
–
Four frequency outputs to BUZ pin
–
–
Clock source generation for LCD
8-Bit Serial I/O Interface
– 40 °C to 85 °C
Operating Voltage Range
–
1.8 V to 5.5 V
–
8-bit transmit/receive mode
–
8-bit receive only mode
Package Type
–
LSB-first or MSB-first transmission selectable
–
–
Internal or external clock source
1-2
80-pin QFP
S3C7238/P7238/C7235/P7235
PRODUCT OVERVIEW
BLOCK DIAGRAM
Watch-Dog
Timer
INT0, INT1,INT2
P1.3/TCL0
P2.0/TCLO0
RESET
XIN
XTIN
P4.0-P4.3
I/O Port 3
P5.0-P5.3
I/O Port 4
P6.0-P6.3/
KS0-KS3
I/O Port 6
P7.0-P7.3/
KS4-KS7
I/O Port 7
Watch
Timer
P2.3/BUZ
XOUT
XTOUT
8-Bit Timer/
Counter 0
Interrupt
Control
Block
Basic
Timer
Clock
Instruction
Register
LCD Drive/
Controller
P8.0-P8.7/
SEG24-SEG31
4-Bit
Accumulator
Internal
Interrupts
Instruction Decoder
I/O Port 0
P0.0/INT4
P0.1/SCK
P0.2/SO
P0.3/SI
Input Port 1
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/TCL0
Program
Counter
Program
Status Word
FLAGS
I/O Port 2
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
I/O Port 3
P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3
Arithmetic and Logic Unit
Stack
Pointer
P8.0-P8.7/
SEG24-SEG31
I/O Port 8
512 x 4-Bit
Data
Memory
8/16-Kbyte
Program
Memory
BIAS
VLC0-VLC2
LCDCK/P3.0
LCDSY/P3.1
COM0-COM3
SEG0-SEG23
Serial I/O
Port
P0.1 P0.2 P0.3
/SCK /SO /SI
Figure 1-1. S3C7238/C7235 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C7238/P7238/C7235/P7235
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S3C7238
S3C7235
(TOP VIEW)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P1.1/INT1
P1.2/INT2
P1.3/TCL0
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
P3.0/LCDCK
P3.1/SCDSY
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
P5.0
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
BIAS
VLC0
SDAT / VLC1
SCLK / VLC2
VDD / VDD
VSS / VSS
Xout
Xin
TEST / TEST
XTin
XTout
RESET / RESET
P0.0/INT4
P0.1/SCK
P0.2/SO
P0.3/SI
P1.0/INT0
Figure 1-2. S3C7238/C7235 80-QFP Pin Assignment Diagram
1-4
SEG19
SEG20
SEG21
SEG22
SEG23
P8.0/SEG24
P8.1/SEG25
P8.2/SEG26
P8.3/SEG27
P8.4/SEG28
P8.5/SEG29
P8.6/SEG30
P8.7/SEG31
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
S3C7238/P7238/C7235/P7235
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7238/C7235 Pin Descriptions
Pin Name
Pin
Type
Description
Number
Reset
Value
Circuit
Type
P0.0
P0.1
P0.2
P0.3
I
I/O
I/O
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are software assignable.
20
21
22
23
INT4
Input
A-1
D*
D*
A-1
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are software assignable.
24
25
26
27
INT0
INT1
INT2
TCL0
Input
A-1
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
4-bit pull-up resistors are software assignable.
28
29
30
31
TCLO0
–
CLO
BUZ
Input
D
P3.0
P3.1
P3.2
P3.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Each individual pin can be specified as input
or output. 4-bit pull-up resistors are software
assignable.
32
33
34
35
LCDCK
LCDSY
Input
D
P4.0–
P4.3
P5.0–
P5.3
I/O
4-bit I/O ports. N-channel open-drain output up
to 5 V. 1-, 4-, and 8-bit read/write and test are
possible. Ports 4 and 5 can be paired to
support 8-bit data transfer. 4-bit pull-up
resistors are software assignable.
36–43
Input
E
P6.0–
P6.3
P7.0–
P7.3
I/O
4-bit I/O ports. Port 6 pins are individually
software configurable as input or output. 1-bit
and 4-bit read/write and test are possible. 4-bit
pull-up resistors are software assignable. Ports
6 and 7 can be paired to enable 8-bit data
transfer.
44–51
KS0–KS3
KS4–KS7
Input
D*
P8.0–
P8.7
O
Output port for 1-bit data (for use as CMOS
driver only)
59–52
SEG24–
SEG31
Output
H-16
SEG0–
SEG23
O
LCD segment signal output
3–1,
80–60
Output
H-15
SEG24–
SEG31
O
LCD segment signal output
59–52
Output
H-16
COM0–
COM3
VLC0–VLC2
O
LCD common signal output
4–7
Output
H-15
–
LCD power supply. Voltage dividing resistors
are assignable by mask option
9–11
–
–
BIAS
–
LCD power control
8
–
–
LCD clock output for display expansion
32
Input
D
LCDCK
I/O
Share
Pin
SCK
SO
SI
–
–
P8.0–P8.7
–
SCLK
SDAT
–
P3.0
1-5
PRODUCT OVERVIEW
S3C7238/P7238/C7235/P7235
Table 1-1. S3C7238/C7235 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
LCDSY
I/O
LCD synchronization clock output for LCD
display expansion
33
P3.1
Input
D
TCL0
I/O
External clock input for timer/counter 0
27
P1.3
Input
A-1
TCLO0
I/O
Timer/counter 0 clock output
28
P2.0
Input
D
SI
I
Serial interface data input
23
P0.3
Input
A-1
SO
I/O
Serial interface data output
22
P0.2
Input
D*
SCK
I/O
Serial I/O interface clock signal
21
P0.1
Input
D*
INT0
INT1
I
External interrupts. The triggering edge for
INT0 and INT1 is selectable. Only INT0 is
synchronized with the system clock.
24
25
P1.0
P1.1
Input
A-1
INT2
I
Quasi-interrupt with detection of rising edge
signals.
26
P1.2
Input
A-1
INT4
I
External interrupt input with detection of rising
or falling edge
20
P0.0
Input
A-1
44–51
P6.0–P7.3
Input
D*
KS0–KS7
I/O
Quasi-interrupt inputs with falling edge
detection.
CLO
I/O
CPU clock output
30
P2.2
Input
D
BUZ
I/O
2, 4, 8 or 16 kHz frequency output for buzzer
sound with 4.19 MHz main system clock or
32.768 kHz subsystem clock.
31
P2.3
Input
D
XIN,
XOUT
–
Crystal, ceramic or RC oscillator pins for main
system clock. (For external clock input, use
XIN and input XIN‘s reverse phase to XOUT)
15,14
–
–
–
XTIN,
XTOUT
–
Crystal oscillator pins for subsystem clock.
(For external clock input, use XTIN and input
XTIN's reverse phase to XTOUT)
17,18
–
–
–
VDD
–
Main power supply
12
–
–
–
VSS
–
Ground
13
–
–
–
RESET
–
Reset signal
19
–
Input
B
TEST
–
Test signal input (must be connected to VSS)
16
–
–
–
NOTES:
1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
2. D * Type has a schmitt trigger circuit at input.
1-6
S3C7238/P7238/C7235/P7235
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
P-CHANNEL
P-CHANNEL
DATA
IN
OUT
N-CHNNEL
N-CHANNEL
OUTPUT
DISABLE
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type C
VDD
VDD
PULL-UP
RESISTOR
PULL-UP
RESISTOR
RESISTOR
ENABLE
P-CHANNEL
RESISTOR
ENABLE
DATA
IN
OUTPUT
DISABLE
P-CHANNEL
CIRCUIT
TYPE C
I/O
SCHMITT TRIGGER
CIRCUIT TYPE A
Figure 1-4. Pin Circuit Type A-1 (P1, P0.0, P0.3)
Figure 1-6. Pin Circuit Type D
(P0.1, P0.2, P2, P3, P6, P7)
1-7
PRODUCT OVERVIEW
S3C7238/P7238/C7235/P7235
VDD
PNE
VDD
PULL-UP
RESISTOR
RESISTOR
ENABLE
DATA
VDD
VLC0
P-CH
I/O
OUTPUT
ENABLE
VLC1
N-CH
LCD SEGMENT/
& PORT 8 DATA
OUT
CIRCUIT TYPE A
Figure 1-7. Pin Circuit Type E (P4, P5)
VLC2
VLC0
Figure 1-9. Pin Circuit Type H-16 (P8)
VLC1
LCD SEGMENT/
COMMON DATA
VDD
OUT
VLC2
IN
SCHMITT TRIGGER
Figure 1-8. Pin Circuit Type H-15 (SEG/COM)
1-8
Figure 1-10. Pin Circuit Type B (RESET
RESET)
S3C7238/P7238/C7235/P7235
14
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7238/C7235 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
Table 14-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Supply Voltage
VDD
–
Input Voltage
VI1
Output Voltage
VO
–
Output Current High
I OH
One I/O pin active
– 15
All I/O ports active
– 35
One I/O pin active
+ 30 (Peak value)
Output Current Low
I OL
Rating
Units
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
All I/O ports
– 0.3 to VDD + 0.3
mA
+ 15 (note)
Total value for ports 0, 2, 3, and 5
+ 100 (Peak value)
+ 60 (note)
Total value for ports 4, 6, and 7
+ 100
+ 60 (note)
Operating Temperature
TA
–
– 40 to + 85
Storage Temperature
Tstg
–
– 65 to + 150
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ×
°C
Duty .
Table 14-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VIH1
All input pins except those
specified below for VIH2, VIH3
0.7 VDD
–
VDD
VIH2
Ports 0, 1, 6, 7 and RESET
0.8 VDD
–
VDD
VIH3
XIN, XOUT, XTIN and XTOUT
VDD – 0.1
–
VDD
Input low
VIL1
Ports 2, 3, 4 and 5
–
–
0.3 VDD
voltage
VIL2
Ports 0, 1, 6, 7 and RESET
–
–
0.2 VDD
VIL3
XIN, XOUT, XTIN and XTOUT
–
–
0.1
VOH1
VDD = 4.5 V to 5.5 V
Ports 0, 2, 3, 4, 5, 6, 7 and BIAS
IOH = – 1 mA
VDD – 1.0
–
–
VOH2
VDD = 4.5 V to 5.5 V
Port 8 ONLY
IOH = – 100 µA
VDD – 2.0
–
–
Input high
voltage
Output high
voltage
14-2
V
V
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Output low
voltage
Input high
leakage
current
Input low
leakage
current
Symbol
Min
Typ
Max
Units
VOL1
VDD = 4.5 V to 5.5 V, Ports 0, 2–7
IOL = 15 mA
Conditions
–
0.4
2
V
VOL2
VDD = 4.5 V to 5.5 V, Port 8 only
IOL = 100 µA
–
–
1
ILIH1
VIN = VDD
All input pins except those specified
below for ILIH2
–
–
3
ILIH2
VIN = VDD
XIN, XOUT, XTIN and XTOUT
–
–
20
ILIL1
VIN = 0 V
All input pins except XIN, XOUT,
XTIN and XTOUT
–
–
–3
ILIL2
VIN = 0 V
XIN, XOUT, XTIN and XTOUT
– 20
Output high
leakage
current
ILOH1
VOUT = VDD
All output pins
Output low
leakage
current
ILOL
VOUT = 0 V
All output pins
Pull-up
resistor
RL1
Ports 0–7
VIN = 0 V; VDD = 5 V
25
47
100
VDD = 3 V
50
95
200
VIN = 0 V; VDD = 5 V, RESET
100
220
400
VDD = 3 V
200
450
800
RL2
µA
–
–
3
µA
–3
KΩ
LCD voltage
dividing
resistor
RLCD
TA = 25 °C
50
93
140
COM output
RCOM
VDD = 5 V
–
3
6
VDD = 3 V
5
15
VDD = 5 V
3
6
VDD = 3 V
5
15
–
± 45
± 90
mV
–
ñ 45
ñ 90
mV
impedance
SEG output
RSEG
impedance
COM output
voltage
deviation
VDC
SEG output
voltage
deviation
VDS
VDD = 5 V (VLC0 – COMi)
Io = ± 15uA (I = 0–3)
VDD = 5 V (VLC0-SEGi)
Io = ± 15µA (I = 0–31)
14-3
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
Table 14-2. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
VLC0 Output
voltage
VLC0
TA = 25 øC
VLC1 Output
voltage
VLC1
TA = 25 øC
VLC2 Output
voltage
VLC2
TA = 25 øC
Supply
Current (1)
IDD1 (2)
IDD2 (2)
IDD3
IDD4
IDD5
IDD6 (3)
Main operating:
VDD = 5 V ± 10%
CPU = fx/4
SCMOD = 000B
crystal oscillator
C1 = C2 = 22pF
VDD = 3 V ± 10%
Main Idle mode;
VDD = 5 V ± 10%
CPU = fx/4
SCMOD = 000B
crystal oscillator
C1 = C2 = 22pF
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
6.0 MHz
4.19 MHz
6.0 MHz
4.19 MHz
Min
Typ
Max
Units
0.6 VDD
– 0.2
0.6 VDD
0.6 VDD +
0.2
V
0.4 VDD
– 0.2
0.2 VDD
– 0.2
–
0.4 VDD
3.5
2.5
0.4 VDD
+ 0.2
0.2 VDD
+ 0.2
8
5.5
1.6
1.2
1.0
0.9
4
3
2.5
2.0
–
0.5
0.4
15
1.0
0.8
30
–
6
15
–
0.5
3
–
6.0 MHz
4.19 MHz
Sub operating:
VDD = 3 V ± 10%
CPU = fxt/4
SCMOD = 1001B
32 kHz crystal oscillator
Sub Idle mode;
VDD = 3 V ± 10%
CPU = fxt/4, SCMOD = 1101B
32 kHz crystal oscillator
Stop mode;
VDD = 5 V ± 10%
CPU = fxt/4, SCMOD = 1101B
Stop mode;
VDD = 5 V ± 10%
CPU = fx/4, SCMOD = 0100B
0.2 VDD
mA
µA
NOTES:
1. D.C. electrical values for supply current (IDD1 to IDD6) do not include current drawn through internal pull-up resistors
and through LCD voltage dividing resistors.
2. Data includes the power consumption for sub-system clock oscillation.
3. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The
main-system clock oscillation stops by the STOP instruction.
14-4
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
C1
Parameter
Oscillation frequency (1)
XIN
Oscillation frequency (1)
XOUT
C1
RC
Oscillator
XIN
XIN
Typ
Max
Units
–
0.4
–
6.0
MHz
Stabilization occurs
when VDD is equal to
the minimum oscillator
voltage range.
–
–
4
ms
–
0.4
–
6.0
MHz
VDD = 4.5 V to 5.5 V
–
–
10
ms
VDD = 1.8 V to 4.5 V
–
–
30
C2
Stabilization time (2)
External
Clock
Min
C2
Stabilization time (2)
Crystal
Oscillator
Test Condition
XOUT
XOUT
R
XIN input frequency (1)
–
0.4
–
6.0
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
VDD = 5 V
R = 20 KΩ, VDD = 5 V
R = 38 KΩ, VDD = 3 V
0.4
–
2.0
1.0
2
MHz
Frequency (1)
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
14-5
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
Table 14-4. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Crystal
Oscillator
XT IN
XT OUT
C1
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
–
32
32.768
35
kHz
VDD = 4.5 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 4.5 V
–
–
10
XTIN input frequency (1)
–
32
–
100
kHz
XTIN input high and low
level width (tXTL, tXTH)
–
5
–
15
µs
C2
Stabilization time (2)
External
Clock
XT IN XT OUT
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 14-5. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O capacitance
14-6
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
Table 14-6. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
Symbol
tCY
time (1)
TCL0 input
f TI0
SCK high, low
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 4.5 V
0.95
–
64
With subsystem clock (fxt)
114
122
125
0
–
1.5
MHz
1
MHz
–
–
µs
–
–
ns
–
–
ns
–
–
ns
–
–
ns
–
300
ns
VDD = 2.7 V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
External SCK source
800
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
650
tKCY
tKH, tKL
tSIK
tKSI
SCK high
Output delay for
SCK to SO
Units
VDD = 1.8 V to 5.5 V
SCK high
SI hold time to
Max
0.48
width
SI setup time to
Typ
tTIH0, tTIL0 VDD = 2.7 V to 5.5 V
low width
SCK cycle time
Min
VDD = 1.8 V to 5.5V
frequency
TCL0 input high,
Conditions
tKSO
3200
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
3800
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
tKCY/2 – 50
Internal SCK source
tKCY/2 – 150
External SCK source
100
Internal SCK source
150
External SCK source
400
Internal SCK source
400
VDD = 2.7 V to 5.5 V
400
1600
–
External SCK source
Internal SCK source
VDD = 1.8 V to 5.5 V
250
1000
External SCK source
Internal SCK source
Interrupt input
tINTH,
tINTL
high, low width
RESET Input Low
tRSL
1000
INT0
(2)
INT1, INT2, INT4, KS0–KS7
10
Input
10
–
–
µs
–
–
µs
Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
14-7
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
CPU Clock
Main OSC. Frequency
1.5 MHz
1.0475 MHz
1.00 MHz
750 kHz
6 MHz
4.19 MHz
3 MHz
500 kHz
250 kHz
15.6 kHz
1
1.8
3
4
5
6
7
Supply Voltage (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 14-1. Standard Operating Voltage Range
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Data retention supply voltage
VDDDR
Normal operation
Data retention supply current
IDDDR
Release signal set time
Oscillator stabilization wait
time (1)
Conditions
Min
Typ
Max
Unit
1.8
–
6.5
V
VDDDR = 1.8 V
–
0.1
10
µA
tSREL
Normal operation
0
–
–
µs
tWAIT
Released by RESET
–
17
2 /fx
–
ms
Released by interrupt
–
(2)
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-8
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
TIMING WAVEFORMS
INTERNAL
RESET
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
RESET
EXECUTION OF
STOP INSTRUCTION
t WAIT
tSREL
Figure 14-2. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
V DD
VDDDR
EXECUTION OF
STOP INSTRUCTION
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
t SREL
tWAIT
Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request
14-9
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
0.8 VDD
0.2 VDD
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/f x
t XL
t XH
Xin
VDD – 0.1 V
0.1 V
Figure 14-5. Clock Timing Measurement at XIN
1/f xt
t XTL
t XTH
XTin
V DD – 0.1 V
0.1 V
Figure 14-6. Clock Timing Measurement at XTIN
14-10
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
1/f TI0
t TIL0
t TIH0
TCL0
0.8 V DD
0.2 V DD
Figure 14-7. TCL0 Timing
t RSL
RESET
0.2 V DD
Figure 14-8. Input Timing for RESET Signal
t INTL
INT0, 1, 2, 4
KS0 to KS7
t INTH
0.8 VDD
0.2 VDD
Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts
14-11
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
t KCY
t KL
t KH
SCK
0.8 V DD
0.2 V DD
t SIK
SI
t KSI
INPUT DATA
0.8 V DD
0.2 V DD
t KSO
SO
OUTPUT DATA
Figure 14-10. Serial Data Transfer Timing
14-12
S3C7238/P7238/C7235/P7235
15
MECHANICAL DATA
MECHANICAL DATA
The S3C7238/C7235 is available in a 80-QFP-1420 package.
23.90 ± 0.30
0-8
20.00 ± 0.20
+ 0.10
14.00 ± 0.20
0.10 MAX
80-QFP-1420C
0.80 ± 0.20
17.90 ± 0.30
0.15 - 0.05
#80
#1
0.80
0.35 + 0.10
0.05 MIN
0.15 MAX
(0.80)
2.65 ± 0.10
3.00 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 15-1. 80-QFP-1420C Package Dimensions
15-1
S3C7238/P7238/C7235/P7235
16
S3P7238/P7235 OTP
S3P7238/P7235 OTP
OVERVIEW
The S3P7238/P7235 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C7238/C7235 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by
a serial data format.
The S3P7238/P7235 is fully compatible with the S3C7238/C7235, both in function and in pin configuration.
Because of its simple programming requirements, the S3P7238/P7235 is ideal for use as an evaluation chip for
the S3C7238/C7235.
16-1
S3C7238/P7238/C7235/P7235
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
S3P7238/P7235 OTP
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
BIAS
VLC0
SDAT / VLC1
SCLK / VLC2
VDD / VDD
VSS / VSS
Xout
Xin
TEST / TEST
XTin
XTout
RESET / RESET
S3P7238
S3P7235
(TOP VIEW)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P1.1/INT1
P1.2/INT2
P1.3/TCL0
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
P3.0/LCDCK
P3.1/SCDSY
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
P5.0
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P0.0/INT4
P0.1/SCK
P0.2/SO
P0.3/SI
P1.0/INT0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NOTE: The bolds indicate an OTP pin names.
Figure 16-1. S3P7238/P7235 Pin Assignments (80-QFP)
16-2
SEG19
SEG20
SEG21
SEG22
SEG23
P8.0/SEG24
P8.1/SEG25
P8.2/SEG26
P8.3/SEG27
P8.4/SEG28
P8.5/SEG29
P8.6/SEG30
P8.7/SEG31
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
Table 16-1. Pin Descriptions Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
VLC1
SDAT
10
I/O
Serial data pin. Output port when reading and
input port when writing can be assigned as
Input/push-pull output port respectively.
VLC2
SCLK
11
I/O
Serial clock pin. Input only pin.
TEST
VPP (TEST)
16
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
RESET
RESET
19
I
Chip initialization
VDD / VSS
VDD / VSS
12/13
I
Logic power supply pin. VDD should be tied to +5
V during programming.
Table 16-2. Comparison of S3P7238/P7235 and S3C7238/C7235 Features
Characteristic
S3P7238/P7235
S3C7238/C7235
Program Memory
8 K/16 K-byte EPROM
8 K/16-Kbyte mask ROM
Operating Voltage (VDD)
1.8 V to 5.5 V
1.8 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5 V
Pin Configuration
80 QFP
80 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
–
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the Vpp (TEST) pin of the S3P7238/P7235, the EPROM programming mode is
entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins
listed in Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
Vpp
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
W
5V
5V
0
0000H
1
EPROM read
12.5V
0
0000H
0
EPROM program
12.5V
0
0000H
1
EPROM verify
12.5V
1
0E3FH
0
EPROM read protection
Mode
NOTE: "0" means low level; "1" means high level.
16-3
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
Table 16-4. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Supply Voltage
VDD
–
Input Voltage
VI1
Output Voltage
VO
–
Output Current High
I OH
One I/O pin active
– 15
All I/O ports active
– 35
One I/O pin active
+ 30 (Peak value)
Output Current Low
I OL
Rating
Units
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
All I/O ports
– 0.3 to VDD + 0.3
mA
+ 15 (note)
Total value for ports 0, 2, 3, and 5
+ 100 (Peak value)
+ 60 (note)
Total value for ports 4, 6, and 7
+ 100
+ 60 (note)
Operating Temperature
TA
–
– 40 to + 85
Storage Temperature
Tstg
–
– 65 to + 150
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ×
°C
Duty .
Table 16-5. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VIH1
All input pins except those
specified below for VIH2, VIH3
0.7 VDD
–
VDD
VIH2
Ports 0, 1, 6, 7 and RESET
0.8 VDD
–
VDD
VIH3
XIN, XOUT, XTIN and XTOUT
VDD – 0.1
–
VDD
Input low
VIL1
Ports 2, 3, 4 and 5
–
–
0.3 VDD
voltage
VIL2
Ports 0, 1, 6, 7 and RESET
–
–
0.2 VDD
VIL3
XIN, XOUT, XTIN and XTOUT
–
–
0.1
VOH1
VDD = 4.5 V to 5.5 V
Ports 0, 2, 3, 4, 5, 6, 7 and BIAS
IOH = – 1 mA
VDD – 1.0
–
–
VOH2
VDD = 4.5 V to 5.5 V
Port 8 ONLY
IOH = – 100 µA
VDD – 2.0
–
–
Input high
voltage
Output high
voltage
16-4
V
V
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
Table 16-5. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Output low
voltage
Input high
leakage
current
Input low
leakage
current
Output high
leakage
current
Output low
leakage
current
Pull-up
resistor
Symbol
Conditions
Min
Typ
Max
Units
VOL1
VDD = 4.5 V to 5.5 V, Ports 0, 2–7
IOL = 15 mA
–
0.4
2
V
VOL2
VDD = 4.5 V to 5.5 V, Port 8 only
IOL = 100 µA
–
–
1
ILIH1
VIN = VDD
All input pins except those specified
below for ILIH2
–
–
3
ILIH2
VIN = VDD
XIN, XOUT, XTIN and XTOUT
–
–
20
ILIL1
VIN = 0 V
All input pins except XIN, XOUT,
XTIN and XTOUT
–
–
–3
ILIL2
VIN = 0 V
XIN, XOUT, XTIN and XTOUT
VOUT = VDD
All output pins
ILOL
VOUT = 0 V
All output pins
RL1
Ports 0–7
VIN = 0 V; VDD = 5 V
25
47
100
VDD = 3 V
50
95
200
VIN = 0 V; VDD = 5 V, RESET
100
220
400
VDD = 3 V
200
450
800
RLCD
TA = 25 °C
50
93
140
RCOM
VDD = 5 V
–
3
6
VDD = 3 V
5
15
VDD = 5 V
3
6
VDD = 3 V
5
15
–
± 45
± 90
mV
–
ñ 45
ñ 90
mV
impedance
SEG output
RSEG
impedance
COM output
voltage
deviation
SEG output
voltage
deviation
– 20
ILOH1
RL2
LCD voltage
dividing
resistor
COM output
µA
VDC
VDD = 5 V (VLC0 – COMi)
–
–
3
µA
–3
KΩ
Io = ± 15uA (I = 0–3)
VDS
VDD = 5 V (VLC0-SEGi)
Io = ± 15µA (I = 0–31)
16-5
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
Table 16-5. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
VLC0 Output
voltage
VLC0
TA = 25 øC
VLC1 Output
voltage
VLC1
TA = 25 øC
VLC2 Output
voltage
VLC2
TA = 25 øC
Supply
Current (1)
IDD1 (2)
IDD2 (2)
IDD3
IDD4
IDD5
IDD6 (3)
Conditions
Main operating:
VDD = 5 V ± 10%
CPU = fx/4
SCMOD = 000B
crystal oscillator
C1 = C2 = 22pF
VDD = 3 V ± 10%
Main Idle mode;
VDD = 5 V ± 10%
CPU = fx/4
SCMOD = 000B
crystal oscillator
C1 = C2 = 22pF
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
6.0 MHz
4.19 MHz
6.0 MHz
4.19 MHz
Min
Typ
Max
Units
0.6 VDD
– 0.2
0.4 VDD
– 0.2
0.2 VDD
– 0.2
–
0.6 VDD
V
3.5
2.5
0.6 VDD +
0.2
0.4 VDD
+ 0.2
0.2 VDD
+ 0.2
8
5.5
1.6
1.2
1.0
0.9
4
3
2.5
2.0
–
0.5
0.4
15
1.0
0.8
30
–
6
15
–
0.5
3
–
6.0 MHz
4.19 MHz
Sub operating:
VDD = 3 V ± 10%
CPU = fxt/4
SCMOD = 1001B
32 kHz crystal oscillator
Sub Idle mode;
VDD = 3 V ± 10%
CPU = fxt/4, SCMOD = 1101B
32 kHz crystal oscillator
Stop mode;
VDD = 5 V ± 10%
CPU = fxt/4, SCMOD = 1101B
Stop mode;
VDD = 5 V ± 10%
CPU = fx/4, SCMOD = 0100B
0.4 VDD
0.2 VDD
mA
µA
NOTES:
1. D.C. electrical values for supply current (IDD1 to IDD6) do not include current drawn through internal pull-up resistors and
2.
3.
through LCD voltage dividing resistors.
Data includes the power consumption for sub-system clock oscillation.
When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The
main-system clock oscillation stops by the STOP instruction.
16-6
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
Table 16-6. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
C1
Parameter
Oscillation frequency (1)
XIN
Oscillation frequency (1)
XOUT
C1
RC
Oscillator
XIN
XIN
Typ
Max
Units
–
0.4
–
6.0
MHz
Stabilization occurs
when VDD is equal to
the minimum oscillator
voltage range.
–
–
4
ms
–
0.4
–
6.0
MHz
VDD = 4.5 V to 5.5 V
–
–
10
ms
VDD = 1.8 V to 4.5 V
–
–
30
C2
Stabilization time (2)
External
Clock
Min
C2
Stabilization time (2)
Crystal
Oscillator
Test Condition
XOUT
XOUT
R
XIN input frequency (1)
–
0.4
–
6.0
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
VDD = 5 V
R = 20 KΩ, VDD = 5 V
R = 38 KΩ, VDD = 3 V
0.4
–
2.0
1.0
2
MHz
Frequency (1)
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
16-7
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
Table 16-7. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Crystal
Oscillator
XT IN
XT OUT
C1
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
–
32
32.768
35
kHz
VDD = 4.5 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 4.5 V
–
–
10
XTIN input frequency (1)
–
32
–
100
kHz
XTIN input high and low
level width (tXTL, tXTH)
–
5
–
15
µs
C2
Stabilization time (2)
External
Clock
XT IN XT OUT
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 16-8. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O capacitance
16-8
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
Table 16-9. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
Symbol
tCY
time (1)
TCL0 input
f TI0
SCK high, low
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 4.5 V
0.95
–
64
With subsystem clock (fxt)
114
122
125
0
–
1.5
MHz
1
MHz
–
–
µs
–
–
ns
–
–
ns
–
–
ns
–
–
ns
–
300
ns
VDD = 2.7 V to 5.5 V
tTIH0, tTIL0 VDD = 2.7 V to 5.5 V
0.48
VDD = 1.8 V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
External SCK source
800
Internal SCK source
650
VDD = 1.8 V to 5.5 V
External SCK source
3200
Internal SCK source
3800
VDD = 1.8 V to 5.5 V
External SCK source
400
low width
SCK cycle time
Min
VDD = 1.8 V to 5.5V
frequency
TCL0 input high,
Conditions
tKCY
tKH, tKL
width
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
SI setup time to
tSIK
SCK high
SI hold time to
tKSI
SCK high
Output delay for
SCK to SO
tKSO
tKCY/2 – 50
1600
Internal SCK source
tKCY/2 – 150
External SCK source
100
Internal SCK source
150
External SCK source
400
Internal SCK source
400
VDD = 2.7 V to 5.5 V
–
External SCK source
Internal SCK source
250
VDD = 1.8 V to 5.5 V
1000
External SCK source
Internal SCK source
Interrupt input
tINTH,
tINTL
high, low width
RESET Input Low
tRSL
1000
INT0
(2)
INT1, INT2, INT4, KS0–KS7
10
Input
10
–
–
µs
–
–
µs
Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
16-9
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
CPU Clock
Main OSC. Frequency
1.5 MHz
1.0475 MHz
1.00 MHz
750 kHz
6 MHz
4.19 MHz
3 MHz
500 kHz
250 kHz
15.6 kHz
1
1.8
3
4
5
6
7
Supply Voltage (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 16-2. Standard Operating Voltage Range
Table 16-10. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Data retention supply voltage
VDDDR
Normal operation
Data retention supply current
IDDDR
Release signal set time
Oscillator stabilization wait
time (1)
Conditions
Min
Typ
Max
Unit
1.8
–
6.5
V
VDDDR = 1.8 V
–
0.1
10
µA
tSREL
Normal operation
0
–
–
µs
tWAIT
Released by RESET
–
17
2 /fx
–
ms
Released by interrupt
–
(2)
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
16-10
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
TIMING WAVEFORMS
INTERNAL
RESET
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
RESET
EXECUTION OF
STOP INSTRUCTION
t WAIT
tSREL
Figure 16-3. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
V DD
VDDDR
EXECUTION OF
STOP INSTRUCTION
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
t SREL
tWAIT
Figure 16-4. Stop Mode Release Timing When Initiated By Interrupt Request
16-11
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
0.8 VDD
0.2 VDD
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
Figure 16-5. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/f x
t XL
t XH
Xin
VDD – 0.1 V
0.1 V
Figure 16-6. Clock Timing Measurement at XIN
1/f xt
t XTL
t XTH
XTin
V DD – 0.1 V
0.1 V
Figure 16-7. Clock Timing Measurement at XTIN
16-12
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
1/f TI0
t TIL0
t TIH0
TCL0
0.8 V DD
0.2 V DD
Figure 16-8. TCL0 Timing
t RSL
RESET
0.2 V DD
Figure 16-9. Input Timing for RESET Signal
t INTL
INT0, 1, 2, 4
KS0 to KS7
t INTH
0.8 VDD
0.2 VDD
Figure 16-10. Input Timing for External Interrupts and Quasi-Interrupts
16-13
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
t KCY
t KL
t KH
SCK
0.8 V DD
0.2 V DD
t SIK
SI
t KSI
INPUT DATA
0.8 V DD
0.2 V DD
t KSO
SO
OUTPUT DATA
Figure 16-11. Serial Data Transfer Timing
16-14
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
START
Address= First Location
VDD =5V, V PP=12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
Verify Byte
Verify 1 Byte
Last Address
FAIL
NO
Increment Address
VDD = VPP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-12. OTP Programming Algorithm
16-15