TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 D D D D D D D (TOP VIEW) Contains Two 64-Bit Static Shift Registers Offers Extendable Data I/O for Expanding the Number of Sensors Contains Analog Buffer With Sample-andHold for Analog Output Over Full Clock Period Single-Supply Operation Operates With 500-kHz Shift Clock 14-Pin Encapsulated Clear Plastic Package Advanced LinCMOS Technology VDD SI1 CLK AO1 GND SO2 VDD 1 14 2 13 3 12 4 11 5 10 6 9 7 8 NC SO1 GND NC SI2 NC AO2 NC – No internal connection description The TSL215 integrated opto sensor consists of two sections of 64 charge-mode pixels arranged in a 128 × 1 linear array. Each pixel measures 120 µm × 70 µm with 125-µm center-to-center spacing. Operation is simplified by internal logic requiring only clock and start-integration-pulse signals. The TSL215 is intended for use in a wide variety of applications including linear and rotary encoding, bar-code reading, edge detection and positioning, and contact imaging. The TSL215 is supplied in a 14-pin dual-in-line clear plastic package. Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Advanced LinCMOS is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 functional block diagram of each section VDD 1,7 1 2 3 64 Pixels Sense Node Dark Pixel Reference Generator Pixel Selector Switch S1 S2 S3 Pixel Buffer Differential Amplifier Pixel Buffer Sample and Hold Output Buffer 4,8 RL (external load) S64 Nonoverlapping Clock Generator Reset 6,13 Q1 CLK 3 AO Q2 Q3 64-Bit Shift Register 2,10 SI Q64 SO Clock Generator Terminal Functions PIN NAME DESCRIPTION NO. AO1 4 Analog output of section 1 AO2 8 Analog output of section 2 CLK 3 Clock. The clock controls charge transfer, pixel output, and reset. GND 5, 12 Ground (substrate). All voltages are referenced to the substrate. NC 9, 11, 14 No internal connection SI1 2 Serial input (section 1). The serial input defines the end of the integration period and initiates the pixel output sequence. SI2 10 Serial input (section 2). The serial input defines the end of the integration period and initiates the pixel output sequence. SO1 13 Serial output (section 1). The serial output provides a signal to drive the SI2 input. SO2 6 Serial output (section 2). The serial output provides a signal to drive the SI1 input of another TSL215 sensor for cascading. VDD 1, 7 2 Supply voltage. These supply power to the analog and digital circuits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 detailed description sensor elements The line of sensor elements, called pixels, consists of 128 discrete photosensing areas. Light energy striking a pixel generates electron-hole pairs in the region under the pixel. The field generated by the bias on the pixel causes the electrons to collect in the element while the holes are swept into the substrate. The amount of charge accumulated in each element is directly proportional to the amount of incident light and the integration time. device operation Operation of the 128 × 1 array sensor is a function of two time periods: an integration period during which a charge is accumulated in the pixels and an output period during which signals are transferred to the output. The integration period is defined by the interval between the externally supplied (SI) pulses and includes the output period (see Figure 1). The required length of the integration period depends on the amount of incident light and the desired output signal level. A single TSL 215 can be connected in either a serial or parallel configuration. serial configuration The serial connection shown in Figure 1 is accomplished by connecting the analog outputs (AO1 and AO2) together and connecting the SO1 output to the SI2 input. As shown in Figure 1, the external SI signal is supplied to only the SI1 input. This causes the first section of 64 pixels to be clocked out in synchronization with CLK. In conjunction with the 64th pixel, the SI pulse is shifted out on the SO1 output. This SO1 pulse is then fed to the SI2 input. The 65th clock cycle terminates the output of the last pixel from the first section and clears the shift register of that section in preparation for the next SI pulse to that section. The rising edge of the 65th cycle also puts AO1 into the high-impedance state. The appearance of the SI2 signal and the 65th clock cycle initiates the output cycle of the second section. The second section of 64 pixels appears at AO2, and the SO2 signal is shifted out on the 128th clock cycle. The rising edge of the 129th clock cycle resets the second section and puts AO2 into the high-impedance state. Both AO1 and AO2 remain in this high-impedance state until a new external SI pulse appears on SI1. When the TSL215 is connected as shown in Figure 1, the analog output appears as a continuous string representing the 128 pixels. parallel configuration Parallel operation of the TSL215 (see Figure 2) is accomplished by connecting the serial input lines (SI1 and SI2) together and connecting each AO line (AO1 and AO2) to its own load resistor (RL ). This supplies the external serial input pulse to both SI1 and SI2 simultaneously. Each AO line must be independent of the other line since both sections are active simultaneously. Pixels 1 through 64 appear on AO1, while pixels 65 through 128 appear on AO2. These two sections of 64 pixels begin clocking out concurrently, each on its respective output. On the 64th clock cycle, both SO1 and SO2 are shifted out of each respective register. The rising edge of the 65th cycle terminates the output of the 64th pixel from each section and also resets both section’s shift registers. Both AO lines then go to the high-impedance state until the next external SI signal appears. sense node On completion of the integration period, the charge contained in each pixel is transferred in turn to the sense node under the control of the clock (CLK) and serial-input (SI) signals. The signal voltage generated at this node is directly proportional to the amount of charge and inversely proportional to the capacitance of the sense node. reset An internal reset signal is generated by the nonoverlapping clock generator (NOCG) and occurs every clock cycle. Reset establishes a known voltage on the sense node in preparation for the next charge transfer. This voltage is used as a reference level for the differential signal amplifier. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 detailed description (continued) shift register Both 64-bit shift registers control the transfer of charge from the pixels to the output stages and provide timing signals for the NOCG. The serial input (SI) signal provides the input to the shift register and is shifted under direct control of CLK out to the serial output (SO) on the 64th clock cycle. This SO pulse can then be used as the SI pulse for the next section or next device. The output period for each section is initiated by the presence of the SI input pulse coincident with a rising edge of CLK (see Figures 1, 2, and 3). The analog output voltage corresponds to the level of the first pixel after settling time (ts) and remains constant for a minimum time (tv). A voltage corresponding to each succeeding pixel is available at each rising edge of CLK. The output period of a section ends when the active section sees the rising edge of the 65th clock cycle, at which time the output assumes the high-impedance state. Once the output period has been initiated by an SI pulse, CLK must be allowed to complete [ (n × 64)+1 ] (where n is the number of sections running in series) positive-going transitions in order to reset the internal logic to a known state. To achieve minimum integration time, the SI pulse may be present on the [ (n × 64)+2 ] rising clock to immediately restart the output phase. sample-and-hold The sample-and-hold signal generated by the NOCG is used to hold the analog output voltage of each pixel constant until the next pixel is clocked out. The signal is sampled while CLK is high and held constant while CLK is low. nonoverlapping clock generators The NOCG circuitry provides internal control signals for the sensor, including reset and pixel-charge sensing. The signals are synchronous and are controlled by the outputs of the shift register. initialization Initialization of the sensor elements may be necessary on power up or during operation after any period of CLK or SI inactivity exceeding the integration time. The initialization phase consists of 12 to 15 consecutively performed output cycles and clears the pixels of any charge that may have accumulated during the inactive period. multiple-unit operation Multiple-sensor devices can be connected together in a serial or parallel configuration. The serial connection is accomplished by connecting analog outputs (AO) together and connecting the SO output of each sensor device to the SI input of the next device. The SI signal is applied to only the first device. Each succeeding device receives its SI input from the SO output of the preceding device. For m-cascaded devices, the SI pulse is applied to the first device after every m •128th positive-going CLK transitions. A common clock signal is applied to all the devices simultaneously. Parallel operation of multiple devices is accomplished by supplying CLK and SI signals to all the devices simultaneously. The output of each device is then separately used for processing. output enable The internally generated output-enable signal enables the output stage of each section during the output period (64 clock cycles). During the remainder of the integration period, the output stage is in the high-impedance state that allows output interconnections of multiple devices without interference. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 absolute maximum ratings, TA = 25°C (unless otherwise noted) (see Note 1)† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Digital output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VDD + 0.5 V Digital output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 mA Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20 mA to 20 mA Operating case temperature range, TC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 25°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to the network GND. 2. Case temperature is the surface temperature of the plastic measured directly over the integrated circuit. recommended operating conditions MIN Supply voltage, VDD Input voltage, VI NOM MAX UNIT 4.5 5.5 V 0 VDD VDD V VDD × 0.7 0 High-level input voltage, VIH Low-level input voltage, VIL Analog output external resistive load, RL VDD × 0.3 750 Clock input frequency, fclock 10 Pulse duration, CLK low, tw(CLKL) nm 500 kHz µs 1 Sensor integration time, tint (see Figures 1 and 2) V Ω 330 Wavelength of light source, λ V 5 ms Setup time, SI before CLK↑, tsu(SI) 50 ns Hold time, SI after CLK↑, th(SI) 50 ns Total number of TSL215 outputs connected together 8 Operating free-air temperature, TA 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 70 °C 5 TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 electrical characteristics , VDD = 5 V, TA = 25°C, fclock = 180 kHz, λp = 565 nm, RL = 330 Ω, CL = 330 pF, tint = 5 ms, Ee = 20 µW/cm2 (unless otherwise noted) (see Note 3) PARAMETER TEST CONDITIONS Low-level output voltage MIN 4.4 Ee = 60 µW/cm2 Analog output voltage, saturation level Analog output voltage (white, average over 64 pixels) Analog output voltage (dark, each pixel) Output voltage (white) change with change in VDD Ee = 0 VDD = 5 V ± 5%, Dispersion of analog output voltage See Note 5 Linearity of analog output voltage tint = 2 ms to 5 ms, See Note 7 See Note 6 See Note 4 High-level input current IDD (average), VI = VDD Low-level input current VI = 0 Pixel recovery time Supply current MAX 0.1 IO = 0 High-level output voltage TYP† UNIT V V 3 3.4 1.75 2.2 V V 0.25 0.4 V ± 2% See Note 4 ±10% 0.85 1.15 25 40 ms 4 12 mA 0.5 µA 0.5 µA Input capacitance 5 pF † All typical values are at VDD = 5 V and TA = 25°C. NOTES: 3. The input irradiance (Ee) is supplied by an LED array with λp = 565 nm. 4. Device tested in parallel mode with only one section active 5. Dispersion of analog output voltage is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test. 6. Linearity of analog output voltage is calculated by averaging over 64 pixels and measuring the maximum deviation of the voltage at 2 ms and 3.5 ms from a line drawn between the voltage at 2.5 ms and 5 ms. 7. Pixel recovery time is the time required for a pixel to go from the analog-output-voltage (white, average over 64 pixels) level to analog-output-voltage (dark, each pixel) level or vice versa after a step change in light input. operating characteristics, RL = 330 Ω, CL = 330 pF, VDD = 5 V, TA = 25°C, tint = 5 ms, Ee = 20 µW/cm2, fclock = 500 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr(SO) tf(SO) Rise time, SO 25 ns Fall time, SO 25 ns tpd(SO) ts Propagation delay time, SO See Figure 3 and Note 8 Settling time tv Valid time NOTE 8: Clock duty cycle is assumed to be 50%. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 70 ns 1 µs 1/2 fclock µs TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 1 2 3 External Si CLK 4 5 6 7 VDD SI1 CLK NC SO1 GND AO1 GND SO2 VDD NC SI2 NC AO2 14 13 12 11 10 9 8 AO (pixels 1–128) RL † 128 Total Cycles CLK 64 Cycles 64 Cycles tint External Si SO1, SI2 Pixels 1–128 AO Common AO1 (1– 64) AO2 (65 –128) † CLK continues or goes low after 129 cycles. Figure 1. Serial Configuration External Si CLK 1 2 3 4 5 6 7 VDD SI1 CLK NC SO1 GND AO1 GND SO2 VDD NC SI2 NC AO2 14 13 12 11 10 9 8 AO1 (pixels 65 –128) RL AO2 (pixels 1– 64) RL † CLK 64 Cycles tint External Si SO1, SI2 AO1 Pixels 1– 64 AO2 Pixels 65 –128 † CLK continues or goes low after 65 cycles. Figure 2. Parallel Configuration POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 PARAMETER MEASUREMENT INFORMATION VDD 0.1 µF† 2 SI1 1 7 VDD VDD 4 SI1 AO1 AO1 RL = 330 Ω 3 CLK CLK 10 SI2 SI2 13 SO1 8 SO1 AO2 AO2 6 SO2 CL = 330 pF RL = 330 Ω SO2 GND CL = 330 pF GND 5 12 † Supply bypass capacitor with short leads should be placed as close to the device as possible. TEST CIRCUIT tw(CLKL) 1 2 64 65 5V 2.5 V CLK 0V tsu(SI) 5V 50% SI 0V th(SI) SO 50% ts ts AO tpd(SO) tpd(SO) 90% Pixel 1 90 % 10 % 50% 10% 90% tr(SO) 90% Pixel 64 tv OPERATIONAL WAVEFORMS Figure 3. Test Circuit and Operational Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tf(SO) TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 TYPICAL CHARACTERISTICS INTEGRATION TIME vs IRRADIANCE FOR CONSTANT AVERAGE ANALOG OUTPUT VOLTAGE NORMALIZED RESPONSIVITY vs WAVELENGTH OF INCIDENT LIGHT 10 1 VDD = 5 V λp = 565 nm Analog Output Voltage (white, average over 64 pixels) = 2 V TA = 25°C 9 t int – Integration Time – ms Normalized Responsivity 0.4 0.1 0.04 VDD = 5 V TA = 25°C tint = 3 ms 0.01 400 8 7 6 5 4 3 2 500 600 700 800 900 1000 1100 λ – Wavelength of Incident Light – nm 0 5 10 15 20 25 30 35 40 Ee – Irradiance – µW/cm2 50 Figure 5 Figure 4 NORMALIZED OUTPUT VOLTAGE vs INTEGRATION TIME ANALOG OUTPUT VOLTAGE (DARK) vs INTEGRATION TIME 300 1 VDD = 5 V TA = 25°C 0.9 250 Output Voltage Normalized to 2.2 V Analog Output Voltage (dark) – mV 45 200 150 100 VDD = 5 V Ee = 0 TA = 25°C 50 2 0.7 Ee = 10 µW/cm2 0.6 0.5 0.4 0.3 Ee = 2 µW/cm2 0.2 0.1 0 1 Ee = 20 µW/cm2 0.8 4 7 10 20 40 70 100 0 2 3 tint – Integration Time – ms Figure 6 4 5 6 7 8 tint – Integration Time – ms 9 10 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TSL215 128 × 1 INTEGRATED OPTO SENSOR SOES005A – JUNE 1992 – REVISED AUGUST 1993 MECHANICAL DATA This assembly consists of a sensor chip mounted on a printed-circuit board in a clear molded plastic package. The distance between the top surface of the package and the surface of the sensor is nominally 1 mm (0.040 inch). Designation per JEDEC Std. 30: PDIP-T14 10,67 (0.420) 9,69 (0.380) 1,91 (0.075) MAX Both Rows CL Bottom View 1 0.254 (0.01) NOM First Pixel Location 19,30 (0.760) 18,29 (0.720) 14 1 13 2 12 3 11 4 10 5 9 6 8 7 2,16 (0.085) MAX 4 Places 2,54 (0.100) T.P. 12 Places (see Note A) Sensor Center Line 3,94 (0.155) 3,68 (0.145) 7,87 (0.310) 7,37 (0.290) 3,18 (0.135) 2,79 (0.110) CL CL Seating Plane 4,6 (0.180) MIN 0,508 (0.020) 0,406 (0.016) Diameter All Pins ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE A: The true-position spacing is 2,54 mm (0.100 inch) between lead centerlines. Each pin centerline is located within 0,25 mm (0.010 inch) of its true longitudinal positions. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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