SILABS Si8230BB-B-IS

Si823x
0 . 5 AND 4 . 0 A MP I S O D R I V E R S (2.5 AND 5 K V RMS )
Features
Pin Assignments





Two completely isolated drivers  60 ns maximum propagation
in one package
delay
Up to 5 kVRMS input-to-output
 Independent HS and LS inputs or
PWM input versions
isolation
Up to 1500 VDC peak driver-to Transient immunity >30 kV/µs
driver differential voltage
 Overlap protection and
HS/LS and dual driver versions
programmable dead time
Up to 8 MHz switching frequency  Operating temperature range
0.5 A peak output (Si8230/1/2)
–40 to +125 °C
4.0 A peak output (Si8233/4/5/6)  UL/VDE/CSA approval
 RoHS-compliant
SOIC-16 (Wide)
VIA
1
16
VDDA
VIB
2
15
VOA
VDDI
3
14
GNDA
GNDI
4
13
NC
DISABLE
5
12
NC
DT
6
11
VDDB
NC
7
10
VOB
VDDI
8
9
Power delivery systems
 Motor control systems
 Isolated dc-dc power supplies
GNDB
SOIC-16 (Narrow)
Applications

Si8230
Si8233
VIA
1
16
VDDA
VIB
2
15
VOA
VDDI
3
14
GNDA
GNDI
4
Si8230 13
NC
DISABLE
5
Si8233 12
NC
DT
6
11
VDDB
NC
7
10
VOB
VDDI
8
9

Lighting control systems
 Plasma displays
 Solar and industrial inverters
Description
The Si823x isolated driver family combines two independent, isolated
drivers into a single package. The Si8230/1/3/4 are high-side/low-side
drivers, and the Si8232/5/6 are dual drivers. Versions with peak output
currents of 0.5 A (Si8230/1/2) and 4.0 A (Si8233/4/5/6) are available. All
drivers operate with a maximum supply voltage of 24 V.
The Si823x drivers utilize Silicon Labs' proprietary silicon isolation
technology, which provides up to 5 kVRMS withstand voltage per UL1577,
and fast 60 ns propagation times. Driver outputs can be grounded to the
same or separate grounds or connected to a positive or negative voltage.
The TTL level compatible inputs with >400 mV hysteresis are available in
individual control input (Si8230/2/3/5/6) or PWM input (Si8231/4)
configurations. High integration, low propagation delay, small installed
size, flexibility, and cost-effectiveness make the Si823x family ideal for a
wide range of isolated MOSFET/IGBT gate drive applications.
GNDB
LGA-14 (5 x 5 mm)
GNDI
1
14
VDDA
VIA
2
13
VOA
VIB
3
12
GNDA
VDDI
4
11
NC
DISABLE
5
10
VDDB
DT
6
7
VOB
VDDI
7
8
GNDB
Si8230
Si8233
Patents Pending
Safety Approval

UL 1577 recognized
Up

to 5000 Vrms for 1 minute
CSA component notice 5A
approval

VDE certification conformity
IEC
60747-5-2 (VDE 0884 Part 2)
60950 (reinforced insulation)
(Pending)
EN
IEC
60950, 61010, 60601
(reinforced insulation)
Rev. 0.3 4/10
Copyright © 2010 by Silicon Laboratories
Si823x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si823x
Block Diagrams
VOA
VDDA
DT
Overlap Protection,
Programmable Dead
Time, Control Gating
UVLO
VOB
UVLO
DISABLE
GNDB
GNDI
VOB
GNDB
GNDI
Si8230/3
Control Gating
VDDB
Isolation
Isolation
VIB
VOA
GNDA
VDDI
VDDB
2
VOA
Programmable Dead
Time, Control Gating
VDDI
UVLO
DISABLE
VDDA
GNDA
GNDA
VDDI
VIA
Isolation
DT
PWM
VDDB
Isolation
Isolation
VDDA
Isolation
VIA
DISABLE
VIB
GNDB
GNDI
Si8231/4
Rev. 0.3
VOB
Si8232/5/6
Si823x
TABLE O F C ONTENTS
Section
Page
1. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.2. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Typical Operating Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Typical Operating Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1. Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.5. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.7. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . . 26
6. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1. RF, Magnetic, and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . 28
7. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1. High-Side / Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2. Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3. Dual Driver with Thermally Enhanced Package (Si8236) . . . . . . . . . . . . . . . . . . . . .30
8. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
11. Land Pattern: Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. Package Outline: Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13. Land Pattern: Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
14. Package Outline: 14 LD LGA (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
15. Land Pattern: 14 LD LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
16. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .48
17. Land Pattern: 14 LD LGA with Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Rev. 0.3
3
Si823x
1. Top-Level Block Diagrams
VDDI
VDDA
ISOLATION
VIA
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDB
ISOLATION
VDDI
UVLO
VOB
UVLO
DISABLE
GNDB
VIB
GNDI
Si8230/3
Figure 1. Si8230/3 Two-Input High-Side / Low-Side Isolated Drivers
VDDI
VDDA
ISOLATION
PWM
LPWM
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDB
ISOLATION
VDDI
UVLO
VOB
UVLO
DISABLE
GNDB
LPWM
GNDI
Si8231/4
Figure 2. Si8231/4 Single-Input High-Side / Low-Side Isolated Drivers
4
Rev. 0.3
Si823x
VDDI
ISOLATION
VDDA
VIA
VOA
UVLO
GNDA
VDDI
VDDI
UVLO
VDDI
ISOLATION
VDDB
DISABLE
VOB
UVLO
GNDB
VIB
GNDI
Si8232/5/6
Figure 3. Si8232/5/6 Dual Isolated Drivers
Rev. 0.3
5
Si823x
2. Electrical Specifications
Table 1. Electrical Characteristics1
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
4.5
—
5.5
V
6.5
—
24
V
Si8230/32/33/35/36
—
2
3
mA
Si8231/34
—
2
3
mA
IDDA(Q),
IDDB(Q)
Current per channel
—
—
3.0
mA
Input Supply Active Current
IDDI
PWM freq = 500 kHz
—
2.5
—
mA
Output Supply Active Current
IDDO
PWM freq = 500 kHz
—
3.6
—
mA
DC Specifications
Input-side Power Supply
Voltage
Driver Supply Voltage
Input Supply Quiescent
Current
Output Supply Quiescent
Current
VDDI
Voltage between VDDA and
VDDA, VDDB GNDA, and VDDB and GNDB
(See “9. Ordering Guide” )
IDDI(Q)
Input Pin Leakage Current
IVIA, IVIB,
IPWM
–10
—
+10
µA dc
Input Pin Leakage Current
IDISABLE
–10
—
+10
µA dc
Logic High Input Threshold
VIH
2.0
—
—
V
Logic Low Input Threshold
VIL
—
—
0.8
V
Input Hysteresis
VIHYST
400
450
—
mV
Logic High Output Voltage
VOAH,
VOBH
IOA, IOB = –1 mA
(VDDA
/VDDB)
— 0.04
—
—
V
Logic Low Output Voltage
VOAL, VOBL
IOA, IOB = 1 mA
—
—
0.04
V
Output Short-circuit Pulsed
Sink Current
IOA(SCL),
IOB(SCL)
Si8230/1/2, Figure 4
—
0.5
—
Si8233/4/5/6, Figure 4
—
4.0
—
Output Short-circuit Pulsed
Source Current
IOA(SCH),
IOB(SCH)
Si8230/1/2, Figure 5
—
0.25
—
Si8233/4/5/6, Figure 5
—
2.0
—
Si8230/1/2
—
5.0
—
Output Sink Resistance
RON(SINK)
Si8233/4/5/6
—
1.0
—
Si8230/1/2
—
15
—
Si8233/4/5/6
—
2.7
—
A
Output Source Resistance
RON(SOURCE)

Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k.
6
Rev. 0.3
Si823x
Table 1. Electrical Characteristics1 (Continued)
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
VDDI Undervoltage Threshold
VDDIUV+
VDDI rising
3.60
4.0
4.45
V
VDDI Undervoltage Threshold
VDDIUV–
VDDI falling
3.30
3.70
4.15
V
VDDI Lockout Hysteresis
VDDIHYS
—
250
—
mV
VDDA, VDDB Undervoltage
Threshold
VDDAUV+,
VDDBUV+
VDDA, VDDB rising
5 V threshold
See Figure 36 on page 25.
5.20
5.80
6.30
V
8 V threshold
See Figure 37 on page 25.
7.50
8.60
9.40
V
10 V threshold
See Figure 38 on page 25.
9.60
11.1
12.2
V
12.5 V threshold
See Figure 39 on page 25.
12.4
13.8
14.8
V
VDDA, VDDB Undervoltage
Threshold
VDDAUV–,
VDDBUV–
VDDA, VDDB falling
5 V threshold
See Figure 36 on page 25.
4.90
5.52
6.0
V
8 V threshold
See Figure 37 on page 25.
7.20
8.10
8.70
V
10 V threshold
See Figure 38 on page 25.
9.40
10.1
10.9
V
12.5 V threshold
See Figure 39 on page 25.
11.6
12.8
13.8
V
VDDA, VDDB
Lockout hysteresis
VDDAHYS,
VDDBHYS
UVLO voltage = 5 V
—
280
—
mV
VDDA, VDDB
Lockout hysteresis
VDDAHYS,
VDDBHYS
UVLO voltage = 8 V
—
600
—
mV
VDDA, VDDB
Lockout hysteresis
VDDAHYS,
VDDBHYS
UVLO voltage = 10 V or 12.5 V
—
1000
—
mV
—
10
—
ns
—
30
60
ns
—
—
5.60
ns
DT = VDDI, No-Connect
—
0.4
—
ns
Figure 41, RDT = 100 k
—
900
—
ns
Figure 41, RDT = 6 k
—
70
—
ns
CL = 200 pF (Si8230/1/2)
—
—
12
ns
CL = 200 pF (Si8233/4/5/6)
—
—
20
ns
AC Specifications
Minimum Pulse Width
Propagation Delay
tPHL, tPLH
Pulse Width Distortion
|tPLH - tPHL|
PWD
Minimum Overlap Time2
TDD
Programmed Dead Time3
Output Rise and Fall Time
CL = 200 pF
DT
tR,tF
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k.
Rev. 0.3
7
Si823x
Table 1. Electrical Characteristics1 (Continued)
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Shutdown Time from
Disable True
Restart Time from
Disable False
Symbol
Test Conditions
Min
Typ
Max
Units
tSD
—
—
60
ns
tRESTART
—
—
60
ns
Device Start-up Time
tSTART
Time from VDD_ = VDD_UV+
to VOA, VOB = VIA, VIB
—
5
7
µs
Common Mode
Transient Immunity
CMTI
VIA, VIB, PWM = VDDI or 0 V
30
50
—
kV/µs
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k.
8
Rev. 0.3
Si823x
2.1. Test Circuits
Figures 4 and 5 depict sink current and source current test circuits.
VDDA = VDDB = 15 V
VDDI
(5 V)
IN_
INPUT
VDD
10
OUT_
Si823x
SCHOTTKY
VSS
1 µF
1 µF
CER
Measure
100 µF
5V
+
_
5V
+
_
10 µF
EL
RSNS
0.1
50 ns
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 4. Sink Current Test Circuit
VDDA = VDDB = 15 V
VDDI
(5 V)
INPUT
IN_
VDD
Si823x
10
OUT_
SCHOTTKY
VSS
1 µF
1 µF
CER
Measure
100 µF
10 µF
EL
RSNS
0.1
50 ns
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 5. Source Current Test Circuit
Rev. 0.3
9
Si823x
Table 2. Absolute Maximum Ratings1
Parameter
Storage Temperature2
Ambient Temperature under Bias
Input-side Supply Voltage
Driver-side Supply Voltage
Voltage on any pin with respect to ground
Output Drive Current per channel
Lead Solder Temperature (10 sec.)
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
Maximum Isolation (Output to Output) (1 sec)
WB SOIC-16
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16
Maximum Isolation (Output to Output) (1 sec)
NB SOIC-16
Maximum Isolation (Input to Output) (1 sec)
14 LD LGA without thermal pad
Maximum Isolation (Output to Output) (1 sec)
14 LD LGA without thermal pad
Maximum Isolation (Input to Output) (1 sec)
14 LD LGA with thermal pad
Maximum Isolation (Output to Output) (1 sec)
14 LD LGA with thermal pad
Symbol
TSTG
TA
VDDI
VDDA, VDDB
VIN
IO
Min
–65
–40
–0.6
–0.6
–0.5
—
—
Typ
—
—
—
—
—
—
—
Max
+150
+125
6.0
30
VDD + 0.5
10
260
Units
°C
°C
V
V
V
mA
°C
—
—
6500
VRMS
—
—
2500
VRMS
—
—
4250
VRMS
—
—
2500
VRMS
—
—
3850
VRMS
—
—
650
VRMS
—
—
1850
VRMS
—
—
0
VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. VDE certifies storage temperature from –40 to 150 °C.
Table 3. Regulatory Information*
CSA
The Si823x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
VDE
The Si823x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
UL
The Si823x is certified under UL1577 component recognition program. For more details, see File E257455.
*Note: Regulatory Certifications apply to 1.5 kVRMS rated devices which are production tested to 1.8 kVRMS for 1 sec.
Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "9.Ordering Guide" on page 37.
10
Rev. 0.3
Si823x
Table 4. Insulation and Safety-Related Specifications
Value
14 LD
NBSOIC-16
14 LD
WBSOIC-16
LGA w/ Unit
LGA
WBSOIC-16
5 kVRMS
Pad
2.5
kVRMS
2.5 kVRMS
1.5 kVRMS
Test
Condition
Parameter
Symbol
Nominal Air Gap
(Clearance)1
L(1O1)
8.0
4.01
3.5
1.75
mm
Nominal External Tracking
(Creepage)1
L(1O2)
8.0
4.01
3.5
1.75
mm
0.014
0.014
0.014
0.014
mm
>175
>175
>175
>175
V
1012
1012
1012
1012

1.4
1.4
1.4
1.4
pF
4.0
4.0
4.0
4.0
pF
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking
Index)
CTI
Resistance
(Input-Output)2
RIO
Capacitance
(Input-Output)2
CIO
Input Capacitance3
DIN IEC
60112/VDE
0303 Part 1
f = 1 MHz
CI
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “10. Package Outline:
16-Pin Wide Body SOIC” , “12. Package Outline: Narrow Body SOIC” , “14. Package Outline: 14 LD LGA (5 x 5 mm)” ,
and “16. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm)” . VDE certifies the clearance and creepage limits
as 4.7 mm minimum for the NB SOIC-16 and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a
clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits
as 3.9 mm minimum for the NB SOIC 16 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si823x is converted into a 2-terminal device. Pins 1–8 (1-7, 14 LD LGA)
are shorted together to form the first terminal and pins 9–16 (8-14, 14 LD LGA) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 5. IEC 60664-1 (VDE 0884 Part 2) Ratings
Specification
Parameter
Basic Isolation Group
Installation Classification
WB
SOIC-16
NB
SOIC-16
14 LD
LGA
14 LD
LGA
w/ Pad
Material Group
IIIa
IIIa
IIIa
IIIa
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-IV
I-III
I-III
I-III
Rated Mains Voltages < 400 VRMS
I-III
I-II
I-II
I-II
Rated Mains Voltages < 600 VRMS
I-III
I-II
I-II
I-I
Test Conditions
Rev. 0.3
11
Si823x
Table 6. IEC 60747-5-2 Insulation Characteristics*
Characteristic
Parameter
Symbol
Maximum Working Insulation
Voltage
VIORM
Input to Output Test Voltage
Highest Allowable Overvoltage (Transient Overvoltage,
tTR = 10 sec)
VPR
Test Condition
560
373
Method a
After Environmental Tests
Subgroup 1
(VIORM x 1.6 = VPR,
tm = 60 sec, Partial
Discharge < 5 pC)
1590
896
597
Method b1
(VIORM x 1.875 = V
PR, 100%
Production Test,
tm = 1 sec,
Partial Discharge <
5 pC)
1375
1050
700
After Input and/or
Safety Test
Subgroup 2/3
(VIORM x 1.2 = VPR,
tm = 60 sec, Partial
Discharge < 5 pC)
1018
672
448
6000
4000
2650
2
2
2
>109
>109
>109
VTR
RS
Unit
NB SOIC-16 14 LD LGA
14 LD LGA
w/ Pad
891
Pollution Degree (DIN VDE
0110, Table 1)
Insulation Resistance at TS,
VIO = 500 V
WB
SOIC-16
V peak
V peak
V peak
*Note: The Si823x is suitable for basic electrical isolation within the safety limit data. Maintenance of the safety data is
ensured by protective circuits. The Si823x provides a climate classification of 40/125/21.
12
Rev. 0.3

Si823x
Table 7. IEC Safety Limiting Values1
Parameter
Case Temperature
Symbol
Test Condition
TS
Safety Input Current
IS
Device Power
Dissipation2
PD
JA = 100 °C/W (WB SOIC-16),
105 °C/W (NB SOIC-16, 14 LD LGA),
50 °C/W (14 LD LGA w/ Pad)
VDDI = 5.5 V,
VDDA = VDDB= 24 V,
TJ = 150 °C, TA = 25 °C
WB
SOIC-16
NB
SOIC-16
14
LD LGA
14 LD
LGA w/
Pad
Unit
150
150
150
150
°C
50
50
50
100
mA
1.2
1.2
1.2
1.2
W
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 6.
2. The Si823x is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle
square wave.
Rev. 0.3
13
Si823x
Table 8. Thermal Characteristics
Parameter
Safety-Limiting Current (mA)
IC Junction-to-Air Thermal Resistance
Symbol
WB
SOIC-16
NB
SOIC-16
14 LD
LGA
14 LD
LGA w/
Pad
Unit
JA
100
105
105
50
°C/W
60
50
VDDI = 5.5 V
VDDA, VDDB = 24 V
40
30
20
10
0
0
50
100
150
Case Temperature (ºC)
200
Safety-Limiting Current (mA)
Figure 6. WB SOIC-16, NB SOIC-16, 14 LD LGA Thermal Derating Curve, Dependence of Safety
Limiting Values with Case Temperature per DIN EN 60747-5-2
120
VDDI = 5.5 V
VDDA, VDDB = 24 V
100
80
60
40
20
0
0
50
100
150
Case Temperature (ºC)
200
Figure 7. 14 LD LGA with Pad Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
14
Rev. 0.3
Si823x
2.2. Theory of Operation
The operation of an Si823x channel is analogous to that of an opto coupler and gate driver, except an RF carrier is
modulated instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si823x channel is shown in
Figure 8.
Transmitter
Receiver
Driver
RF
OSCILLATOR
VDD
A
Dead
time
control
MODULATOR
SemiconductorBased Isolation
Barrier
B
DEMODULATOR
0.5 to 4 A
peak
Gnd
Figure 8. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 9 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 9. Modulation Scheme
Rev. 0.3
15
Si823x
3. Typical Operating Characteristics (0.5 Amp)
The typical performance characteristics depicted in Figures 10 through 21 are for information purposes only. Refer
to Table 1 on page 6 for actual specification limits.
VDDA Supply Current (mA)
10
Rise/Fall Time (ns)
8
Tfall
6
4
Trise
2
VDD=12V, 25°C
CL = 100 pF
7
Duty Cycle = 50%
CL = 100 pF
1 Channel Switching
6
5
500kHz
4
3
100kHz
2
1
50 kHz
0
9
0
9
12
15
18
21
1MHz
14
24
19
24
VDDA Supply Voltage (V)
VDDA Supply (V)
Figure 10. Rise/Fall Time vs. Supply Voltage
Figure 13. Supply Current vs. Supply Voltage
30
Supply Current (mA)
Propagation Delay (ns)
5
25
H-L
20
L-H
15
4
3
VDDA = 15V,
f = 250kHz, CL = 0 pF
Duty Cycle = 50%
2 Channels Switching
2
1
VDD=12V, 25°C
CL = 100 pF
-50
0
10
9
12
15
18
21
50
100
Temperature (°C)
24
VDDA Supply (V)
Figure 14. Supply Current vs. Temperature
Figure 11. Propagation Delay vs. Supply
Voltage
40
Rise/Fall Time (ns)
35
VDDA Supply Current (mA)
4
Duty Cycle = 50%
CL = 0 pF
1 Channel Switching
3.5
1MHz
3
500kHz
2.5
2
50 kHz
24
VDDA Supply Voltage (V)
15
10
VDD=12V, 25°C
0.5
1.0
1.5
Load (nF)
Figure 15. Rise/Fall Time vs. Load
Figure 12. Supply Current vs. Supply Voltage
16
Tfall
0.0
1
19
20
0
1.5
14
25
5
100kHz
9
Trise
30
Rev. 0.3
2.0
50
4
45
3.75
40
3.5
35
Source Current (A)
Propagation Delay (ns)
Si823x
L-H
30
H-L
25
20
3.25
3
2.75
2.5
2.25
15
VDD=12V, 25°C
10
0.0
0.5
1.0
VDD=12V, Vout=VDD-5V
2
1.5
10
2.0
15
20
25
Supply Voltage (V)
Load (nF)
Figure 19. Output Source Current vs. Supply
Voltage
Figure 16. Propagation Delay vs. Load
25
L-H
20
Sink Current (A)
Propagation Delay (ns)
30
H-L
15
VDD=12V, Load = 200pF
10
-40
-20
0
20
40
60
80
100
120
7
6.75
6.5
6.25
6
5.75
5.5
5.25
5
4.75
4.5
4.25
4
VDD=12V, Vout=5V
-40
Temperature (°C)
-10
Figure 17. Propagation Delay vs. Temperature
20
50
80
110
Temperature (°C)
Figure 20. Output Sink Current vs. Temperature
9
3.5
3.25
Source Current (A)
Sink Current (A)
8
7
6
5
12
14
16
18
20
2.75
2.5
2.25
VDD=12V, Vout=5V
4
10
3
22
24
VDD=12V, Vout=VDD-5V
2
-40
Supply Voltage (V)
Figure 18. Output Sink Current vs. Supply
Voltage
-10
20
50
80
110
Temperature (°C)
Figure 21. Output Source Current vs.
Temperature
Rev. 0.3
17
Si823x
4. Typical Operating Characteristics (4.0 Amp)
The typical performance characteristics depicted in Figures 22 through 33 are for information purposes only. Refer
to Table 1 on page 6 for actual specification limits.
VDDA Supply Current (mA)
10
Rise/Fall Time (ns)
8
Tfall
6
Trise
4
2
14
15
18
6
2
21
24
14
19
24
Figure 25. Supply Current vs. Supply Voltage
10
Supply Current (mA)
30
Propagation Delay (ns)
50 kHz
0
VDDA Supply Voltage (V)
Figure 22. Rise/Fall Time vs. Supply Voltage
25
L-H
8
6
VDDA = 15V,
f = 250kHz, CL = 0 pF
Duty Cycle = 50%
2 Channels Switching
4
2
20
0
-50
0
50
H-L
15
Figure 26. Supply Current vs. Temperature
10
9
12
15
18
21
40
24
35
Rise/Fall Time (ns)
VDDA Supply (V)
Figure 23. Propagation Delay vs. Supply
Voltage
14
Duty Cycle = 50%
CL = 0 pF
1 Channel Switching
12
1MHz
19
15
10
VDD=12V, 25°C
1
2
3
4
5
6
7
8
Figure 27. Rise/Fall Time vs. Load
50 kHz
14
Tfall
Load (nF)
100kHz
2
9
20
0
6
0
25
0
500kHz
4
Trise
30
5
10
8
100
Temperature (°C)
VDD=12V, 25°C
CL = 100 pF
VDDA Supply Current (mA)
100kHz
4
VDDA Supply (V)
24
VDDA Supply Voltage (V)
Figure 24. Supply Current vs. Supply Voltage
18
500kHz
8
9
0
12
1MHz
10
VDD=12V, 25°C
CL = 100 pF
9
Duty Cycle = 50%
CL = 100 pF
1 Channel Switching
12
Rev. 0.3
9
10
Si823x
4
50
3.75
Propagation Delay (ns)
45
H-L
35
Source Current (A)
40
L-H
30
25
20
3.25
3
2.75
2.5
2.25
15
0
1
2
3
4
5
6
7
10
8
9
30
Sink Current (A)
H-L
L-H
20
15
VDD=12V, Load = 200pF
-40
-20
0
20
40
60
80
100
7
6.75
6.5
6.25
6
5.75
5.5
5.25
5
4.75
4.5
4.25
4
25
VDD=12V, Vout=5V
-40
120
-10
20
50
80
110
Temperature (°C)
Temperature (°C)
Figure 29. Propagation Delay vs. Temperature
Figure 32. Output Sink Current vs. Temperature
3.5
9
3.25
Source Current (A)
8
Sink Current (A)
20
Supply Voltage (V)
Figure 31. Output Source Current vs. Supply
Voltage
Figure 28. Propagation Delay vs. Load
10
15
10
Load (nF)
25
VDD=12V, Vout=VDD-5V
2
VDD=12V, 25°C
10
Propagation Delay (ns)
3.5
7
6
5
3
2.75
2.5
2.25
VDD=12V, Vout=5V
4
10
12
14
16
18
20
22
VDD=12V, Vout=VDD-5V
2
24
-40
Supply Voltage (V)
-10
20
50
80
110
Temperature (°C)
Figure 30. Output Sink Current vs. Supply
Voltage
Figure 33. Output Source Current vs.
Temperature
Rev. 0.3
19
Si823x
5. Application Information
The Si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations.
5.1. Products
Table 9 shows the configuration and functional overview for each product in this family.
Table 9. Si823x Family Overview
Part Number
Configuration
Overlap
Protection
Programmable
Dead Time
Inputs
Peak Output
Current (A)
Si8230
High-Side/Low-Side


VIA, VIB
0.5
Si8231
High-Side/Low-Side


PWM
0.5
Si8232
Dual Driver
—
—
VIA, VIB
0.5
Si8233
High-Side/Low-Side


VIA, VIB
4.0
Si8234
High-Side/Low-Side


PWM
4.0
Si8235/6
Dual Driver
—
—
VIA, VIB
4.0
5.2. Device Behavior
Table 10 contains truth tables for the Si8230/3, Si8231/4, and Si8232/5/6 families.
Table 10. Si823x Family Truth Table*
Si8230/3 (High-Side/Low-Side) Truth Table
Inputs
VDDI State Disable
VIA
VIB
L
L
Powered
L
H
H
Output
Notes
VOA
VOB
L
L
L
Output transition occurs after internal dead time
expires.
Powered
L
L
H
Output transition occurs after internal dead time
expires.
L
Powered
L
H
L
Output transition occurs after internal dead time
expires.
H
H
Powered
L
L
L
Invalid state. Output transition occurs after internal
dead time expires.
X
X
Unpowered
X
L
L
Output returns to input state within 7 µs of VDDI
power restoration.
X
X
Powered
H
L
L
Device is disabled.
Si8231/4 (PWM Input High-Side/Low-Side) Truth Table
PWM Input
VDDI State Disable
Output
VOA
VOB
Notes
H
Powered
L
H
L
Output transition occurs after internal dead time
expires.
L
Powered
L
L
H
Output transition occurs after internal dead time
expires.
X
Unpowered
X
L
L
Output returns to input state within 7 µs of VDDI
power restoration.
X
Powered
H
L
L
Device is disabled.
*Note: This truth table assumes VDDA and VDDB are powered. If VDDA or VDDB power is lost, the respective output state
(VOA or VOB) is undetermined.
20
Rev. 0.3
Si823x
Table 10. Si823x Family Truth Table* (Continued)
Si8232/5/6 (Dual Driver) Truth Table
Inputs
VDDI State Disable
VIA
VIB
L
L
Powered
L
H
H
Output
Notes
VOA
VOB
L
L
L
Output transition occurs immediately
(no internal dead time).
Powered
L
L
H
Output transition occurs immediately
(no internal dead time).
L
Powered
L
H
L
Output transition occurs immediately
(no internal dead time).
H
H
Powered
L
H
H
Output transition occurs immediately
(no internal dead time).
X
X
Unpowered
X
L
L
Output returns to input state within 7 µs of VDDI
power restoration.
X
X
Powered
H
L
L
Device is disabled.
*Note: This truth table assumes VDDA and VDDB are powered. If VDDA or VDDB power is lost, the respective output state
(VOA or VOB) is undetermined.
Rev. 0.3
21
Si823x
5.3. Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these
supplies must be placed as close to the VDD and GND pins of the Si823x as possible. The optimum values for
these capacitors depend on load current and the distance between the chip and the regulator that powers it. Low
effective series resistance (ESR) capacitors, such as Tantalum, are recommended.
5.4. Power Dissipation Considerations
Proper system design must assure that the Si823x operates within safe thermal limits across the entire load range.
The Si823x total power dissipation is the sum of the power dissipated by bias supply current, internal switching
losses, and power delivered to the load. Equation 1 shows total Si823x power dissipation. In a non-overlapping
system, such as a high-side/low-side driver, n = 1. For a dual driver with each driver having an independent load, n
can have a maximum value of 2, corresponding to a 100% overlap between the two outputs.
2
2
P D = V DDI I DDI + 2  V DDO I QOUT + C int V DDO F  + 2n  C L V DDO F 
where:
P D is the total Si823x device power dissipation (W)
I DDI is the input-side maximum bias current (3 mA)
I QOUT is the driver die maximum bias current (2.5 mA)
C int is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)
V DDI is the input-side VDD supply voltage (4.5 to 5.5 V)
V DDO is the driver-side supply voltage (10 to 24 V)
F is the switching frequency (Hz)
n is the overlap constant (max value = 2)
Equation 1.
The maximum power dissipation allowable for the Si823x is a function of the package thermal resistance, ambient
temperature, and maximum allowable junction temperature, as shown in Equation 2:
T jmax – T A
P Dmax  --------------------------ja
where:
P Dmax = Maximum Si823x power dissipation (W)
T jmax = Si823x maximum junction temperature (145 °C)
T A = Ambient temperature (°C)
ja = Si823x junction-to-air thermal resistance (105 °C/W)
F = Si823x switching frequency (Hz)
Equation 2.
Substituting values for PDMAX TjMAX, TA, and ja into Equation 2 results in a maximum allowable total power
dissipation of 1.1 W. Maximum allowable load is found by substituting this limit and the appropriate datasheet
values from Table 1 on page 6 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and
Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V.
–3
1.4  10
– 11
C L(MAX) = -------------------------- – 7.5  10
F
Equation 3.
–3
1.4  10
– 10
C L(MAX) = -------------------------- – 3.7  10
F
Equation 4.
22
Rev. 0.3
Si823x
Equation 1 and Equation 2 are graphed in Figure 34 where the points along the load line represent the package
dissipation-limited value of CL for the corresponding switching frequency.
1 6 ,0 0 0
0 .5 A D r i ve r ( p F )
4 A D r i ve r ( p F )
1 4 ,0 0 0
1 2 ,0 0 0
Max Load (pF)
1 0 ,0 0 0
8 ,0 0 0
6 ,0 0 0
4 ,0 0 0
2 ,0 0 0
0
700
650
600
550
500
450
400
350
300
250
200
150
100
F re q u e n c y (K h z )
Figure 34. Max Load vs. Switching Frequency
Rev. 0.3
23
Si823x
5.5. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si823x VDD lines. Care must be taken to
minimize parasitic inductance in these paths by locating the Si823x as close to the device it is driving as possible.
In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and
ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for
power devices and small signal components provides the best overall noise performance.
5.6. Device Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 35, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low
when input side power supply (VDDI) is not present.
5.6.1. Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period
tSTART. Following this, the outputs follow the states of inputs VIA and VIB.
5.6.2. Under Voltage Lockout
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. The input (control) side, Driver A and Driver B, each have
their own under voltage lockout monitors.
The Si823x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver
outputs, VOA and VOB, remain low when the input side of the Si823x is in UVLO and their respective VDD supply
(VDDA, VDDB) is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA
unconditionally enters UVLO when VDDA falls below VDDAUV– and exits UVLO when VDDA rises above
VDDAUV+.
UVLO+
UVLO-
VDD HYS
VDDI
UVLO+
UVLO-
VDD HYS
VDDA
VIA
DISABLE
tSTART
tSD
tSTART
tSTART
tSD
tRESTART
tPHL
tPLH
VOA
Figure 35. Device Behavior during Normal Operation and Shutdown
24
Rev. 0.3
Si823x
5.6.3. Under Voltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 36
through 39, upon power up, the Si823x is maintained in UVLO until VDD rises above VDDUV+. During power down,
the Si823x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+ –
VDDHYS).
V DDUV+ (Typ)
3.5
Output Voltage (VO) 10.5
Output Voltage (VO) 10.5
V DDUV+ (Typ)
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.5
Supply Voltage (V DD - V SS) (V)
9.0
Figure 36. Si823x UVLO Response (5 V)
10.0 10.5 11.0 11.5 12.0 12.5
Figure 38. Si823x UVLO Response (10 V)
V DDUV+ (Typ)
Output Voltage (VO) 10.5
Output Voltage (VO) 10.5
V DDUV+ (Typ)
6.0
9.5
Supply Voltage (V DD - V SS) (V)
6.5
7.0
7.5
8.0
8.5
9.0
11.3
9.5 10.0
11.8
12.3 12.8 13.3 13.8 14.3 14.8 15.3
Supply Voltage (V DD - V SS) (V)
Supply Voltage (V DD - V SS) (V)
Figure 39. Si823x UVLO Response (12.5 V)
Figure 37. Si823x UVLO Response (8 V)
Rev. 0.3
25
Si823x
5.6.4. Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB
causes the corresponding output to go high. For PWM input versions (Si8231/4), VOA is high and VOB is low when
the PWM input is high, and VOA is low and VOB is high when the PWM input is low.
5.6.5. Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of VIA
and VIB. Device operation terminates within tSD after DISABLE = VIH and resumes within tRESTART after
DISABLE = VIL. The DISABLE input has no effect if VDDI is below its UVLO level (i.e. VOA, VOB remain low).
5.7. Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si8230/1/3/4) include programmable overlap protection to prevent outputs VOA and
VOB from being high at the same time. These devices also include programmable dead time, which adds a userprogrammable delay between transitions of VOA and VOB (Figure 26.A). When enabled, dead time is present on
all transitions, even after overlap recovery (Figure 26.B). The amount of dead time delay (DT) is programmed by a
single resistor (RDT) connected from the DT input to ground per Equation 5. Note that the dead time pin can be
tied to VDDI or left floating to provide a nominal dead time at approximately 400 ps.
DT  10  RDT
where:
DT = dead time (ns)
and
RDT = dead time programming resistor (k 
Equation 5.
The device driving VIA and VIB should provide a minimum dead time of TDD to avoid activating overlap protection.
Input/output timing waveforms for the two-input drivers are shown in Figure 40, and dead time waveforms are
shown in Figure 41.
Ref
VIA
`
VIB
VOA
VOB
A
B
C
D
E
F
G
H
I
Description
A
Normal operation: VIA high, VIB low.
B
Normal operation: VIB high, VIA low.
C
Contention: VIA = VIB = high.
D
Recovery from contention: VIA transitions low.
E
Normal operation: VIA = VIB = low.
F
Normal operation: VIA high, VIB low.
G
Contention: VIA = VIB = high.
H
Recovery from contention: VIB transitions low.
I
Normal operation: VIB transitions high.
Figure 40. Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers
26
Rev. 0.3
Si823x
OVERLAP
OVERLAP
VOB
VIA
VIA
VIB
50%
VIB
DT
DT
DT
DT
90%
VOA
VOA
10%
DT
DT
90%
VOB
VOB
10%
A. Typical Dead Time Operation
B. Dead Time Operation During Overlap
Figure 41. Dead Time Waveforms for High-Side/Low-Side Two-Input Drivers
Rev. 0.3
27
Si823x
6. RF Radiated Emissions
The Si823x family uses a RF carrier frequency of approximately 700 MHz. This results in a small amount of
radiated emissions at this frequency and its harmonics. The radiation is not from the IC but, rather, is due to a small
amount of RF energy driving the isolated ground planes which can act as a dipole antenna.
The unshielded Si8230 evaluation board passes FCC Class B (Part 15) requirements. Table 11 shows measured
emissions compared to FCC requirements. Note that the data reflects worst-case conditions where all inputs are
tied to logic 1 and the RF transmitters are fully active.
Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less
efficient antenna.
Table 11. Radiated Emissions
Frequency Measured
(MHz)
(dBµV/m)
FCC Spec
(dBµV/m)
Compared to
Spec (dB)
712
29
37
–8
1424
39
54
–15
2136
42
54
–12
2848
43
54
–11
4272
44
54
–10
4984
44
54
–10
5696
44
54
–10
6.1. RF, Magnetic, and Common Mode Transient Immunity
The Si823x families have very high common mode transient immunity while transmitting data. This is typically
measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements
show no failures at 30 kV/µs (minimum). During a high surge event, the output may glitch low for up to 20–30 ns,
but the output corrects immediately after the surge event.
The Si823x families pass the industrial requirements of CISPR24 for RF immunity of 10 V/m using an unshielded
evaluation board. As shown in Figure 20, the isolated ground planes form a parasitic dipole antenna. The PCB
should be laid-out to not act as an efficient antenna for the RF frequency of interest. RF susceptibility is also
significantly reduced when the end system is housed in a metal enclosure, or otherwise shielded.
The Si823x digital isolator can be used in close proximity to large motors and various other magnetic-field
producing equipment. In theory, data transmission errors can occur if the magnetic field is too large and the field is
too close to the isolator. However, in actual use, the Si823x devices provide extremely high immunity to external
magnetic fields and have been independently evaluated to withstand magnetic fields of at least 1000 A/m
according to the IEC 61000-4-8 and IEC 61000-4-9 specifications.
GND1
Isolator
GND2
Dipole
Antenna
Figure 42. Dipole Antenna
28
Rev. 0.3
Si823x
7. Applications
The following examples illustrate typical circuit configurations using the Si823x.
7.1. High-Side / Low-Side Driver
Figure 43A shows the Si8230/3 controlled using the VIA and VIB input signals, and Figure 43B shows the Si8231/4
controlled by a single PWM signal.
VDD2
VDDI
D1
VDDI
C1
1uF
1500 V max
1500 V max
VDDA
VDDA
GNDI
CB
OUT1
VIA
OUT2
VIB
RDT
PWMOUT
PWM
GNDA
DT
CONTROLLER
CB
Q1
VOA
GNDA
DT
Si8230/3
CONTROLLER
RDT
Si8231/4
VDDB
VDDB
VDDB
C3
10uF
DISABLE
I/O
C3
10uF
DISABLE
GNDB
VOB
Q1
VOA
VDDB
I/O
D1
C2
1 µF
VDDI
C1
1uF
GNDI
VDD2
VDDI
C2
1 µF
GNDB
Q2
A
VOB
Q2
B
Figure 43. Si823x in Half-Bridge Application
For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver
for Q1, which has a maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note
that the input side of the Si823x requires VDD in the range of 4.5 to 5.5 V, while the VDDA and VDDB output side
supplies must be between 6.5 and 24 V with respect to their respective grounds. The boot-strap start up time will
depend on the CB cap chosen. VDD2 is usually the same as VDDB. Also note that the bypass capacitors on the
Si823x should be located as close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass
capacitors be used to reduce high frequency noise and maximize performance.
Rev. 0.3
29
Si823x
7.2. Dual Driver
Figure 44 shows the Si823x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be
referenced to a common ground or to different grounds with as much as 1500 V dc between them.
VDDI
VDDI
C1
10 µF
Q1
VOA
GNDI
VDDA
PH1
VIA
PH2
VIB
VDDA
C2
10 µF
GNDA
CONTROLLER
Si8235/6
VDDB
VDDB
I/O
DISABLE
C3
10 µF
GNDB
VOB
Q2
Figure 44. Si8235 in a Dual Driver Application
7.3. Dual Driver with Thermally Enhanced Package (Si8236)
The thermal pad of the Si8236 must be connected to a heat spreader to lower thermal resistance. Generally, the
larger the thermal shield’s area, the lower the thermal resistance. It is recommended that a thermal vias also be
used to add mass to the shield. Vias generally have much more mass than the shield alone and consume less
space, thus reducing thermal resistance more effectively. While the heat spreader is not generally a circuit ground,
it is a good reference plane for the Si8236 and is also useful as a shield layer for EMI reduction.
With a 10mm2 thermal plane on the outer layers (including 20 thermal vias), the thermal impedance of the Si8236
was measured at 50 °C/W. This is a significant improvement over the Si835 which does not include a thermal pad.
The Si8235’s thermal resistance was measured at 105 °C /W.
30
Rev. 0.3
Si823x
8. Pin Descriptions
SOIC-16 (Narrow)
SOIC-16 (Wide)
VIA
1
16
VDDA
VIA
1
16
VDDA
VIB
2
15
VOA
VIB
2
15
VOA
VDDI
3
14
GNDA
VDDI
3
14
GNDA
GNDI
4
13
NC
GNDI
4
DISABLE
5
12
NC
DISABLE
5
Si8230 13
Si8233 12
DT
6
11
VDDB
DT
6
11
VDDB
NC
7
10
VOB
NC
7
10
VOB
VDDI
8
9
VDDI
8
9
Si8230
Si8233
GNDB
NC
NC
GNDB
Table 12. Si8230/3 Two-Input HS/LS Isolated Driver (SOIC-16)
Pin
Name
1
VIA
Non-inverting logic input terminal for Driver A.
2
VIB
Non-inverting logic input terminal for Driver B.
3
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
4
GNDI
Input-side ground terminal.
5
Description
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the
dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when connected to VDDI or left open (see "5.7.Programmable Dead Time and Overlap Protection" on
page 26).
7
NC
No connection.
8
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
9
GNDB
Ground terminal for Driver B.
10
VOB
11
VDDB
12
NC
No connection.
13
NC
No connection.
14
GNDA
15
VOA
16
VDDA
Driver B output (low-side driver).
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
Ground terminal for Driver A.
Driver A output (high-side driver).
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 0.3
31
Si823x
SOIC-16 (Narrow)
SOIC-16 (Wide)
PWM
1
16
VDDA
NC
2
15
VOA
VDDI
3
14
GNDI
4
DISABLE
5
DT
PWM
1
16
VDDA
NC
2
15
VOA
GNDA
VDDI
3
14
GNDA
13
NC
GNDI
4
12
NC
DISABLE
5
Si8231 13
Si8234 12
6
11
VDDB
DT
6
11
VDDB
NC
7
10
VOB
NC
7
10
VOB
VDDI
8
9
VDDI
8
9
Si8231
Si8234
GNDB
NC
NC
GNDB
Table 13. Si8231/4 PWM Input HS/LS Isolated Driver (SOIC-16)
Pin
Name
1
PWM
2
NC
3
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
4
GNDI
Input-side ground terminal.
5
32
Description
PWM input.
No connection.
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the
dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when connected to VDDI or left open (see "5.7.Programmable Dead Time and Overlap Protection" on
page 26).
7
NC
No connection.
8
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
9
GNDB
Ground terminal for VOB driver output.
10
VOB
11
VDDB
12
NC
No connection.
13
NC
No connection.
14
GNDA
15
VOA
16
VDDA
Driver B output (low-side driver).
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
Ground terminal for Driver A.
Driver A output (high-side driver).
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 0.3
Si823x
SOIC-16 (Narrow)
SOIC-16 (Wide)
VIA
1
16
VDDA
VIA
1
16
VDDA
VIB
2
15
VOA
VIB
2
15
VOA
VDDI
3
14
GNDA
VDDI
3
14
GNDA
GNDI
4
13
NC
GNDI
4
DISABLE
5
12
NC
DISABLE
5
Si8232 13
Si8235 12
NC
6
11
VDDB
NC
6
11
VDDB
NC
7
10
VOB
NC
7
10
VOB
VDDI
8
9
VDDI
8
9
Si8232
Si8235
GNDB
NC
NC
GNDB
Table 14. Si8232/5 Dual Isolated Driver (SOIC-16)
Pin
Name
1
VIA
Non-inverting logic input terminal for Driver A.
2
VIB
Non-inverting logic input terminal for Driver B.
3
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
4
GNDI
Input-side ground terminal.
5
Description
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
NC
No connection.
7
NC
No connection.
8
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
9
GNDB
Ground terminal for VOB driver output.
10
VOB
11
VDDB
12
NC
No connection.
13
NC
No connection.
14
GNDA
15
VOA
16
VDDA
Driver B output.
Driver output VOB power supply voltage terminal; connect to a source of 6.5 to 24 V.
Ground terminal for Driver A.
Driver B output.
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 0.3
33
Si823x
LGA-14 (5 x 5 mm)
GNDI
1
14
VDDA
VIA
2
13
VOA
VIB
3
12
GNDA
VDDI
4
11
NC
DISABLE
5
10
VDDB
DT
6
7
VOB
VDDI
7
8
GNDB
Si8233
Table 15. Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA)
34
Pin
Name
Description
GNDI
1
Input-side ground terminal.
VIA
2
Non-inverting logic input terminal for Driver A.
VIB
3
Non-inverting logic input terminal for Driver B.
VDDI
4
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE
5
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 1 ns dead
time when connected to VDDI or left open (see"5.7.Programmable Dead Time and
Overlap Protection" on page 26).
VDDI
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB
8
Ground terminal for Driver B.
VOB
9
Driver B output (low-side driver).
VDDB
10
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
11
No connection.
GNDA
12
Ground terminal for Driver A.
VOA
13
Driver A output (high-side driver).
VDDA
14
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 0.3
Si823x
LGA-14 (5 x 5 mm)
GNDI
1
14
VDDA
PWM
2
13
VOA
NC
3
12
GNDA
VDDI
4
11
NC
DISABLE
5
10
VDDB
DT
6
7
VOB
VDDI
7
8
GNDB
Si8234
Table 16. Si8234 PWM Input HS/LS Isolated Driver (14 LD LGA)
Pin
Name
Description
GNDI
1
Input-side ground terminal.
PWM
2
PWM input.
NC
3
No connection.
VDDI
4
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE
5
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 1 ns dead
time when connected to VDDI or left open (see "5.7.Programmable Dead Time and
Overlap Protection" on page 26).
VDDI
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB
8
Ground terminal for Driver B.
VOB
9
Driver B output (low-side driver).
VDDB
10
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
11
No connection.
GNDA
12
Ground terminal for Driver A.
VOA
13
Driver A output (high-side driver).
VDDA
14
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 0.3
35
Si823x
LGA-14 (5 x 5 mm)
GNDI
1
14
VDDA
VIA
2
13
VOA
VIB
3
12
GNDA
11
NC
Si8235
Si8236
VDDI
4
DISABLE
5
10
VDDB
NC
6
7
VOB
VDDI
7
8
GNDB
Table 17. Si8235/6 Dual Isolated Driver (14 LD LGA)
36
Pin
Name
Description
GNDI
1
Input-side ground terminal.
VIA
2
Non-inverting logic input terminal for Driver A.
VIB
3
Non-inverting logic input terminal for Driver B.
VDDI
4
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE
5
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
NC
6
No connection.
VDDI
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB
8
Ground terminal for Driver B.
VOB
9
Driver B output (low-side driver).
VDDB
10
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
11
No connection.
GNDA
12
Ground terminal for Driver A.
VOA
13
Driver A output (high-side driver).
VDDA
14
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 0.3
Si823x
9. Ordering Guide
The ordering part number (OPN) naming convention is described in Figure 45. The currently available OPNs are
listed in Table 18. The part number convention is not intended to imply that all possible device configuration options
and their corresponding ordering part numbers (OPN) will be available or are included in the ordering guide table.
However, if there is a specific device configuration of interest that is currently not listed in the ordering guide table,
contact your local Silicon Labs sales representative, or go to the Silicon Labs Technical Support web page at
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a request for your
specific device configuration and OPN. Ordering part number options for 10 V and 12.5 V UVLO will be made
available only by request.
Si823YUV-R-TPn
ISOdriver Product
Peak Output Current (0,1,2=0.5A, 3,4,5=4A)
UVLO* level (A=5V, B=8V, C=10V, D=12.5V)
Insulation Rating (A=1.5kV,B=2.5kV,C=3.75kV,D=5kV)
Product Revision
Temp Range (I=-40 to +125C)
Package Type (S=SOIC, M=LGA)
Package Extension (1=Narrow Body)
Note: UVLO = Under Voltage Lock Out for VDDA, VDDB.
Figure 45. ISODriver OPN Naming Convention
Rev. 0.3
37
Si823x
Table 18. Ordering Part Numbers
Ordering Part
Number (OPN)
Inputs
Peak
UVLO
Configuration
Current Voltage
Isolation
Rating
Temperature
Range
Package
Type
Legacy
Ordering Part
Number (OPN)
2.5 kV Only
Wide Body (WB) Package Options
Si8230BB-B-IS
VIA, VIB
High Side/
Low Side
Si8231BB-B-IS
PWM
High Side/
Low Side
Si8232BB-B-IS
VIA,VIB
Dual Driver
Si8230-A-IS
0.5 A
8V
Si8231-A-IS
2.5 kVrms
Si8233BB-C-IS
VIA,VIB
High Side/
Low Side
Si8234BB-C-IS
PWM
High Side/
Low Side
Si8235BB-C-IS
VIA,VIB
Dual Driver
–40 to +125 °C
SOIC-16
Wide Body
Si8232-A-IS
Si8233-B-IS
4.0 A
8V
Si8234-B-IS
Si8235-B-IS
Narrow Body (NB) Package Options
Si8230BB-B-IS1
VIA,VIB
High Side/
Low Side
Si8231BB-B-IS1
PWM
High Side/
Low Side
Si8232BB-B-IS1
VIA,VIB
Dual Driver
0.5 A
8V
2.5 kVrms
Si8233BB-C-IS1
VIA,VIB
High Side/
Low Side
Si8234BB-C-IS1
PWM
High Side/
Low Side
Si8235BB-C-IS1
VIA,VIB
Dual Driver
4.0 A
–40 to +125 °C
SOIC-16
Narrow
Body
N/A
8V
Note: All packages are RoHS-compliant.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 and 14-LD LGA packages and MSL2A for narrow-body
SOIC-16 packages with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications
and peak solder temperatures.
38
Rev. 0.3
Si823x
Table 18. Ordering Part Numbers (Continued)
Ordering Part
Number (OPN)
Inputs
Peak
UVLO
Configuration
Current Voltage
Isolation
Rating
Temperature
Range
Package
Type
Legacy
Ordering Part
Number (OPN)
2.5 kV Only
LGA Package Options
Si8233BB-C-IM
VIA,VIB
High Side/
Low Side
Si8234BB-C-IM
PWM
High Side/
Low Side
Si8235BB-C-IM
VIA,VIB
Dual Driver
Si8235AB-C-IM
VIA,VIB
Dual Driver
5V
Si8236BA-C-IM
VIA, VIB
Dual Driver
8V
Si8236AA-C-IM
VIA,VIB
Dual Driver
5V
Si8233-B-IM
8V
LGA-14
5x5 mm
2.5 kVrms
4.0 A
Si8234-B-IM
Si8235-B-IM
–40 to +125 °C
N/A
1.5 kVrms
LGA-14
5x5 mm
with Thermal Pad
Si8236-B-IM
SOIC-16
Wide Body
N/A
5 kV Ordering Options
Si8230BD-B-IS
VIA, VIB
High Side/
Low Side
Si8231BD-B-IS
PWM
High Side/
Low Side
Si8232BD-B-IS
VIA, VIB
Dual Driver
0.5 A
8V
Si8233BD-C-IS
VIA, VIB
High Side/
Low Side
Si8234BD-C-IS
PWM
High Side/
Low Side
Si8235BD-C-IS
VIA, VIB
Dual Driver
5.0 kVrms
–40 to +125 °C
4.0 A
Note: All packages are RoHS-compliant.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 and 14-LD LGA packages and MSL2A for narrow-body
SOIC-16 packages with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications
and peak solder temperatures.
Rev. 0.3
39
Si823x
10. Package Outline: 16-Pin Wide Body SOIC
Figure 46 illustrates the package details for the Si823x in a 16-Pin Wide Body SOIC. Table 19 lists the values for
the dimensions shown in the illustration.
Figure 46. 16-Pin Wide Body SOIC
Table 19. Package Diagram Dimensions
Millimeters
Symbol
Min
Max
A
—
2.65
A1
0.1
0.3
D
10.3 BSC
E
10.3 BSC
E1
7.5 BSC
b
0.31
0.51
c
0.20
0.33
e
40
1.27 BSC
h
0.25
0.75
L
0.4
1.27

0°
7°
Rev. 0.3
Si823x
11. Land Pattern: Wide-Body SOIC
Figure 47 illustrates the recommended land pattern details for the Si823x in a 16-pin wide-body SOIC. Table 20
lists the values for the dimensions shown in the illustration.
Figure 47. 16-Pin SOIC Land Pattern
Table 20. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 0.3
41
Si823x
12. Package Outline: Narrow Body SOIC
Figure 48 illustrates the package details for the Si823x in a 16-pin narrow-body SOIC (SO-16). Table 21 lists the
values for the dimensions shown in the illustration.
Figure 48. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 21. Package Diagram Dimensions
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.31
0.51
c
0.17
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
L2
42
1.27
0.25 BSC
Rev. 0.3
Si823x
Table 21. Package Diagram Dimensions (Continued)
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC JSTD-020C specification for Small Body Components.
Rev. 0.3
43
Si823x
13. Land Pattern: Narrow Body SOIC
Figure 49 illustrates the recommended land pattern details for the Si823x in a 16-pin narrow-body SOIC. Table 22
lists the values for the dimensions shown in the illustration.
Figure 49. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 22. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
44
Rev. 0.3
Si823x
14. Package Outline: 14 LD LGA (5 x 5 mm)
Figure 50 illustrates the package details for the Si823x in an LGA outline. Table 23 lists the values for the
dimensions shown in the illustration.
Figure 50. Si823x LGA Outline
Table 23. Package Diagram Dimensions
Dimension
MIN
NOM
MAX
A
0.74
0.84
0.94
b
0.25
0.30
0.35
D
5.00 BSC
D1
4.15 BSC
e
0.65 BSC
E
5.00 BSC
E1
3.90 BSC
L
0.70
0.75
0.80
L1
0.05
0.10
0.15
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.15
eee
—
—
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 0.3
45
Si823x
15. Land Pattern: 14 LD LGA
Figure 51 illustrates the recommended land pattern details for the Si823x in a 14-pin LGA. Table 24 lists the values
for the dimensions shown in the illustration.
Figure 51. 14-Pin LGA Land Pattern
46
Rev. 0.3
Si823x
Table 24. 14-Pin LGA Land Pattern Dimensions
Dimension
(mm)
C1
4.20
E
0.65
X1
0.80
Y1
0.40
Notes:
General:
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05 mm.
Solder Mask Design:
4. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design:
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly:
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD020D specification for Small Body Components.
Rev. 0.3
47
Si823x
16. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm)
Figure 52 illustrates the package details for the Si8236 ISOdriver in an LGA outline. Table 25 lists the values for the
dimensions shown in the illustration.
Figure 52. Si823x LGA Outline with Thermal Pad
Table 25. Package Diagram Dimensions
Dimension
MIN
NOM
MAX
A
0.74
0.84
0.94
b
0.25
0.30
0.35
D
5.00 BSC
D1
4.15 BSC
e
0.65 BSC
E
5.00 BSC
E1
3.90 BSC
L
0.70
0.75
0.80
L1
0.05
0.10
0.15
P1
1.40
1.45
1.50
P2
4.15
4.20
4.25
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.15
eee
—
—
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
48
Rev. 0.3
Si823x
17. Land Pattern: 14 LD LGA with Thermal Pad
Figure 53 illustrates the recommended land pattern details for the Si8236 in a 14-pin LGA with thermal pad.
Table 26 lists the values for the dimensions shown in the illustration.
Figure 53. 14-Pin LGA with Thermal Pad Land Pattern
Rev. 0.3
49
Si823x
Table 26. 14-Pin LGA with Thermal Pad Land Pattern Dimensions
Dimension
(mm)
C1
4.20
C2
1.50
D2
4.25
E
0.65
X1
0.80
Y1
0.40
Notes:
General:
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05 mm.
Solder Mask Design:
4. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design:
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly:
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD020D specification for Small Body Components.
50
Rev. 0.3
Si823x
DOCUMENT CHANGE LIST
Revision 0.11 to Revision 0.2






Updated all specs to reflect latest silicon revision.
Updated Table 1 on page 6 to include new UVLO
options.
Updated Table 2 on page 10 to reflect new maximum
package isolation ratings
Added Figures 34, 35, and 36.
Updated Ordering Guide to reflect new package
offerings.
Added "5.6.3.Under Voltage Lockout (UVLO)" on
page 25 to describe UVLO operation.
Revision 0.2 to Revision 0.3

Moved Sections 2, 3, and 4 to after Section 5.
 Updated Tables 15, 16, and 17.
Removed
Si8230, Si8231, and Si8232 from pinout and
from title.

Updated and added Ordering Guide footnotes.
 Updated UVLO specifications in Table 1 on page 6.
 Added PWD and Output Supply Active Current
specifications in Table 1.
 Updated and added typical operating condition
graphs in "3.Typical Operating Characteristics
(0.5 Amp)" on page 16 and "4.Typical Operating
Characteristics (4.0 Amp)" on page 18.
Rev. 0.3
51
Si823x
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
52
Rev. 0.3