STK16CA8 128K x 8 AutoStorePlus™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM Preliminary FEATURES DESCRIPTION • 25ns, 35ns and 45ns Access Times • Directly Replaces 128K x 8 Static RAM, Battery-Backed RAM or EEPROM • Transparent Data Save on Power Down • STORE to QuantumTrap™ Nonvolatile Elements is Initiated by Software or AutoStorePlus™on Power Down • RECALL to SRAM Initiated by Software or Power Restore • 5mA Typical ICC at 200ns Cycle Time • Unlimited READ and WRITE Cycles to SRAM • 100-Year Data Retention to Quantum Trap • Single 3V +20%, -10% Operation • Commercial and Industrial Temperatures • 32-Pin DIP Package The Simtek STK16CA8 is a fast static RAM with a nonvolatile element in each static memory cell. The embedded nonvolatile elements incorporate Simtek’s QuantumTrap™ technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the nonvolatile elements. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) can take place automatically on power down or under software control. An internal capacitor guarantees the STORE operation, even under extreme power-down slew rates or loss of power from “hot swapping”. Transfers from the nonvolatile elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be controlled by entering control sequences on the SRAM inputs. The STK16CA8 is pin-compatible with 128k x 8 SRAMs and batterybacked SRAMs, allowing direct substitution while providing superior performance. BLOCK DIAGRAM PIN CONFIGURATIONS NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 ROW DECODER Quantum Trap 1024 x 1024 INPUT BUFFERS A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 POWER CONTROL STORE STATIC RAM ARRAY 1024 x 1024 RECALL COLUMN I/O STORE/ RECALL CONTROL SOFTWARE DETECT A0 - A15 COLUMN DEC A0 A1 A2 A3 A4 A10 A11 G E W September 2003 1 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 PIN NAMES A0 - A16 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable VCC Power (+ 3V) VSS Ground Document Control # ML0023 rev 0.1 STK16CA8 ABSOLUTE MAXIMUM RATINGSa Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.5V to +3.9V Voltage on Input Relative to VSS . . . . . . . . . .–0.5V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA (VCC = 3.0V +20%, -10%) DC CHARACTERISTICS SYMBOL COMMERCIAL PARAMETER MIN INDUSTRIAL MAX MIN MAX UNITS NOTES ICC b Average VCC Current 50 40 35 55 45 35 mA mA mA tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns ICC c Average VCC Current during STORE 1.5 1.5 mA All Inputs Don’t Care, VCC = max ICC b Average VCC Current at tAVAV = 200ns 3V, 25°C, Typical 5 5 mA W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels ISBd VCC Standby Current (Standby, Stable CMOS Input Levels) 1 1 mA E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) IILK Input Leakage Current ±1 ±1 µA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±1 ±1 µA VCC = max VIN = VSS to VCC, E or G ≥ VIH VIH Input Logic “1” Voltage 2.0 VCC + .3 2.0 VCC + .3 V All Inputs VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs VOH Output Logic “1” Voltage V IOUT = – 2mA VOL Output Logic “0” Voltage 0.4 V IOUT = 4mA TA Operating Temperature 85 °C 1 2 3 2.4 2.4 0.4 0 70 – 40 Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 Note c: ICC is the average current required for the duration of the STORE cycle (tSTORE ) . 2 Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEe SYMBOL PARAMETER (TA = 25°C, f = 1.0MHz) MAX UNITS CONDITIONS CIN Input Capacitance 5 pF ∆V = 0 to 3V COUT Output Capacitance 7 pF ∆V = 0 to 3V 3.0V 577 Ohms Note e: These parameters are guaranteed but not tested. OUTPUT 789 Ohms 30 pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading September 2003 2 Document Control # ML0023 rev 0.1 STK16CA8 SRAM READ CYCLES #1 & #2 NO. SYMBOLS #1, #2 (VCC = 3.0V +20%, -10%) PARAMETER Alt. STK16CA8-25 STK16CA8-35 STK16CA8-45 MIN MIN MIN MAX MAX 25 tELQV tACS Chip Enable Access Time 2 tAVAVf tRC Read Cycle Time 3 tAVQVg tAA Address Access Time 25 35 45 ns 4 tGLQV tOE Output Enable to Data Valid 10 15 20 ns 5 tAXQXg tOH Output Hold after Address Change 3 3 3 6 tELQX tLZ Chip Enable to Output Active 3 3 3 7 tEHQZh tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 35 45 10 0 9 tGHQZh tOHZ Output Disable to Output Inactive 10 tELICCHe tPA Chip Enable to Power Active 11 tEHICCLe tPS Chip Disable to Power Standby 45 UNITS 1 25 35 MAX 13 ns 0 10 0 ns 15 0 13 0 35 ns ns 15 ns 45 ns 0 25 ns ns ns Note f: W must be high during SRAM READ cycles. Note g: Device is continuously selected with E and G both low. Note h: Measured ± 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledf, g 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E Controlledf 2 tAVAV ADDRESS E 1 tELQV 6 11 tEHICCL tELQX 7 tEHQZ G 8 9 tGHQZ 4 tGLQV tGLQX DQ (DATA OUT) DATA VALID 10 tELICCH ACTIVE ICC September 2003 STANDBY 3 Document Control # ML0023 rev 0.1 STK16CA8 (VCC = 3.0V +20%, -10%) SRAM WRITE CYCLES #1 & #2 SYMBOLS NO. #1 #2 Alt. STK16CA8-25 PARAMETER MIN MAX STK16CA8-35 MIN MAX STK16CA8-45 MIN MAX UNITS 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 20 t WLQZ h, i tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write Note i: Note j: 0 0 10 3 13 3 ns 15 3 ns ns If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be ≥ VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledj 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN 16 tWHDX DATA VALID 20 tWLQZ DATA OUT 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA SRAM WRITE CYCLE #2: E Controlledj 12 tAVAV ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA OUT September 2003 16 tEHDX DATA VALID HIGH IMPEDANCE 4 Document Control # ML0023 rev 0.1 STK16CA8 MODE SELECTION E W G A15 - A0 (hex) MODE I/O POWER H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L 4E38 B1C7 83E0 7C1F 703F 8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Inhibit Output Data Output Data Output Data Output Data Output Data Output Data L 4E38 B1C7 83E0 7C1F 703F 4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore inhibit off Output Data Output Data Output Data Output Data Output Data Output Data L 4E38 B1C7 83E0 7C1F 703F 8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Output Data Output Data Output Data Output Data Output Data Output High Z L 4E38 B1C7 83E0 7C1F 703F 4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output Data Output Data Output Data Output High Z L L L L H H H H Active Active Active lCC NOTES k, l, m k, l, m k, l, m 2 Active k, l, m Note k: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note l: While there are 17 addresses on the STK16CA8, only the lower 16 are used to control software modes. Note m: I/O state depends on the state of G. The I/O table shown assumes G low. September 2003 5 Document Control # ML0023 rev 0.1 STK16CA8 (VCC = 3.0V +20%, -10%) AutoStorePlus™/POWER-UP RECALL NO. SYMBOLS Standard 22 tRESTORE 23 tSTORE 24 VSWITCH tHLHZ STK16CA8 PARAMETER Alternate MIN MAX UNITS NOTES Power-up RECALL Duration 5 ms n STORE Cycle Duration 10 ms o 2.65 V Low Voltage Trigger Level 2.55 Note n: tRESTORE starts from the time VCC rises above VSWITCH. Note o: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place. AutoStorePlus™/POWER-UP RECALL VCC 24 VSWITCH AutoStore™ 23 tSTORE POWER-UP RECALL 22 tRESTORE W DQ (DATA OUT) POWER-UP RECALL BROWN OUT NO STORE (NO SRAM WRITES) BROWN OUT AutoStore™ BROWN OUT AutoStore™ RECALL WHEN VCC RETURNS ABOVE VSWITCH September 2003 6 Document Control # ML0023 rev 0.1 STK16CA8 SOFTWARE-CONTROLLED STORE/RECALL CYCLEp NO. SYMBOLS STK16CA8-25 PARAMETER Alternate (VCC = 3.0V +20%, -10%) MIN MAX STK16CA8-35 MIN STK16CA8-45 MAX MIN G cont 25 tAVAV tAVAV tRC STORE/RECALL Initiation Cycle Time 25 35 45 ns 26 tAVEL tAVGL tAS Address Set-up Time 0 0 0 ns 27 tELEH tGLGH tCW Clock Pulse Width 20 25 30 ns 28 tELAX tGLAX Address Hold Time 20 29 tRECALL tRECALL RECALL Duration 20 MAX UNITS NOTES E cont 20 20 20 q ns 20 µs Note p: The software sequence is clocked with E controlled READs or G controlled READs. Note q: The six consecutive addresses must be in the order listed in the Mode Selection Table: (4E38, B1C7, 83E0, 7C1F, 703F, 8FC0) for a STORE cycle or (4E38, B1C7, 83E0, 7C1F, 703F, 4C63) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDq 25 25 tAVAV ADDRESS tAVAV ADDRESS #1 26 ADDRESS #6 27 tAVEL tELEH E 28 tELAX G 29 / tRECALL 23 tSTORE DQ (DATA) DATA VALID DATA VALID HIGH IMPEDANCE SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDq 25 25 tAVAV ADDRESS tAVAV ADDRESS #1 ADDRESS #6 E 26 tAVGL 27 tGLGH G 23 tSTORE 28 tGLAX DQ (DATA) September 2003 DATA VALID DATA VALID 7 29 / tRECALL HIGH IMPEDANCE Document Control # ML0023 rev 0.1 STK16CA8 DEVICE OPERATION The STK16CA8 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to the nonvolatile elements (the STORE operation) or from the nonvolatile elements to SRAM (the RECALL operation). In this mode SRAM functions are disabled. one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. POWER-UP RECALL During power up, or after any low-power condition (VCCX < VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. SRAM READ The STK16CA8 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-16 determines which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until new output data appears or until E or G is brought high, or W is brought low. If the STK16CA8 is in a WRITE state at the end of power-up RECALL, the WRITE will be inhibited and E or W must be brought high and then low for a write to initiate. SOFTWARE NONVOLATILE STORE The STK16CA8 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. 1. 2. 3. 4. 5. 6. AutoStorePlus™ OPERATION The STK16CA8’s automatic STORE on power-down is completely transparent to the system. The AutoStore™ initiation takes less than 500ns when power is lost (VCC < VSWITCH) at which point the part depends only on its internal capacitor for STORE completion. 4E38 (hex) B1C7 (hex) 83E0 (hex) 7C1F (hex) 703F (hex) 8FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, and it is necessary that G be low for the sequence to be In order to prevent unneeded STORE operations, automatic STOREs will be ignored unless at least September 2003 Read address Read address Read address Read address Read address Read address 8 Document Control # ML0023 rev 0.1 STK16CA8 valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. sequence has been performed, regardless of device power cycles. The AutoStore Inhibit can be disabled by initiating an AutoStore Inhibit Off sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Inhibit Off sequence, the following sequence of E controlled read operations must be performed: SOFTWARE NONVOLATILE RECALL A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 4E38 (hex) B1C7 (hex) 83E0 (hex) 7C1F (hex) 703F (hex) 4C63 (hex) 1. 2. 3. 4. 5. 6. Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle Read address Read address Read address Read address Read address Read address 4E38 (hex) B1C7 (hex) 83E0 (hex) 7C1F (hex) 703F (hex) 4B46 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Inhibit Off LOW AVERAGE ACTIVE POWER Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. The STK16CA8 draws significantly less current when it is cycled at times longer than 50ns. Figure 3 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Figure 4 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK16CA8 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading. HARDWARE PROTECT The STK16CA8 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCCX < VSWITCH, all externally initiated STORE operations and SRAM WRITEs will be inhibited. PREVENTING STORES The AutoStore™ function can be disabled on the fly by initiating an AutoStore Inhibit sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Inihibit sequence, the following sequence of E controlled read operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 4E38 (hex) B1C7 (hex) 83E0 (hex) 7C1F (hex) 703F (hex) 8B45 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Inhibit Once the AutoStore™ inhibit has been initiated, it will remain active until an AutoStore™ inhibit off September 2003 9 Document Control # ML0023 rev 0.1 50 50 40 40 Average Active Current (mA) Average Active Current (mA) STK16CA8 30 20 TTL 10 30 TTL 20 CMOS 10 CMOS 0 0 50 100 150 Cycle Time (ns) 50 200 200 Figure 4: Icc (max) Writes Figure 3: Icc (max) Reads September 2003 100 150 Cycle Time (ns) 10 Document Control # ML0023 rev 0.1 STK16CA8 ORDERING INFORMATION STK16CA8 - W F 45 I Temperature Range Blank = Commercial (0 to 70°C) I = Industrial (-40 to 85°C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Lead Finish Blank = 85%Sn/15%Pb F = 100% Sn (Matte Tin) Package W = Plastic 32-pin 600 mil DIP September 2003 11 Document Control # ML0023 rev 0.1 STK16CA8 Document Revision History Date Revision Summary 0.0 May 2003 Publish new datasheet 0.1 September 2003 Added lead-free lead finish September 2003 12 Document Control # ML0023 rev 0.1