74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 D Inputs Are TTL-Voltage Compatible D Asynchronous Clear D Fully Independent Clock Circuit Simplifies D D D D DW PACKAGE (TOP VIEW) QA QB QC QD QE GND GND GND GND QF QG QH RCO CLK Use Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC™ (Enhanced-Performance Implanted CMOS) 1-μm Process 500-mA Typical Latch-Up Immunity at 125°C description 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 A B C D E F VCC VCC G H ENP ENT S0 S1 15 The 74ACT11867 is a synchronous presettable binary counter featuring an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform. 14 The counters are fully programmable; that is, the outputs can each be preset to either logic level. The load-mode circuitry allows parallel loading of the cascaded counters. As loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock rising edge. The carry look-ahead circuitry is provided for cascading counters for n-bit synchronous applications without additional gating. This is done with two count-enable inputs and a carry output. Both count-enable (ENP and ENT) inputs must be low to count. The direction of the count is determined by the levels of the select (S0 and S1) inputs (see the function table). Input ENT is fed forward to enable the ripple-carry (RCO) output. RCO then produces a low-level pulse while the count is zero (all outputs low) when counting down or 255 during counting up (all outputs high). This low-level overflow carry pulse can be used to enable successive cascaded stages. Transitions at ENP and ENT are allowed regardless of the level of the clock input. These counters feature a fully independent clock circuit. Whenever ENP and/or ENT is taken high, RCO either goes high or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The 74ACT11867 is characterized for operation from −40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright © 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 MODE FUNCTION TABLE S1 S0 FUNCTION L L Clear Count down L H H L Load H H Count up logic symbol† S0 S1 ENT 16 15 17 18 ENP CLK A B C D E F G H † 2 14 28 CTRDIV256 0 1 M 0 3 1,4,5CT = 0 G4 3,4,5CT = 255 G5 0 13 RCO C6/1,4,5−/3,4,5+ 0R 1 2,6D 27 2 26 3 25 4 24 5 23 10 20 11 19 12 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QA QB QC QD QE QF QG QH 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 logic diagram (positive logic) CLK S0 S1 ENP 14 16 15 18 28 1D C1 R 1 1D C1 R 2 B 27 1D C1 R 3 C 26 25 1D C1 R 4 24 1D C1 R 5 23 1D C1 R 10 20 1D C1 R 11 QG 19 1D C1 R 12 QH A D E F G H 13 ENT QA QB QC QD QE QF RCO 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 output sequence S1 S0 A B C D Data Inputs E F G H CLK ENP ENT QA QB QC QD Outputs QE QF QG QH RCO 253 254 255 0 Count Up 1 2 1 0 255 254 253 252 Count Down Async Preset Clear Outputs to 252 † 4 ENT and ENP must both be low for counting to occur. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Inhibit† 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±225 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH IOL Δt/Δv Input transition rise or fall rate TA Operating free-air temperature MIN NOM MAX 4.5 5 5.5 2 UNIT V V 0.8 V 0 VCC V 0 VCC V High-level output current −24 mA Low-level output current 24 mA 0 10 ns/V −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = −50 50 μA A VOH IOH = −24 mA IOH = −75 mA† TYP MAX 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 5.5 V 4.94 4.8 MAX V 0.1 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 IOL = 75 mA† 5.5 V II VI = VCC or GND 5.5 V ICC VI = VCC or GND, IO = 0 ΔICC‡ One input at 3.4 V, Other inputs at VCC or GND Ci VI = VCC or GND UNIT 3.85 4.5 V IOL = 24 mA MIN 4.5 V 5.5 V IOL = 50 μA A VOL TA = 25°C MIN V 1.65 ±0.1 ±1 5.5 V 8 80 μA 5.5 V 0.9 1 mA 5V 4.5 μA pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V . CC timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C fclock tw tsu Clock frequency Pulse duration § th tskew Setup time before CLK↑ Hold time after CLK↑ Skew time between S0 and S1 to avoid inadvertent MAX 0 70 MIN MAX UNIT 0 70 MHz S0 and S1 low 12 12 CLK 6.5 6.5 Data 8 8 ENP, ENT 4 4 S0, S1 (load) 11 11 S0, S1 (count down) 11 11 S0, S1 (count up) 11 11 1 1 Data clear¶ MIN S0 and S1 low § 0 ns ns ns 0 ns This setup time is required to ensure stable data. ¶ This is the maximum time for which S0 and S1 can be low simultaneously when the device transitions between the load (S1 = H, S0 = L) and count-down (S1 = L, S0 = H) modes. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX MIN MAX fmax 70 tPLH 6 9.9 12.7 6 14.6 6.4 10.9 14.2 6.4 16.3 CLK RCO CLK Q ENT RCO tPHL Clear (S0, S1 low) tPLH tPHL tPLH 70 UNIT MHz ns 5 8.9 11.9 5 13.6 4.9 9 12.2 4.9 14 3.9 6.8 9.1 3.9 10.5 3.1 7 10.2 3.1 11.5 Q 6.3 11.9 16.6 6.3 19.1 ns S0, S1 (count up/down) RCO 55 5.5 10 4 10.4 15 15.6 6 5 5.5 5 17 8 17.8 ns tPHL S0, S1 (count up/down) RCO 56 5.6 10 1 10.1 14 14.8 8 5 5.6 6 17 2 17.2 ns tPHL Clear (S0, S1 low) RCO 6.2 11.3 15.6 6.2 17.8 ns TYP UNIT tPHL tPLH tPHL ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 62 pF 7 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 50 pF (see Note A) 3V 500 Ω Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS LOAD CIRCUIT 3V Input (see Note B) 3V Timing Input (see Note B) 0V tsu Data Input 1.5 V 0V tPHL tPLH 1.5 V th 1.5 V In-Phase Output 50% VCC 3V 1.5 V tPLH tPHL 1.5 V 0V Out-of-Phase Output VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 7-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 74ACT11867DW OBSOLETE SOIC DW 28 TBD Call TI Call TI Samples Not Available 74ACT11867DWR OBSOLETE SOIC DW 28 TBD Call TI Call TI Samples Not Available 74ACT11867NT OBSOLETE PDIP NT 28 TBD Call TI Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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