TI 74CB3Q3306ADCURE4

SN74CB3Q3306A
www.ti.com
SCDS113E – DECEMBER 2002 – REVISED JANUARY 2011
Dual FET Bus Switch 2.5-V/3.3-V Low-Voltage High-Bandwidth Bus Switch
Check for Samples: SN74CB3Q3306A
FEATURES
•
1
•
•
•
•
•
•
•
(1)
(1)
High-Bandwidth Data Path (up to 500 MHz )
5-V-Tolerant I/Os With Device Powered Up or
Powered Down
Low and Flat ON-State Resistance (ron)
Characteristics Over Operating Range
(ron = 4 Ω Typ)
Rail-to-Rail Switching on Data I/O Ports
– 0- to 5-V Switching With 3.3-V VCC
– 0- to 3.3-V Switching With 2.5-V VCC
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 3.5 pF Typ)
Fast Switching Frequency (f OE = 20 MHz Max)
For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI application
report, CBT-C, CB3T, and CB3Q Signal-Switch Families,
literature number SCDA008.
•
•
•
•
•
•
•
•
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption (ICC = 0.25 mA Typ)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0- to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Supports Both Digital and Analog
Applications: USB Interface, Differential Signal
Interface, Bus Isolation, Low-Distortion Signal
Gating
PW PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
1OE
1A
1B
GND
1
2
3
8
7
6
4
5
VCC
2OE
2B
2A
1OE
1A
1B
GND
1
8
2
7
3
6
4
5
VCC
2OE
2B
2A
ORDERING INFORMATION
PACKAGE (1)
TA
TSSOP – PW
–40°C to 85°C
US8-DCU
(1)
(2)
ORDERABLE PART NUMBER
Tube
SN74CB3Q3306APW
Tape and reel
SN74CB3Q3306APWR
Tape and reel
SN74CB3Q3306ADCUR
74CB3Q3306ADCURE4
TOP-SIDE MARKING
BU306A
GA6R (2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
The last character designates assembly/test site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2011, Texas Instruments Incorporated
SN74CB3Q3306A
SCDS113E – DECEMBER 2002 – REVISED JANUARY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION/ORDERING INFORMATION
The SN74CB3Q3306A is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows
for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device
also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.
Specifically designed to support high-bandwidth applications, the SN74CB3Q3306A provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
The SN74CB3Q3306A is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can
be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is
ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high,
the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Table 1. FUNCTION TABLE
(EACH BUS SWITCH)
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
2
1A
1OE
3
1B
SW
1
5
2A
6
SW
2B
7
2OE
2
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Product Folder Link(s) :SN74CB3Q3306A
SN74CB3Q3306A
www.ti.com
SCDS113E – DECEMBER 2002 – REVISED JANUARY 2011
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
B
A
VCC
Charge
Pump
EN(1)
(1) EN is the internal enable signal applied to the switch.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VIN
Control input voltage range (2)
(3)
(2) (3) (4)
MIN
MAX
–0.5
4.6
V
–0.5
7
V
VI/O
Switch I/O voltage range
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
±64
mA
±100
mA
II/O
ON-state switch current
–0.5
7
UNIT
(5)
Continuous current through each VCC or
GND
qJA
Package thermal impedance (6)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(5)
(6)
DCU
TBD
PW
88
–65
150
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
MIN MAX
VCC
Supply voltage
VIH
High-level control input
voltage
VIL
Low-level control input
voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
UNIT
2.3
3.6
V
VCC = 2.3 V to 2.7 V
1.7
5.5
VCC = 2.7 V to 3.6 V
2
5.5
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
–40
85
°C
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Copyright © 2002–2011, Texas Instruments Incorporated
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3
SN74CB3Q3306A
SCDS113E – DECEMBER 2002 – REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
MIN TYP (2)
TEST CONDITIONS
VCC = 3.6 V,
II = –18 mA
VCC = 3.6 V,
VIN = 0 to 5.5 V
VCC = 3.6 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0
ICC
VCC = 3.6 V,
II/O = 0,
Switch ON or OFF,
VIN = VCC or GND
Other inputs at VCC or GND
IIN
IOZ
Control inputs
(3)
MAX
UNIT
–1.8
V
±1
mA
±1
mA
1
mA
0.7
mA
25
mA
0.03
0.1
mA/
MHz
2.5
3.5
pF
0.25
ΔICC
(4)
Control inputs
VCC = 3.6 V,
One input at 3 V,
ICCD
(5)
Per control
input
VCC = 3.6 V,
A and B ports open,
Control inputs
VCC = 3.3 V,
VIN = 5.5 V, 3.3 V, or 0
Cio(OFF)
VCC = 3.3 V,
Switch OFF,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
3.5
5
pF
Cio(ON)
VCC = 3.3 V,
Switch ON,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
8
10.5
pF
VI = 0,
IO = 30 mA
4
8
VI = 1.7 V,
IO = –15 mA
5
9
VI = 0,
IO = 30 mA
4
6
VI = 2.4 V,
IO = –15 mA
5
8
Cin
ron
Control input switching at 50% duty cycle
VCC = 2.3 V,
TYP at VCC = 2.5 V
(6)
VCC = 3 V
(1)
(2)
(3)
(4)
(5)
(6)
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 2).
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
f OE
4
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
UNIT
MAX
OE
A or B
10
20
MHz
A or B
B or A
0.2
0.2
ns
ten
OE
A or B
1.5
6.5
1.5
5.5
ns
tdis
OE
A or B
1
6
1
5
ns
tpd
(1)
(2)
(1)
FROM
(INPUT)
(2)
Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0)
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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Product Folder Link(s) :SN74CB3Q3306A
SN74CB3Q3306A
www.ti.com
SCDS113E – DECEMBER 2002 – REVISED JANUARY 2011
TYPICAL ron vs VI
ron − ON-State Resistance − Ω
16
VCC = 3.3 V
TA = 25°C
IO = −15 mA
14
12
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
18
20
VI − V
Figure 1. Typical ron vs VI
TYPICAL ICC
vs
OE SWITCHING FREQUENCY
12
VCC = 3.3 V
TA = 25°C
A and B Ports Open
ICC − mA
10
8
6
4
2
One OE Switching
0
0
2
4
6
8
10
12
14
16
OE Switching Frequency − MHz
Figure 2. Typical ICC vs OE Switching Frequency
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5
SN74CB3Q3306A
SCDS113E – DECEMBER 2002 – REVISED JANUARY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
VI
S1
RL
VO
50 Ω
50 Ω
VG2
RL
CL
(see Note A)
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
VCC or GND
VCC or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
GND
GND
500 Ω
500 Ω
VCC
VCC
30 pF
50 pF
0.15 V
0.3 V
V∆
VCC
Output
Control
(VIN)
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VCC
VCC/2
VCC/2
VOL
VOL + V∆
VOL
tPZH
tPHL
VCC/2
0V
tPZL
Output
Control
(VIN)
Open
GND
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
tPHZ
VOH
VCC/2
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
6
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SN74CB3Q3306A
www.ti.com
SCDS113E – DECEMBER 2002 – REVISED JANUARY 2011
REVISION HISTORY
Changes from Revision D (April 2005) to Revision E
•
Page
Added DCU package ordering information. .......................................................................................................................... 1
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7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74CB3Q3306ADCURE4
ACTIVE
US8
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GA6R
74CB3Q3306ADCURG4
ACTIVE
US8
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GA6R
74CB3Q3306APWRE4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU306A
SN74CB3Q3306ADCUR
ACTIVE
US8
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(A6 ~ GA6R)
GZ
SN74CB3Q3306APW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU306A
SN74CB3Q3306APWE4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU306A
SN74CB3Q3306APWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU306A
SN74CB3Q3306APWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
BU306A
SN74CB3Q3306APWRE4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU306A
SN74CB3Q3306APWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU306A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74CB3Q3306ADCURG4
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
US8
DCU
8
3000
180.0
SN74CB3Q3306ADCUR
US8
DCU
8
3000
SN74CB3Q3306APWR
TSSOP
PW
8
2000
B0
(mm)
K0
(mm)
P1
(mm)
8.4
2.25
3.35
1.05
4.0
180.0
9.0
2.05
3.3
1.0
330.0
12.4
7.0
3.6
1.6
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Nov-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74CB3Q3306ADCURG4
US8
DCU
8
3000
202.0
201.0
28.0
SN74CB3Q3306ADCUR
US8
DCU
8
3000
182.0
182.0
20.0
SN74CB3Q3306APWR
TSSOP
PW
8
2000
364.0
364.0
27.0
Pack Materials-Page 2
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www.ti.com/audio
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Computers and Peripherals
www.ti.com/computers
DLP® Products
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Logic
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Microcontrollers
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RFID
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www.ti.com/omap
TI E2E Community
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Wireless Connectivity
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