SITRONIX ST3020

ST3020
Audio Decoder/ Encoder
P r e l i m i n a r y
Datasheet
Version 0.1
2007/06/20
Note: Sitronix Technology Corp. reserves
the right to change the contents in this
document without prior notice. This is not
a final specification. Some parameters
are subject to change
ST3020
1
FEATURES
n DSP based voice/audio processor
n Operation voltage
n Speech playback/recorder
_ Low Bit Rate Compression (LBRC)
_ 1.2K/1.6K/2.4Kbps@8KHz playback
_ 1.6K/2.2K/[email protected] playback
_ AB-repeat
_ Time stretch (speed up x 2, speed down x
2)
_ Combine syllable
_ Encryption
_ Audio Playback (CBR, VBR – all bit rates)
_ Forward/backward play, AB-repeat
_ Spectrum gain
_ Time stretch (speed up x 1.5, speed down x
1.5)
_ Combine syllable
_ Encryption
_ Wav Playback
_ Forward/backward play, AB-repeat
_ Wav Record {(MS-ADPCM(3.8:1)}
_ Software AGC
_ Motion-JPEG playback
_ JPEG-baseline decoder
– Core logic: 2.25V~2.7V
– I/O pads: 3.0V~3.6V
n Voltage regulator for core logic
n Low Voltage Reset (LVR)
_ 2.5V low voltage reset
n One PLL to generate high system
frequency from a 3MHz source
_ 12M~30MHz PLL output
n Triple clock sources
_ Crystal......................................3MHz
_ External input...… … … … … ......3MHz
n Low power down current
_Typical current: 3uA
n One 16-bit programmable Timer
n One clocking output
n One external interrupt
_ Edge/level trigger supported
n One 14-bit direct-drive DAC
– Maximum current: 145mA
n MCU interfaces
_ Parallel mode
n Two Serial PORT interfaces(SP)
_ Programmable data length from 8-bit to
16-bit
_ I2S, Left/Right Justified interfaces to
external DAC/ADC
2
GENERAL DESCRIPTION
The ST3020 is a highly integrated and cost-effective DSP based audio processor for various
consumer applications. It consists of one powerful DSP for advanced voice decoder and encoder
algorithms of natural speech with less memory. It provides low bit rate compression (LBRC) for voice
playback, audio playback, motion-JPEG playback, and JPEG-baseline decoder.
System clock comes from 3MHz crystal or external input.
ST3020 has 32 I/Os and these can be either GPIO or functional pins. Each pin can be programmed
to input or output. One external interrupt pin can be requested by external devices.
One internal 16-bit DAC can provide significant volume equipping with internal amplifier. For
particular application or recorder, two general audio interfaces are supported to interface with
external DAC/ADC. Audio interface can be configured to I2S or Left/Right Justified compatible
mode.
There are parallel interface to connect with different MCUs.
Preliminary Ver 0.1
Page 2/13
2007/06/20
ST3020
2.1
Block Diagram
VDD33
VSS33
VDD33
VSS33
VDD25
VSS25
VDD25
VSS25
REGVDD33
REGVSS33
VREF
VCCOUT
DPA0/TF0
DPA1/RF0
DPA2/TX0
DPA3/RX0
DPA4/SCLK0
DPA8/TF1
DPA9/RF1
DPA10/TX1
DPA11/RX1
DPA12/SCLK1
Parallel
Power
MCU
Interface
2.5V
Regulator
SP0
16-Bit DAC
SP1
DSP Core
PWD
PWDA
Power Down
Controller
DPA[14:13]
DPB[15:0]
General IO
TEST[2:0]
Test Mode
Circuit
OSCXI
OSCXO
ECLK
CMODE[1:0]
PLLVDD25
PLLVSS25
PLLVDD25A
PLLVSS25A
ROM
Clock
Generator
RDY
REQ
CS
P/S
DACO
DACO
DACOB
DACOB
DACOVDD33A
DACOVDD33A
DACOVSS33A
DACOVSS33A
DACVDD33A
DACVSS33A
VCM
RESET
External
Interrupt
XREQ/DPA5
Clock out
generator
CLKO/DPA6
Special I/O
SO0/DPA7
SO1/DPA15
RAM
Timer
PLL
Figure 2-1
Preliminary Ver 0.1
LVR
D[3:7]
RD
WR
CMD
PMODE
ST3020 Block Diagram
Page 3/13
2007/06/20
ST3020
3
SIGNAL DESCRIPTIONS
Table 3-1
Function
Group
System control
Special I/O
GPIO
External
Interrupt
Serial Port0/
DPA[4:0]
Serial Port1/
DPA[12:8]
MCU Interface
Preliminary Ver 0.1
Signal Function Description
Pin Name
Pin #
I/O
Description
RESET
PWD
PWDA
1
1
1
I
I
O
OSCXI
1
I
OSXO
ECLK
1
1
O
I
CMODE[1:0]
2
I
TEST[2:0]
SO[1:0]/
DPA[7,15]
CLKO/
DPA[6]
DAP[13,14],
DPB[0:15]
3
I
2
O
System reset, low active
Power down, low active
Power down acknowledge, high active
Crystal input or R-oscillator input. If not used, it connects to
GND
Crystal output. If not used, it connects to GND
External clock input. If not used, it connects to GND
Clock source select
01=Crystal. ECLK connects to GND
1X=ECLK. OSCXI and OSXO connect to GND
Test mode. TEST[2:0] connect to GND
SO0/DPA[7], SO1/DPA[15]
1
O
18
I/O
XREQ/DPA[5]
1
I
TF0/DPA[0]
RF0/DPA[1]
TX0/DPA[2]
RX0/DPA[3]
SCLK0/DPA[4]
TF1/DPA[8]
RF1/DPA[9]
TX1/DPA[10]
RX1/DPA[11]
SCLK1/DPA[12]
D[0]/SCL
D[1]/SDI
D[2]/SDO
D[3:7]
1
1
1
1
1
1
1
1
1
1
1
1
1
5
O
I
O
I
O
O
I
O
I
O
I/O
I/O
I/O
I/O
WR
1
I
Parallel : Write enable, low active
RD
1
I
Parallel : Read enable, low active
CS
1
I
Parallel : Chip select, low active
CMD
1
I
REQ
1
O
Parallel : Command/data select
“H”: Data
“L”: Command
DSP wants to sent command to MCU, low active
RDY
1
O
DSP permit MCU access data, low active, not used
PMODE
1
I
Parallel interface select
0: Parallel (default). Connecting to GND
1: Not used
Clock output/DPA[6]
General I/O
External interrupt/DPA[5]
Transmit frame synchronization/DPA[0]
Receive frame synchronization/DPA[1]
Serial data transmit/DPA[2]
Serial data receive/DPA[3]
Serial clock/DPA[4]
Transmit frame synchronization/DPA[8]
Receive frame synchronization/DPA[9]
Serial data transmit/DPA[10]
Serial data receive/DPA[11]
Serial clock/DPA[12]
Parallel : Data bus
Parallel : Data bus
Parallel : Data bus
Parallel : Data bus
Page 4/13
2007/06/20
ST3020
Power
Regulator
DAC
Preliminary Ver 0.1
P/S
1
I
VDD25
VSS25
VDD33
VSS33
REGVDD33
REGVSS33
PLLVDD25
PLLVSS25
PLLVDD25A
PLLVSS25A
DACVDD33A
DACVSS33A
DACOVDD33A
DACOVSS33A
VCCOUT
VREF
DACO
DACOB
VCM
2
2
2
2
1
1
1
1
1
1
1
1
2
2
1
1
2
2
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
Parallel/serial interface select
0: Not used
1: Parallel. Connect to VDD33.
2.5V power
2.5V power ground
3.3V power
3.3V power ground
Digital power input of regulator
Digital power ground of regulator
Digital power input of PLL
Digital power ground of PLL
Analog power input of PLL
Analog power ground of PLL
Analog power input of DAC
Analog power ground of DAC
Analog power input of DAC output stage
Analog power ground of DAC output stage
2.5V output of regulator
Voltage reference
DAC direct drive pin(+)
DAC direct drive pin(-)
Common mode voltage reference
Page 5/13
2007/06/20
ST3020
4
ELECTRICAL CHARACTERISTICS
4.1
Absolute Maximum Rations
*Note: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. All the ranges are stress ratings only.
Functional operation of this device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied or intended. Exposed to the absolute
maximum rating conditions for extended periods
may affect device reliability.
DC Supply Voltage: VDD33 ----------- -0.3V to +4.5V
Operating Ambient Temperature ---- -10°C to +60°C
Storage Temperature ------------------- -10°C to +125°C
4.2
DC Electrical Characteristics
Table 4-1
DC Electrical Characteristics
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25°C, unless otherwise specified
Parameter
Symbol
Min.
Operating Voltage
VDD33
3.0
Operating Voltage
VDD25
2.25
Operating Current
IOP1
30
Power Down Current
IPD
3
Output driving
Iod
16
mA
Output sinking
Ios
26
mA
Input low voltage
VIL
0.6
V
Input high voltage
VIH
1.3
V
Pull-up resistor
RPU
54
KΩ
Pull-down resistor
RPD
50
KΩ
Low Voltage Reset Level
VLVR
Preliminary Ver 0.1
2.4
Typ.
2.5
2.5
Page 6/13
Max.
Unit
3.6
V
2.7
V
mA
4.5
2.6
Condition
Run at 24MHz without speaker
mA
V
2007/06/20
ST3020
4.3
AC Electrical Characteristics
Figure 4-1
Parallel Interface Timing Diagram
Table 4-2
Timing parameters for Figure 4-1
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25°C
Symbol
Characteristic
tCH
tCS
tCYC
tCCLW
tCCHW
tCCLR
tCCHR
tDS
tDH
tACC
tOH
Cmd pin hold time
Cmd pin setup time
System cycle time
Write pulse width
Enable H write width
Read pulse width
Enable H read width
Write data setup time
Write data hold time
Read access time
Read data disable time
Rating
Min.
Typ.
Max.
5
5
3.5D
0.5D
3D
0.5D
3D
0.5D
5
25
4
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Remark: D = time of one DSP system clock
Preliminary Ver 0.1
Page 7/13
2007/06/20
ST3020
5
PAD DIAGRAM
Preliminary Ver 0.1
Page 8/13
2007/06/20
ST3020
6
DEVICE INFORMATION
Substrate:
PAD
Symbol
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TF0
RF0
TX0
RX0
SCLK0
XREQ
CLKO
SO0
TF1
RF1
TX1
RX1
SCLK1
DPA13
DPA14
SO1
VDD25
VSS25
TEST2
TEST1
TEST0
VSS33
VDD33
DPB0
DPB1
DPB2
DPB3
DPB4
DPB5
DPB6
GND
X
Y
PAD
Symbol
No.
X
Y
1616.23
1716.23
1816.23
1916.23
2016.23
2116.23
2216.23
2316.23
2416.23
2516.23
2616.23
2716.23
2826.23
2936.23
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
406.55
516.55
626.55
736.55
836.55
936.55
1036.55
1136.55
1236.55
1336.55
1436.55
1536.55
1636.55
1736.55
1836.55
1936.55
31 DPB7
32 DPB8
33 DPB9
34 DPB10
35 DPB11
36 DPB12
37 DPB13
38 DPB14
39 DPB15
40 VSS33
41 VDD33
42 PWDA
43
PWD
44
D7
45
D6
46
D5
47
D4
48
D3
49
SDO
50
SDI
51
SCL
52 VDD25
53 VSS25
54
CMD
55 PMODE
56
REQ
57
RDY
58
WR
59
RD
60
CS
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2977.5
2940
2830
2720
2620
2520
2420
2320
2220
2120
2020
1920
1820
1720
1620
1520
1420
1320
1220
1120
1020
920
820
2036.55
2136.55
2236.55
2336.55
2436.55
2546.55
2656.55
2766.55
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
Preliminary Ver 0.1
Page 9/13
PAD
No.
Symbol
X
Y
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
P/S
RESET
CMODE0
CMODE1
OSCXI
OSXO
ECLK
VREF
VCCOUT
REGVDD33
REGVSS33
PLLVSS25
PLLVDD25
PLLVSS25A
PLLVDD25A
DACVSS33
DACVDD33
VCM
DACOB
DACOB
DACOVSS3
DACOVSS3
DACOVDD3
DACOVDD3
DACO
DACO
720
620
520
420
320
210
100
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
3107.5
2753.0
2643.0
2533.0
2433.0
2257.0
2157.0
2057.0
1957.0
1781.0
1681.0
1581.0
1481.0
1381.0
1281.0
1181.0
1081.0
981.04
881.04
781.04
2007/06/20
WR
220
WR
RD
220
RD
CS
220
220
GPIO
D0~7
A0/
GPIO
GPIO
OSCN
Figure 7-1
CSn
ST3020
CMD
7.1
P/S
APPLICATION CIRCUIT
SO1
PWD
PWDA
RESET
ECLK
OSCXI
OSXO
CMODE[1:0]
PMODE
7
REQ
D7~0
ST3020
Application Circuit Diagram
Note:
1. If any of OSCXI, OSXO, and ECLK is not used, it needs to connect to GND.
2. The cascade resistor and parallel capacitor on CMD, RD, WR, and CS pins can reduce noise
interference. In general, resistor is short and capacitor is open. Please preserve the options on
PCB.
Preliminary Ver 0.1
Page 10/13
2007/06/20
ST3020
7.2
ADC
10K
10K
1.2K
1.5K
2K
Figure 7-2
Preliminary Ver 0.1
ADC Application Circuit Diagram
Page 11/13
2007/06/20
ST3020
7.3
DAC
Figure 7-3
Preliminary Ver 0.1
DAC Application Circuit Diagram
Page 12/13
2007/06/20
ST3020
8
REVISION
REVISION
0.1
DESCRIPTION
PAGE
First release
DATE
2007/06/20
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or
reproduced without permission from Sitronix. Sitronix Technology Corp. reserves the right to change this document without prior notice
and makes no warranty for any errors which may appear in this document. Sitronix products are not intended for use in life support,
critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or
physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
Preliminary Ver 0.1
Page 13/13
2007/06/20