SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993
•
•
•
•
•
•
•
•
DW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Independent Registers A and B Buses
Multiplexed Real-Time and Stored Data
Inverting Data Paths
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
G
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
DIR
description
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
CAB
SAB
B1
B2
B3
B4
VCC
VCC
B5
B6
B7
B8
CBA
SBA
The 74ACT11648 consists of bus transceiver
circuits with 3-state outputs, D-type flip-flops, and
control circuitry arranged for multiplexed transmission of data directly from the data bus or from
the internal storage registers. Data on the A or B bus will be clocked into the registers on the low-to-high
transition of the appropriate clock pin (CAB or CBA). Examples of the four fundamental bus-management
functions that can be performed with the octal bus transceivers and registers are shown in Figure 1.
Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode,
data present at the high-impedance port may be stored in either register or in both. The select controls (SAB
and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for select control will
eliminate the typical decoding glitch that occurs in a mulitplexer during the transition between stored and
real-time data. The direction control determines which bus will receive data when enable G is active (low). In
the isolation mode (control G high), A data may be stored in one register and/or B data may be stored in the
other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74ACT11648 is characterized for operation from − 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2−1
1
14
28
16
27
15
1
14
28
16
27
15
G
DIR
CAB
CBA
SAB
SBA
G
DIR
CAB
CBA
SAB
SBA
L
X
X
X
L
L
H
X
X
L
X
REAL-TIME TRANSFER BUS A TO BUS B
BUS A
BUS B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
L
1
14
28
16
27
15
1
14
28
G
DIR
CAB
CBA
SAB
SBA
G
DIR
X
X
↑
X
X
X
L
L
X
X
X
↑
X
X
L
H
H
X
↑
↑
X
X
STORAGE FROM A, B, OR A AND B
POST OFFICE BOX 655303
16
27
15
CAB
CBA
SAB
SBA
X
H or L
X
H
H or L
X
H
X
TRANSFER STORED DATA TO A OR B
Figure 1. Bus-Management Functions
2−2
BUS B
BUS A
BUS B
BUS A
SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993
• DALLAS, TEXAS 75265
SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993
FUNCTION TABLE
INPUTS
DATA I/O
G
DIR
CAB
CBA
SAB
SBA
A1 THRU A8
X
X
↑
X
X
X
Input
B1 THRU B8
Unspecified†
OPERATION OR FUNCTION
X
X
X
↑
X
X
Unspecified†
Input
Store A, B unspecified†
Store B, A unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B Data
H
X
H or L
H or L
X
X
Input
Input
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H or L
X
H
Output
Input
Stored B Data to A Bus
L
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
L
H
H or L
X
H
X
Input
Output
Stored A Data to B Bus
† The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every low-to-high transition on the clock inputs.
logic symbol‡
1
G
14
DIR
16
CBA
15
SBA
28
CAB
27
SAB
A1
2
logic diagram (positive logic)
1
A2
A3
A4
A5
A6
A7
A8
1
1
14
DIR
CBA 16
SBA 15
CAB 28
27
SAB
26
≥1
6D
3
G
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
5
5
7
7
B1
4D
1
≥1
1 of 8
Channels
1D
C1
2
25
B2
4
24
5
23
10
20
11
19
12
18
13
17
A1
2
26
1D
C1
B3
B1
B4
B5
To Seven Other Channels
B6
B7
B8
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
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2−3
SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
Dt /Dv
Low-level output current
TA
Operating free-air temperature
2−4
High-level input voltage
2
High-level output current
Input transition rise or fall rate
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
V
0.8
V
VCC
VCC
V
−24
mA
V
24
mA
0
10
ns/ V
−40
85
°C
SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.5 V
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
IOH = − 24 mA
5.5 V
4.94
4.8
IOH = − 75 mA{
5.5 V
IOH = − 50 mA
A
VOH
IOL = 50 mA
A
VOL
II
IOZ
Control Inputs
A or B ports‡
ICC
DICC§
TA = 25°C
TYP
MAX
VCC
MIN
MAX
UNIT
V
3.85
4.5 V
0.1
0.1
5.5 V
0.1
0.1
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA{
5.5 V
VI = VCC or GND
VI = VCC or GND
5.5 V
± 0.1
±1
mA
5.5 V
± 0.5
±5
mA
5.5 V
8
80
mA
5.5 V
0.9
1
mA
VI = VCC or GND,
One input at 3.4 V,
IO = 0
Other inputs at GND or VCC
V
1.65
Ci
Control Inputs VI = VCC or GND
5V
4.5
Cio
A or B ports
VI = VCC or GND
5V
12
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended range of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
0
MAX
UNIT
0
75
MHz
fclock
tw
Clock frequency
6.7
6.7
ns
tsu
th
Setup time, A before CAB↑ or B before CBA↑
5
5
ns
Hold time, A after CAB↑ or B after CBA↑
2
2
ns
Pulse duration, CAB or CBA high or low
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
90
MIN
2−5
SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993
switching characteristics over recommended ranges of supply voltage operating free-air
temperature (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
MIN
75
A or B
B or A
tPZH
tPZL
G
A or B
tPHZ
tPLZ
G
A or B
tPLH
tPHL
CBA or CAB
A or B
tPLH
tPHL
SAB or SBA†
(with A or B high)
A or B
tPLH
tPHL
SBA or SAB†
(with A or B low)
A or B
tPZH
tPZL
DIR
A or B
tPHZ
tPLZ
DIR
A or B
MAX
75
UNIT
MHz
2.4
6.5
9.5
2.4
10.7
4.4
8.5
11.3
4.4
12.7
4.2
9.2
13
4.2
14.6
4.3
9.8
13.9
4.3
15.6
5.7
8.7
11.3
5.7
12.2
5.3
8.1
10.5
5.3
11.4
5.2
9.4
12
5.2
13.7
6
10.5
13.5
6
15.2
4.7
8.6
11.3
4.7
12.9
3.8
8.6
12
3.8
13.4
2.6
7.1
10.2
2.6
11.5
5.4
9.7
12.6
5.4
14.1
3.9
9.8
14.9
3.9
16.9
3.9
10.8
15.1
3.9
17.2
4.5
8.2
10.6
4.5
11.5
3.9
7.3
9.6
3.9
11.3
ns
ns
ns
ns
ns
ns
ns
ns
† These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
2−6
Power dissipation capacitance per transceivers
Outputs disabled
POST OFFICE BOX 655303
TYP
UNIT
61
CL = 50 pF,
• DALLAS, TEXAS 75265
f = 1 MHz
15
pF
SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH /tPHL
tPLZ /tPZL
tPHZ /tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
Timing Input
(see Note B)
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
3V
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note C)
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPLH
tPHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
50% VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2−7
SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993
2−8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
74ACT11648DW
OBSOLETE
SOIC
DW
28
TBD
Call TI
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74ACT11648DWR
OBSOLETE
SOIC
DW
28
TBD
Call TI
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74ACT11648DWR
OBSOLETE
SOIC
DW
28
TBD
Call TI
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74ACT11648NT
OBSOLETE
PDIP
NT
28
TBD
Call TI
Call TI
74ACT11648NT
OBSOLETE
PDIP
NT
28
TBD
Call TI
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(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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