SITRONIX ST7541

ST
Sitronix
ST7541
4 Gray Scale Dot Matrix LCD Controller/Driver
INTRODUCTION
ST7541 is a driver & controller LSI for 4-level gray scale graphic dot-matrix liquid crystal display systems. This chip can
connect directly to a microprocessor which supports: Serial Peripheral Interface (SPI), IIC or 8-bit parallel interface. Display
data stores in an on-chip display data RAM of 128 x 129 x 2 bits. It performs display data RAM read/write operation with no
external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to
drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
4-level Gray Scale
– Display with PWM and FRC Methods
DDRAM Data [2n:2n+1]
Gray Scale
2n
2n + 1
0
0
White
0
1
Light gray
1
0
Dark gray
1
1
Black
(Accessible column address, n = 0~127)
Driver Output Circuits
On-chip Low Power Analog Circuit
128 segment outputs / 128+1 common outputs
– On-chip oscillator circuit
Applicable Duty Ratios
– Voltage booster (x3, x4, x5 or x6)
– Various partial display
– Voltage regulator (temperature coefficient: -0.144%/˚C, or
– Partial window moving & data scrolling
external input)
On-chip Display Data RAM
– On-chip electronic contrast control function (64 steps X 8)
– Capacity: 128 × 129 × 2= 33,024 bits
– Voltage follower (LCD bias : 1/5 to 1/12)
Microprocessor Interface
Operating Voltage Range
– 8-bit bi-directional parallel interface supports 6800-series
– Supply voltage (VDD): 1.8 to 3.3V
or 8080-series MPU
– Supply voltage (VDD2): 2.4 to 3.3V
– 4-line serial interface (4-Line SPI)
– LCD driving voltage (VLCD = V0 - VSS): 3.5 to 15.0 V
– 3-line serial interface (3-Line 8-bit SPI)
Package Type
– IIC serial interface
– Application for COG
ST7541
6800 , 8080 ,
4-Line , 3-Line interface
(without IIC interface)
ST7541i
IIC interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
Ver 1.9
1/78
2007/9/3
ST7541
ST7541 Pad Arrangement (COG)
Chip Size: 12,575 um × 1,220 um
Bump Pitch:
PAD NO 1 ~ 229, 353 ~ 385: 55 um (COM/SEG), PAD NO 230 ~ 338: 75 um (I/O) ,PAD NO 339 ~ 352: 75 um (I/O) ,
PAD 338 ~ 339 : 81um
Bump Size:
PAD NO 1 ~ 196, 218 ~ 229, 353 ~ 364 : 35(x) um ×96(y) um
PAD NO 197 ~ 217, 365 ~ 385 : 96(x) um ×35(y) um
PAD NO 230 ~ 352 : 55(x)um ×60(y) um
Bump Height: 17 um (Typ)
Chip Thickness:
Part Number
ST7541-G
ST7541-G2
ST7541-G4
Ver 1.9
Thickness
635 um (default)
480 um
300 um
2/78
2007/9/3
ST7541
Pad Center Coordinates
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
1
COM30
5096
556
36
SEG3
3171
556
2
COM29
5041
556
37
SEG4
3116
556
3
COM28
4986
556
38
SEG5
3061
556
4
COM27
4931
556
39
SEG6
3006
556
5
COM26
4876
556
40
SEG7
2951
556
6
COM25
4821
556
41
SEG8
2896
556
7
COM24
4766
556
42
SEG9
2841
556
8
COM23
4711
556
43
SEG10
2786
556
9
COM22
4656
556
44
SEG11
2731
556
10
COM21
4601
556
45
SEG12
2676
556
11
COM20
4546
556
46
SEG13
2621
556
12
COM19
4491
556
47
SEG14
2566
556
13
COM18
4436
556
48
SEG15
2511
556
14
COM17
4381
556
49
SEG16
2456
556
15
COM16
4326
556
50
SEG17
2401
556
16
COM15
4271
556
51
SEG18
2346
556
17
COM14
4216
556
52
SEG19
2291
556
18
COM13
4161
556
53
SEG20
2236
556
19
COM12
4106
556
54
SEG21
2181
556
20
COM11
4051
556
55
SEG22
2126
556
21
COM10
3996
556
56
SEG23
2071
556
22
COM9
3941
556
57
SEG24
2016
556
23
COM8
3886
556
58
SEG25
1961
556
24
COM7
3831
556
59
SEG26
1906
556
25
COM6
3776
556
60
SEG27
1851
556
26
COM5
3721
556
61
SEG28
1796
556
27
COM4
3666
556
62
SEG29
1741
556
28
COM3
3611
556
63
SEG30
1686
556
29
COM2
3556
556
64
SEG31
1631
556
30
COM1
3501
556
65
SEG32
1576
556
31
COM0
3446
556
66
SEG33
1521
556
32
COMS1
3391
556
67
SEG34
1466
556
33
SEG0
3336
556
68
SEG35
1411
556
34
SEG1
3281
556
69
SEG36
1356
556
35
SEG2
3226
556
70
SEG37
1301
556
Ver 1.9
3/78
2007/9/3
ST7541
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
71
SEG38
1246
556
106
SEG73
-679
556
72
SEG39
1191
556
107
SEG74
-734
556
73
SEG40
1136
556
108
SEG75
-789
556
74
SEG41
1081
556
109
SEG76
-844
556
75
SEG42
1026
556
110
SEG77
-899
556
76
SEG43
971
556
111
SEG78
-954
556
77
SEG44
916
556
112
SEG79
-1009
556
78
SEG45
861
556
113
SEG80
-1064
556
79
SEG46
806
556
114
SEG81
-1119
556
80
SEG47
751
556
115
SEG82
-1174
556
81
SEG48
696
556
116
SEG83
-1229
556
82
SEG49
641
556
117
SEG84
-1284
556
83
SEG50
586
556
118
SEG85
-1339
556
84
SEG51
531
556
119
SEG86
-1394
556
85
SEG52
476
556
120
SEG87
-1449
556
86
SEG53
421
556
121
SEG88
-1504
556
87
SEG54
366
556
122
SEG89
-1559
556
88
SEG55
311
556
123
SEG90
-1614
556
89
SEG56
256
556
124
SEG91
-1669
556
90
SEG57
201
556
125
SEG92
-1724
556
91
SEG58
146
556
126
SEG93
-1779
556
92
SEG59
91
556
127
SEG94
-1834
556
93
SEG60
36
556
128
SEG95
-1889
556
94
SEG61
-19
556
129
SEG96
-1944
556
95
SEG62
-74
556
130
SEG97
-1999
556
96
SEG63
-129
556
131
SEG98
-2054
556
97
SEG64
-184
556
132
SEG99
-2109
556
98
SEG65
-239
556
133
SEG100
-2164
556
99
SEG66
-294
556
134
SEG101
-2219
556
100
SEG67
-349
556
135
SEG102
-2274
556
101
SEG68
-404
556
136
SEG103
-2329
556
102
SEG69
-459
556
137
SEG104
-2384
556
103
SEG70
-514
556
138
SEG105
-2439
556
104
SEG71
-569
556
139
SEG106
-2494
556
105
SEG72
-624
556
140
SEG107
-2549
556
Ver 1.9
4/78
2007/9/3
ST7541
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
141
SEG108
-2604
556
176
COM75
-4529
556
142
SEG109
-2659
556
177
COM76
-4584
556
143
SEG110
-2714
556
178
COM77
-4639
556
144
SEG111
-2769
556
179
COM78
-4694
556
145
SEG112
-2824
556
180
COM79
-4749
556
146
SEG113
-2879
556
181
COM80
-4804
556
147
SEG114
-2934
556
182
COM81
-4859
556
148
SEG115
-2989
556
183
COM82
-4914
556
149
SEG116
-3044
556
184
COM83
-4969
556
150
SEG117
-3099
556
185
COM84
-5024
556
151
SEG118
-3154
556
186
COM85
-5079
556
152
SEG119
-3209
556
187
COM86
-5134
556
153
SEG120
-3264
556
188
COM87
-5189
556
154
SEG121
-3319
556
189
COM88
-5244
556
155
SEG122
-3374
556
190
COM89
-5299
556
156
SEG123
-3429
556
191
COM90
-5354
556
157
SEG124
-3484
556
192
COM91
-5409
556
158
SEG125
-3539
556
193
COM92
-5464
556
159
SEG126
-3594
556
194
COM93
-5519
556
160
SEG127
-3649
556
195
COM94
-5574
556
161
Reserve
-3704
556
196
COM95
-5629
556
162
Reserve
-3759
556
197
COM96
-6234
550
163
Reserve
-3814
556
198
COM97
-6234
495
164
Reserve
-3869
556
199
COM98
-6234
440
165
COM64
-3924
556
200
COM99
-6234
385
166
COM65
-3979
556
201
COM100
-6234
330
167
COM66
-4034
556
202
COM101
-6234
275
168
COM67
-4089
556
203
COM102
-6234
220
169
COM68
-4144
556
204
COM103
-6234
165
170
COM69
-4199
556
205
COM104
-6234
110
171
COM70
-4254
556
206
COM105
-6234
55
172
COM71
-4309
556
207
COM106
-6234
0
173
COM72
-4364
556
208
COM107
-6234
-55
174
COM73
-4419
556
209
COM108
-6234
-110
175
COM74
-4474
556
210
COM109
-6234
-165
Ver 1.9
5/78
2007/9/3
ST7541
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
211
COM110
-6234
-220
246
D0
-3529
-574
212
COM111
-6234
-275
247
D0
-3454
-574
213
COM112
-6234
-330
248
D1
-3379
-574
214
COM113
-6234
-385
249
D1
-3304
-574
215
COM114
-6234
-440
250
D2
-3229
-574
216
COM115
-6234
-495
251
D2
-3154
-574
217
COM116
-6234
-550
252
D3
-3079
-574
218
COM117
-5418
-556
253
D3
-3004
-574
219
COM118
-5363
-556
254
D4
-2929
-574
220
COM119
-5308
-556
255
D4
-2854
-574
221
COM120
-5253
-556
256
D5
-2779
-574
222
COM121
-5198
-556
257
D5
-2704
-574
223
COM122
-5143
-556
258
D6
-2629
-574
224
COM123
-5088
-556
259
D6
-2554
-574
225
COM124
-5033
-556
260
D7
-2479
-574
226
COM125
-4978
-556
261
D7
-2404
-574
227
COM126
-4923
-556
262
VDD
-2329
-574
228
COM127
-4868
-556
263
VDD
-2254
-574
229
COMS2
-4813
-556
264
VDD
-2179
-574
230
T9
-4729
-574
265
VDD
-2104
-574
231
VDD
-4654
-574
266
VDD
-2029
-574
232
PS0
-4579
-574
267
VDD
-1954
-574
233
PS1
-4504
-574
268
VDD2
-1879
-574
234
PS2
-4429
-574
269
VDD2
-1804
-574
235
VSS
-4354
-574
270
VDD2
-1729
-574
236
CSB
-4279
-574
271
VDD2
-1654
-574
237
CSB
-4204
-574
272
VDD2
-1579
-574
238
RST
-4129
-574
273
VDD2
-1504
-574
239
RST
-4054
-574
274
VDD2
-1429
-574
240
A0
-3979
-574
275
VDD2
-1354
-574
241
A0
-3904
-574
276
VDD2
-1279
-574
242
RW_WR
-3829
-574
277
VDD2
-1204
-574
243
RW_WR
-3754
-574
278
VDD2
-1129
-574
244
E_RD
-3679
-574
279
VDD2
-1054
-574
245
E_RD
-3604
-574
280
VDD2
-979
-574
Ver 1.9
6/78
2007/9/3
ST7541
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
281
VDD2
-904
-574
316
VOUT_OUT
1721
-574
282
VDD2
-829
-574
317
VOUT_OUT
1796
-574
283
VDD2
-754
-574
318
VOUT_OUT
1871
-574
284
VSS2
-679
-574
319
VOUT_OUT
1946
-574
285
VSS2
-604
-574
320
VOUT_IN
2021
-574
286
VSS2
-529
-574
321
VOUT_IN
2096
-574
287
VSS2
-454
-574
322
VOUT_IN
2171
-574
288
VSS2
-379
-574
323
VOUT_IN
2246
-574
289
VSS2
-304
-574
324
VOUT_IN
2321
-574
290
VSS2
-229
-574
325
VOUT_IN
2396
-574
291
VSS2
-154
-574
326
T[8]
2471
-574
292
VSS2
-79
-574
327
T[7]
2546
-574
293
VSS2
-4
-574
328
T[6]
2621
-574
294
VSS2
71
-574
329
T[5]
2696
-574
295
VSS2
146
-574
330
T[4]
2771
-574
296
VSS2
221
-574
331
T[3]
2846
-574
297
VSS2
296
-574
332
T[2]
2921
-574
298
VSS2
371
-574
333
T[1]
2996
-574
299
VSS2
446
-574
334
T[0]
3071
-574
300
VSS
521
-574
335
VDD
3146
-574
301
VSS
596
-574
336
REF
3221
-574
302
VSS
671
-574
337
VSS
3296
-574
303
VSS
746
-574
338
VEXT
3371
-574
304
VSS
821
-574
339
VDD
3452
-574
305
VSS
896
-574
340
INTRS
3527
-574
306
TA
971
-574
341
VSS
3602
-574
307
TB
1046
-574
342
OSC1
3677
-574
308
MF2
1121
-574
343
OSC1
3752
-574
309
MF1
1196
-574
344
VDD
3827
-574
310
MF0
1271
-574
345
VR
3902
-574
311
DS0
1346
-574
346
VR
3977
-574
312
DS1
1421
-574
347
V4
4052
-574
313
VDD
1496
-574
348
V3
4127
-574
314
VOUT_OUT
1571
-574
349
V2
4202
-574
315
VOUT_OUT
1646
-574
350
V1
4277
-574
Ver 1.9
7/78
2007/9/3
ST7541
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
351
V0
4352
-574
369
COM47
6234
-330
352
V0
4427
-574
370
COM46
6234
-275
353
COM63
5340
-556
371
COM45
6234
-220
354
COM62
5395
-556
372
COM44
6234
-165
355
COM61
5450
-556
373
COM43
6234
-110
356
COM60
5505
-556
374
COM42
6234
-55
357
COM59
5560
-556
375
COM41
6234
0
358
COM58
5615
-556
376
COM40
6234
55
359
COM57
5670
-556
377
COM39
6234
110
360
COM56
5725
-556
378
COM38
6234
165
361
COM55
5780
-556
379
COM37
6234
220
362
COM54
5835
-556
380
COM36
6234
275
363
COM53
5890
-556
381
COM35
6234
330
364
COM52
5945
-556
382
COM34
6234
385
365
COM51
6234
-550
383
COM33
6234
440
366
COM50
6234
-495
384
COM32
6234
495
367
COM49
6234
-440
385
COM31
6234
550
368
COM48
6234
-385
Ver 1.9
8/78
2007/9/3
ST7541
BLOCK DIAGRAM
SEG0 TO SEG127
COM0 TO COM128
VDD
V0
V1
V2
V3
V4
SEGMENT DRIVERS
COMMON DRIVERS
VSS
DATA LATCHES
COMMON
OUTPUT
CONTROLLER
CIRCUIT
V/F
Circuit
V0
VR
INTRS
VEXT
REF
FRC/PWM FUNCTION CIRCUIT
RESET
V/R
Circuit
OSCILLATOR
DISPLAY DATA RAM
(DDRAM)
[128X129X2]
OSC1
TIMING
GENERATOR
DISPLAY
ADDRESS
COUNTER
V/C
Circuit
ADDRESS COUNTER
VOUT_IN
VOUT_OUT
VDD2
VSS2
DATA
REGISTER
INSTRUCTION
REGISTER
BUS
HOLDER
INSTRUCTION
DECODER
MPU INTERFACE(PARALLEL & SERIAL)
DB0
DB1
DB2
DB3
DB4
DB5
DB6(SI)
9/78
DB7(SCL)
E_RD
RW_WR
A0
CSB
/RST
PS0
PS1
PS2
DS0
DS1
MF0
MF1
MF2
Ver 1.9
2007/9/3
ST7541
PIN DESCRIPTION
POWER SUPPLY
Name
Type
Description
VDD
Power
Digital Power supply
VSS
Power
Ground
VDD2
Power
Analog Power supply
VSS2
Power
Ground
VOUT_OUT
Power
Internal booster output. Left these pads open when using external power supply.
Short VOUT_OUT with VOUT_IN when using internal booster.
The power supply pads of internal regulator. Apply high voltage here for internal regulator.
VOUT_IN
Power
If using external booster, VOUT_OUT must be open with internal booster programmed OFF (set
register VC=0).
If using internal booster, short VOUT_OUT with VOUT_IN together.
LCD driver supply voltages. V1, V2, V3, V4 need the capacitor between with VSS.
Voltages should have the following relationship:
V0
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
V1
V2
Power
V3
V4
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD bias.
LCD bias
V1
V2
V3
V4
1/N bias
(N-1) / N x V0
(N-2) / N x V0
(2/N) x V0
(1/N) x V0
NOTE: N = 5 to 12
LCD DRIVER SUPPLY
Name
Type
Description
V0 voltage adjustment pin
VR
I
It is valid only when on-chip resistors are not used (INTRS = "L")
When using internal resistors (INTRS = "H"), open this pin
Selects the external VREF voltage via the VEXT pin
REF
I
REF = “H”: using the internal VREF
REF = “L”: using the external VREF
Externally input reference voltage (VREF) for the internal voltage regulator
VEXT
I
It is valid only when REF is "L"
When using internal voltage regulator, this pin must be open
OSC1
Ver 1.9
I
External OSC input pin, when using internal clock oscillator, connect OSC1 to VDD.
10/78
2007/9/3
ST7541
SYSTEM CONTROL
Name
Type
Description
Internal resistor select pin. This pin selects the resistors for adjusting V0 voltage level.
INTRS
I
INTRS = "H": use the internal resistors.
INTRS = "L": use the external resistors.
VR pin and external resistive divider control V0 voltage
Test pins. Don’ t use these pins.
T[0] ~ T[9]
Test
Reserve
X
This pin must be OPEN
MF[2:0]
I
Manufacturer ID code for reference, suggest set to [ MF2.MF1.MF0 = 0.0.0 ]
DS[1:0]
I
Display size ID code for reference, suggest set to [ DS1.DS0 = 0.0 ]
TA, TB
I
Please Open these pins.
Test pins
TA and TB must connect to Vss.
MICROPROCESSOR INTERFACE
Name
Type
RST
I
Description
Reset input pin. When RST is “L”, initialization is executed.
Microprocessor interface select input pin
PS[2:0]
I
PS2
PS1
PS0
L
L
H
L
H
L
L
L
H
Interface
A0
Data
Read/Write
Serial clock
Parallel 80
A0
DB[7:0]
/RD, /WR
-
H
Parallel 68
A0
DB[7:0]
E, R/W
-
L
3Line Serial
-
SID (DB7)
Write only
SCLK (DB6)
H
L
4Line Serial
A0
SID (DB7)
Write only
SCLK (DB6)
L
L
IIC Serial
-
SDA
Read/Write
SCL
mode
NOTE:
*1. Reading of data or status is not available in serial interface modes (4-Line, 3-Line and IIC).
*2. In 3-Line or 4-Line interface: DB[5:0], E_RD and RW_WR must be fixed to “H” or “L”.
*3. In IIC and 3-Line interface: A0 must be fixed to “H” or “L”.
CSB
I
Chip select input. Data/instruction I/O is enabled only when CSB is "L".
When chip select is non-active, DB[7:0] will be high impedance.
Register selection input.
A0
I
A0 = "H": DB[7:0] are display data.
A0 = "L": DB[7:0] are control instruction.
Read / Write execution control pin
PS1
MPU type
RW_WR
Description
Read / Write control input pin.
RW_WR
I
H
6800-series
R/W
R/W = “H” : read;
R/W = “L” : write.
Write enable clock input pin.
L
8080-series
/WR
The data on DB[7:0] are latched at the rising edge of the
/WR signal.
Ver 1.9
11/78
2007/9/3
ST7541
MICROPROCESSOR INTERFACE (continued)
Name
Type
Description
Read / Write execution control pin
PS1
MPU Type
E_RD
Description
Read / Write control input pin.
E_RD
I
H
6800-series
E
R/W = “H”: When E is “H”, DB[7:0] are in an output status;
R/W = “L”: DB[7:0] are latched at the falling edge of this
signal.
L
8080-series
/RD
Read enable clock input pin.
When /RD is “L”, DB[7:0] are in output status.
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus.
When chip select is not active (CSB=H), DB[7:0] will be high impedance.
When the 3-Line/4-Line serial interface is selected (PS[2:0] = "000" or “010”):
DB[0:5]: high impedance (connect to “H” or “L”);
DB6: serial input clock (SCLK);
DB7: serial input data (SID).
DB[7:0]
I/O
When chip select is not active, DB[7:0] is high impedance.
When the IIC serial interface is selected (PS[2:0] = "100"):
DB7: serial clock input (SCL);
DB[6:4]: serial data input (SDA_IN);
DB[3:2]: serial data output (SDA_OUT). For acknowledge signal output in IIC interface;
DB[1:0]: Is slave address (SA) bit1, 0, must connect to Vdd or Vss.
*DB[6:2]: must be connected together as SDA signal of IIC interface.
Note:
1.
By connecting SDA_IN and SDA_OUT externally, the SDA line becomes fully IIC interface compatible. Separating
acknowledge-output from serial data input is advantageous for chip-on-glass (COG) applications. In COG applications,
the ITO resistance and the pull-up resistor will form a voltage divider which affects acknowledge-signal level. Larger
ITO resistance will raise the acknowledge-signal level and system cannot recognize this level as a valid logic “0” level.
By separating SDA_IN from SDA_OUT, the IC can be used in a mode which ignores the acknowledge-bit. For
applications which check acknowledge-bit, it is necessary to minimize the ITO resistance of the SDA_OUT trace to
guarantee a valid low level.
2.
After VDD is turned ON, any MPU interface pins cannot be left floating.
Ver 1.9
12/78
2007/9/3
ST7541
LCD DRIVER OUTPUTS
Name
Type
Description
LCD segment driver outputs.
The display data and frame signal control the output voltage of segment driver.
SEG0
to
Display Data
Frame
H
O
SEG127
Segment driver output voltage
Normal display
Reverse display
+
V0
V2
H
-
VSS
V3
L
+
V2
V0
L
-
Display OFF, Power Saving
V3
VSS
VSS
VSS
LCD common driver outputs.
The scan signal and frame signal control the output voltage of common driver.
COM0
to
Scan Data
Frame
Common driver output voltage
H
+
VSS
O
COM127
H
-
V0
L
+
V1
L
-
V4
Display OFF, Power Saving
COMS
(COMS1,2)
O
VSS
Common output for the icons.
The output signals of two pins are same. When not used, these pins should be left open.
Recommend ITO Resistance
PIN Name
ITO Resistance
PS[2:0], REF, OCS1, INTRS, TA, TB
No Limitation
T[9:0], VR, VEXT
Floating
Vdd, Vdd2, Vss, Vss2 , VOUT_IN , VOUT_OUT
<100Ω
*1
<300Ω
*1
<1KΩ
SDA (SDA_IN & SDA_OUT)
CSB , E , R/W , A0 , DB[7:0]
V0, V1 , V2 , V3 , V4
<500Ω
RST
<10KΩ
Note:
1.
If using IIC interface mode, the resistance of SDA signal should be lower than 300Ω (if the system pull up resistor is
2.
The option setting to be “H” should connect to VDD.
3.
The option setting to be “L” should connect to VSS.
4.7KΩ).
Ver 1.9
13/78
2007/9/3
ST7541
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There is CSB pin for chip selection. The ST7541 can interface with an MPU when CSB is "L". When these pins are set to any
other combination, A0, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of
serial interface, the internal shift register and the counter are reset.
Parallel / Serial Interface
ST7541 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial
interface is determined by PS pin as shown in Table 1.
Table 1 Parallel / Serial Interface Mode
Type
PS2
PS1
L
H
L
L
Parallel
L
L
L
H
H
L
Serial
PS0
CSB
H
CSB
L
Interface mode
6800-series MPU mode
8080-series MPU mode
CSB
3-Line SPI mode
CSB
4-Line SPI mode
CSB
IIC SPI mode
Parallel Interface (PS0 = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in Table 2. The
type of data transfer is determined by signals at A0, E_RD and RW_WR as shown in
Table 3.
Table 2 Microprocessor Selection for Parallel Interface
PS1
CSB
A0
E_RD
RW_WR
DB0 to DB7
MPU bus
H
CSB
A0
E
R/W
DB0 to DB7
6800-series
L
CSB
A0
/RD
/WR
DB0 to DB7
8080-series
Table 3 Parallel Data Transfer
Common
A0
H
6800-series
8080-series
E_RD
RW_WR
E_RD
RW_WR
(E)
(R/W)
(/RD)
(/WR)
H
H
L
H
Description
Display data read out
H
H
L
H
L
Display data write
L
H
H
L
H
Register status read
L
H
L
H
L
Writes to internal register (instruction)
NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case,
interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, RW_WR as in
case of 6800-series mode.
Ver 1.9
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2007/9/3
ST7541
Serial Interface
Serial mode
PS0
PS1
PS2
CSB
A0
3-Line SPI mode
4-Line SPI mode
L
L
L
CSB
No used
L
H
L
CSB
Used
IIC SPI mode
L
L
H
CSB
No Used
If A0 is not used it must be fixed either “H” or “L”
3-Line / 4-Line (PS[2:0] = "000" or “010”)
3-Line and 4-Line serial interface are similar except the display data/command indication is controlled by commands (3-Line
SPI mode) or by the register selection pin (A0, 4-Line SPI mode).
When ST7541 is active (CSB=“L”), serial data (DB7) and serial clock (DB6) inputs are enabled. When ST7541 is not active
(CSB=“H”), the internal 8-bit shift register and 3-bit counter are reset. The read operation is not supported in these modes.
Serial data on SID is latched at the rising edge of serial clock on SCL. After the 8th serial clock, the serial input data on SID
will be processed as 8-bit parallel data/command. When writing sequential display data, the DDRAM column address pointer
will be increased by one automatically after each byte of DDRAM access.
4-Line SPI Mode (PS0 = "L", PS1 = "H", PS2 = "L")
This mode uses A0 pin to indicate the input serial data on SID is display data (A0=“H”) or command (A0=“L”).
Figure 1. 4-line SPI Timing
3-Line SPI Mode (PS0 = "L", PS1 = "L" ,PS2= "L")
This mode does not have an A0 pin to indicate the input serial data on SID is display data or command. The default input
from MCU is command. The display data/command indication is controlled via software. The MCU send 2-byte command
(Set Data Direction & Display Data Length) before the display data(s). These 2 commands are only used in 3-Line SPI
mode.
The first command “Set Data Direction” (11101000b) indicates MCU wants to transfer display data. The second command
“Display Data Length” informs LCD driver the number of input data bytes. After receiving these two continuous commands,
the following messages will be treated as display data rather than command. After the display data string is sent over, the
following bytes are treated as commands (unless receiving another pair of Set Data Direction & Display Data Length
commands). If data transfer is stopped during transmitting, it is not valid data. New data will be transferred serially with most
significant bit first.
NOTE: In spite of transmission of data, if CSB is disabled, the state will be terminated abnormally and next state is initialized.
Ver 1.9
15/78
2007/9/3
ST7541
(1) Set Page and Column Address:
Action
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Set Page Address
1
0
1
1
P3
P2
P1
P0
Set Column Address MSB
0
0
0
1
0
Y7
Y6
Y5
Set Column Address LSB
0
0
0
0
Y4
Y3
Y2
Y1
(2) Set Data Direction and Set Display Data Length:
Action
Set Data Direction (DDC)
(3-Line SPI mode Only)
Set Display Data Length
(No. of DATA)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
0
1
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
(3) This figure is example for 104 Data bytes to be transferred.
Figure 2. 3-Line SPI Timing (A0 is not used)
IIC Interface (PS0 = "L", PS1 = "L", PS2= "H")
IIC Interface uses two signals (Serial Data: SDA and Serial Clock: SCL) to communicate with MPU and other ICs or modules.
It receives the command and data sent by MPU through SDA and SCL. Both SDA and SCL must connect to VDD by a pull-up
resistor which drives SDA and SCL to “HIGH” when the bus is not busy. Data transfer can be initiated only when the bus is
not busy. This interface supports writing command/data and reading acknowledge-bit.
[ BIT TRANSFER ]
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes on SDA while SCL is “HIGH” will be interpreted as START or STOP. Bit transfer is
illustrated in Figure 3.
SDA
SCLK
Data line stable
Data Valid
Change of data
allowed
Figure 3. Bit transfer
Ver 1.9
16/78
2007/9/3
ST7541
[ START AND STOP CONDITIONS ]
When the bus is not busy, both SDA and SCL lines remain HIGH. A HIGH-to-LOW transition of SDA, while SCL is HIGH is
defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition
(P). The START and STOP conditions are illustrated in Figure 4.
Figure 4. Definition of START and STOP conditions
[ SYSTEM CONFIGURATION ]
The system configuration is illustrated in Figure 5 and some word-definitions are explained below:
l
Transmitter: the device, which sends the data to the bus.
l
Receiver: the device, which receives the data from the bus.
l
Master: the device, which initiates a transfer, generates clock signals and terminates a transfer.
l
Slave: the device addressed by a master.
l
Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message.
l
Arbitration: the procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is
allowed to do so and the message is not corrupted.
l
Synchronization: procedure to synchronize the clock signals of two or more devices.
Figure 5. System configuration
[ ACKNOWLEDGE ]
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on SDA by the
transmitter during the time when the master generates an extra acknowledge-related clock pulse. A slave receiver which is
addressed must generate an acknowledge-bit, after the reception of each byte. The device that acknowledges must
pull-down the SDA line during the acknowledge-clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge-related clock pulse (set-up and hold times must be taken into consideration). Acknowledgement on the IIC
Interface is illustrated in Figure 6.
Figure 6. Acknowledgement on the 2-line Interface
Ver 1.9
17/78
2007/9/3
ST7541
[ IIC INTERFACE PROTOCOL ]
The IIC interface of ST7541 supports writing command/data to the addressed slaves on the bus. Before transferring any data
on the bus, the target device(s) should be addressed first. Four slave addresses (0111100, 0111101, 0111110 and 0111111)
are reserved for ST7541. The least significant 2 bits of the slave address is configured by connecting the inputs SA1 and
SA0 to either logic 0 (VSS) or logic 1 (VDD). The IIC Interface protocol is illustrated in Figure 7.
The IIC communication sequence is initiated with a START condition (S) set by the master, and then followed by a slave
address. All slaves with the same specified address should acknowledge in parallel, all the others will ignore the bus transfer.
After the acknowledgement of the slave address, one or more command words are followed. The command word(s) define
the status of the addressed slaves. A command word consists of a control byte (which defines Co and A0) and a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. Co=0), and is followed by data byte(s) only. The A0 bit
in the control byte defines whether the data byte(s) will be interpreted as command or as RAM data. Therefore, after the last
control byte, either a series of display data bytes or a series of command data bytes may follow (depends on the A0 bit). If the
A0 bit is set to 0, the command bytes will be decoded and execute. If the A0 bit of the last control byte is set to 1, the series of
display data bytes will be stored in DDRAM. The data pointer is automatically increased by 1 after writing each byte of display
data into DDRAM. The addressed slave makes the acknowledgement after receiving each byte of command or display data.
At the end of transmission the bus master issues a STOP condition (P).
Figure 7. 2-line Interface protocol
Co
0
1
Last control byte. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP or RE-START condition.
Another control byte will follow the data byte unless a STOP or RE-START condition is received.
BUSY FLAG
The Busy Flag indicates whether the ST7541 is operating or not. When DB7 is "H" in read status operation, this device is in
busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check
this flag before each instruction, which improves the MPU performance.
Ver 1.9
18/78
2007/9/3
ST7541
DATA TRANSFER
The ST7541 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to
on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 8. And when reading data
from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads
this stored data from bus holder for the next data read cycle as shown in Figure 9. This means that a dummy read cycle must
be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the
specified address cannot be output with the read display data instruction right after the address sets, but can be output at the
second read of data.
MPU signal
A0
/WR
D0 to D7
N
D(N)
D(N+1) D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
N+1
N+2
N+3
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
Figure 8 Write Timing
MPU signal
A0
/WR
/RD
D0 to D7
N
Dummy
D(N)
D(N+1)
Internal signals
/WR
/RD
BUS HOLDER
COLUMN ADDRESS
N
N
D(N)
D(N+1) D(N+2)
D(N)
D(N+1) D(N+2)
Figure 9 Read Timing
Ver 1.9
19/78
2007/9/3
ST7541
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 129-row (17 pages by 8 bits) by 128-column addressable array.
Each pixel can be selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8
lines and the 17th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through
DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The
microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently,
data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
Page Address Circuit
It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 16 is a special RAM
area for the icons and display data DB0 is only valid. The page address is set from 0 to 15, and Page 16 is for Icon page.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line
Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip
RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At
the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and
generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is enabled by
setting icon control register, display data of icons are not scrolled because the MPU can not access Line Address of icons.
Segment Control Circuit
This circuit controls the display data scan circuit. It allows the display data related commands (such as: Display ON/OFF,
Reverse Display ON/OFF and Entire Display ON/OFF) without changing the data in the DDRAM.
Column Address Circuit
Command “Set Column Address MSB / LSB” will set 7-bit ([Y7:Y1]) of the internal column address and Y0 is set to “0”. The
internal column address (Y[7:0]) is increased by 1 after accessing (read or write) each byte of display data (refer to Figure
10). After the 2
nd
access (read or write), the Column Address will point to the next column)
SEG
0
1
2
3
…
124
125
126
127
00H
01H
02H
03H
…
7CH
7DH
7EH
7FH
Set Column
Address
[Y7:Y1]
DDRAM Col.
Sequential Display Data Read/Write Direction
Address
[Y7:Y0]
Display data
(MX=0)
00
01
02
03
04
05
06
07
…
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
0
0
1
0
0
…
1
1
1
0
0
1
0
0
0
0
0
1
1
0
1
1
LCD panel
…
display
Display data
(MX=1)
0
0
0
1
1
0
1
1
LCD panel
…
…
display
Figure 10 The Relationship between the Column Address and The Segment Outputs
Ver 1.9
20/78
2007/9/3
ST7541
LCD DISPLAY CIRCUITS
FRC (Frame Rate Control) and PWM (Pulse Width Modulation) Function Circuit
ST7541 incorporates FRC function and PWM circuits to display a 4-level gray scale. The FRC function and PWM utilize
liquid crystal characteristics whose transmittance is changed by an effective value of applied voltage. ST7541 provides
palette-registers to assign the desired gray level. These registers are set by the instructions and the RST.
4FRC & 3FRC vs. 9PWM, 12PWM, 15PWM
– Gray Scale Table of 4 FRC (Frame Rate Control)
Gray scale level
MSB (DB7 to DB4)
White
Light gray
Dark gray
LSB (DB3 to DB0)
2nd FR (FR2)
1st FR (FR1)
4th FR (FR4)
3rd FR (FR3)
2nd FR (FR2)
1st FR (FR1)
4th FR (FR4)
3rd FR (FR3)
2nd FR (FR2)
1st FR (FR1)
4th FR (FR4)
3rd FR (FR3)
2nd FR (FR2)
1st FR (FR1)
4th FR (FR4)
3rd FR (FR3)
MSB (DB7 to DB4)
LSB (DB3 to DB0)
Black
– Gray Scale Table of 3 FRC (Frame Rate Control)
Gray scale level
White
Light gray
Dark gray
Black
2nd FR (FR2)
1st FR (FR1)
XXXX
3rd FR (FR3)
2nd FR (FR2)
1st FR (FR1)
XXXX
3rd FR (FR3)
2nd FR (FR2)
1st FR (FR1)
XXXX
3rd FR (FR3)
2nd FR (FR2)
1st FR (FR1)
XXXX
3rd FR (FR3)
– Gray Scale Table of PWM (Pulse Width Modulation)
Frame Parameter (FRn)
15-PWM
12-PWM
9-PWM
Dec
Hex
4-bit
PWM width
Note
PWM width
Note
PWM width
Note
0
00
0000
0(0/15)
Brighter
0(0/12)
Brighter
0(0/9)
Brighter
1
01
0001
1/15
1/12
1/9
2
02
0010
2/15
2/12
2/9
3
03
0011
3/15
3/12
3/9
4
04
0100
4/15
4/12
4/9
5
05
0101
5/15
5/12
5/9
6
06
0110
6/15
6/12
6/9
7
07
0111
7/15
7/12
7/9
8
08
1000
8/15
8/12
8/9
9
09
1001
9/15
9/12
1(9/9)
10
0A
1010
10/15
10/12
11
0B
1011
11/15
11/12
12
0C
1100
12/15
1(12/12)
13
0D
1101
13/15
14
0E
1110
14/15
15
0F
1111
1(15/15)
Ver 1.9
0/12
Darker
21/78
Darker
This field is
0/9
Darker
This field is
OFF level
OFF level
2007/9/3
ST7541
Oscillator
This is on-chip Oscillator without external resistor. When the internal oscillator is used, this pin must connect to VDD; when
the external oscillator is used, this pin could be input pin. This oscillator signal is used in the voltage converter and display
timing generation circuit.
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is
generated in synchronization with the display clock and the display data latch circuit latches the 128-bit display data in
synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the
access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables
the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the
common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and
internal timing signal are shown in Figure 11.
128 129
1
2
3
4
5
6
7
8
9
10
11
12
121 122 123 124 125 126 127 128 129 1
2
3
4
5
CL(Internal)
FR(Internal)
M(Internal)
COM0
V0
V1
V2
V3
V4
VSS
COM1
V0
V1
V2
V3
V4
VSS
SEGn
V0
V1
V2
V3
V4
VSS
Figure 11 2-frame AC Driving Waveform (Duty Ratio: 1/129)
128
129
1
2
3
4
5
6
7
8
9
10
11
12
120
121
122
123
124
125
126
127
128
129
1
2
3
4
CL(Internal)
FR(Internal)
M(Internal)
V0
V1
V2
V3
V4
Vss
COM0
V0
V1
V2
V3
V4
Vss
COM1
V0
V1
V2
V3
V4
Vss
SEGn
Figure 12 N-Line Inversion Driving Waveform (N=5,Duty Ratio=1/129)
Ver 1.9
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ST7541
LCD DRIVER CIRCUIT
This driver circuit is configured by 129-channel common drivers and 128-channel segment drivers. This LCD panel driver
voltage depends on the combination of display data and M signal.
V DD
V SS
M
COM0
V0
COM1
V1
V2
COM0
COM2
V3
V4
VSS
COM3
COM4
V0
COM5
V1
COM6
V2
COM1
V3
COM7
V4
VSS
COM8
V0
COM9
V1
V2
COM2
COM10
V3
COM11
V4
VSS
COM12
V0
COM13
V1
COM14
V2
SEG0
SEG 0
1
2
3
V3
V4
VSS
4
V0
V1
V2
SEG1
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
COM0 to SEG0
-V4
-V3
-V2
-V1
-V0
V0
V1
V2
V3
V4
VSS
COM0 to SEG1
-V4
-V3
-V2
-V1
-V0
Ver 1.9
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ST7541
Partial Display on LCD
ST7541 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the
various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the
instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages. The
partial display duty ratio could be set from 16 ~ 128.
If the partial display region is out of the Max. Display range, it would be no operation.
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Figure 13 Reference Example for Partial Display
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Figure 14 Partial Display (Partial Display Duty=16,initial COM0=0)
Ver 1.9
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ST7541
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Figure 15 Moving Display (Partial Display Duty=16,Initial COM0=8)
Ver 1.9
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ST7541
POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower
circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table 4 shows the
referenced combinations in using Power Supply circuits.
Table 4 Recommended Power Supply Combinations
Power
Customer Power System
V/C
V/R
V/F
circuits
circuits
circuits
111
ON
ON
ON
011
OFF
ON
ON
001
OFF
OFF
ON
OPEN
000
OFF
OFF
OFF
OPEN
Control
(VC VR VF)
Only the internal power supply circuits
are used
Only the voltage regulator circuits and
voltage follower circuits are used
Only the voltage follower circuits are
used
Only the external power supply
circuits are used
VOUT_IN
V0
Internal
V1 to V4
Without
With
capacitor
capacitor
External
Without
With
input
capacitor
capacitor
External
With
input
capacitor
External
External
input
input
Voltage Converter Circuits
These circuits boost up the electric potential between VDD2 and Vss to 3, 4, 5 or 6 times toward positive side and boosted
voltage is outputted from VOUT pin. It is possible to select the lower boosting level in any boosting circuit by “Set DC-DC
Step-up” instruction. When the higher level is selected by instruction, VOUT voltage is not valid.
Note: we would like to recommend to use the external VOUT when the panel is large than 1.8 inch
Voltage Regulator Circuits
The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting
resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier
circuits shown in Figure 16, it is necessary to be applied internally or externally.
For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And
VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter
is the value selected by
instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta= 25˚C is shown in
Table 5.
V0 = (1 + Rb / Ra) x VEV
[V] ……………… (Eq. 1)
VEV = (1 – (63 - α) / 210) x VREF
[V] ……………… (Eq. 2)
Table 5 VREF Voltage at Ta = 25°C
REF
Temp. coefficient
VREF [ V ]
1
-0.144% / ˚C
2.1
0
External input
VEXT
VOUT
V0
Rb
VEV
VR
Ra
VSS
GND
Figure 16 Internal Voltage Regulator Circuit
Ver 1.9
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ST7541
In Case of Using Internal Resistors, Ra and Rb (INTRS = “H”)
When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and
VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage".
Table 6 Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0)
3-bit data settings (R2 R1 R0)
000
001
010
011
100
101
110
111
2.3
3.0
3.7
4.4
5.1
5.8
6.5
7.2
1 + (Rb / Ra)
Figure 17 Shows V0 voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6-bit electronic volume
registers for each temperature coefficient at Ta = 25°C.
16.000
14.000
12.000
000
001
010
011
100
101
110
111
10.000
8.000
6.000
4.000
2.000
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
9
12
6
3
0
0.000
Figure 17 Electronic Volume Level (Temp. Coefficient = -0.144% / °C)
Ver 1.9
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ST7541
In Case of Using External Resistors, Ra and Rb (INTRS = "L")
When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0
and VR.
Example: For the following requirements
1. LCD driver voltage, V0 = 10V
2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)
3. Maximum current flowing Ra, Rb = 1 uA
From Eq. 1:
10 = (1 + Rb / Ra) x VEV
[V] ……………… (Eq. 3)
VEV = (1 – (63 - 32) / 210) x 2.1 = 1.79
[V] ……………… (Eq. 4)
10 / (Ra + Rb) = 1
[uA] ……………… (Eq. 5)
From Eq. 2:
From Requirement-3:
From Eq. 3~5:
Ra = 1.79
[MΩ]
Rb = 8.21
[MΩ]
Table 7 Shows the Range of V0 depending on the above Requirements.
Table 7 The Range of V0
Electronic volume level
V0
Ver 1.9
0
.......
32
.......
63
8.21
.......
10.00
.......
11.73
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ST7541
Voltage Follower Circuits
VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4), and those output impedance
are converted by the Voltage Follower for increasing drive capability. Table 8 shows the relationship between V1 to V4 level
and each duty ratio.
Table 8 The Relationship between V1 to V4 Level and Each Duty Ratio
LCD bias
V1
V2
V3
V4
Remarks
1/N
(N-1)/N x V0
(N-2)/N x V0
2/N x V0
1/N x V0
N = 5 to 12
Follower Voltage Reference Circuit (Internal Booster & Regulator)
VSS2
VSS
VSS2
C1
VSS
C1
VOUT
VDD
VOUT
VSS
INTR
INTR
VSS
V0
VR
VSS
Ra
VSS
VSS
V0
C2
C2
C2
C2
V1
V2
V3
V4
ST7541
ST7541
Rb
V0
C2
C2
C2
C2
V1
V2
V3
V4
Left is using internal Resister
Right is using External Resister
C1= 1u F ~ 4.7u F , C2 = 0.1u F ~ 1u F
Ver 1.9
(suggestion value: C1=1uF , C2=0.1uF)
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ST7541
Follower voltage reference circuit (External Vout & Internal Regulator)
VOUT
External
VDD
VOUT
External
VSS
INTR
INTR
VSS
V0
VR
VSS
Ra
VSS
VSS
V0
C2
C2
C2
C2
V1
V2
V3
V4
ST7541
ST7541
Rb
V0
C2
C2
C2
C2
V1
V2
V3
V4
Left is using internal Resister
Right is using External Resister
C1= 1u F ~ 4.7u F , C2 = 0.1u F ~ 1u F (suggestion value: C1=1uF , C2=0.1uF)
Ver 1.9
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ST7541
Booster Efficiency
By Booster Stages (3X, 4X, 5X, 6X) and Booster Efficiency (Level1~2) commands, we could easily set the best Booster
performance with suitable current consumption. If the Booster Efficiency is set to higher level (level2 is higher than level1),
The Boost Efficiency is better than lower level, and it just need few more power consumption current. It could be applied to
each multiple voltage Condition.
When the LCD Panel loading is heavier, then the Performance of Booster will be not in a good working condition. We could
set the BE level to be higher. We do not need to change to higher Booster Stage, and just need few more current. The
Booster Efficiency Command could be used together with Booster Stage Command to choose one best Boost output
condition. We could see the Boost Stage Command as a large scale operation, and see the Booster Efficiency Command as
a small scale operation. These commands are very convenient for using.
Vout Voltage
Level1
Level2
5X boost
Loading
VSS Current
Level1
Level2
5X Current
Loading
Ver 1.9
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ST7541
RESET CIRCUIT
Setting RST to “L” can initialize internal function. RST pin must connect to the reset pin of MPU and initialization by RST pin
is essential before operating. Please note the hardware reset is not same as the software reset. When RST becomes “L”, the
hardware reset procedure will start. When RESET instruction is executed, the software reset procedure will start. The
procedure is listed below:
Procedure
Hardware Reset
Software Reset
V
X
Power Save Mode: P=0
V
X
Power Control OFF: VC=0, VR=0, VF=0
V
X
Booster Step: DC[1:0]=0
V
X
Booster Efficiency: BE=1
V
X
Frame Rate: 77Hz, FR[3:0]=0
V
X
LCD Bias: 1/12 Bias, BS[2:0]=(1,1,1)
V
X
Display OFF: D=0, all SEGs/COMs output at VSS
V
X
Normal Display: REV=0, EON=0
V
X
SEG Normal Direction: ADC=0
V
X
COM Normal Direction: SHL=0
V
X
ICON Control: OFF, ICON=0
V
X
Partial Display Duty: L[7:0]=0
V
X
N-Line Inversion: OFF, N[4:0]=0
V
X
Oscillator OFF
Initial COM0: C[6:0]=0
V
X
Initial Display Line: S[6:0]=0
V
V
Read-modify-Write: Released
V
V
Display Data Length (if using 3-Line SPI Interface): D[7:0]=0
V
V
FRC/PWM Mode: 4-FRC, 9-PWM
V
V
Column Address Y[7:1]=0
V
V
Page Address P[3:0]=0
V
V
V0 Regulator Resistor: R[2:0]=(0,0,0)
V
V
EV[5:0]=(1,0,0,0,0,0)
V
V
V
V
Gray Scale Setting:
[ White Mode ] OFF
White Palette: WA[3:0]=0, WB[3:0]=0, WC[3:0]=0, WD[3:0]=0
[ Light Gray Mode ] OFF
Light Gray Palette: LA[3:0]=0, LB[3:0]=0, LC[3:0]=0, LD[3:0]=0
[ Dark Gray Mode ] OFF
Dark Gray Palette: DA[3:0]=0, DB[3:0]=0, DC[3:0]=0, DD[3:0]=0
[ Black Mode ] OFF
Black Palette: BA[3:0]=0, BB[3:0]=0, BC[3:0]=0, BD[3:0]=0
After power-on, RAM data are undefined and the display status is “Display OFF”. It’s better to initialize whole DDRAM (ex: fill
all 00h or write the display pattern) before turning the Display ON. Besides, the power is not stable at the time that the power
is just turned ON. A hardware reset is needed to initialize those internal registers after the power is stable.
Ver 1.9
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ST7541
COMMAND TABLE
Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
0
0
0
0
0
FR3
FR2
FR1
FR0
0
BE
x'
0
1
1
Mode Set
Read display data
Description
2-byte command
Set FR (Frame Rate) and
Write display data
1
0
Read status
0
1
Read data
Read data into DDRAM
Write data
BUSY
ON
RES
MF2
MF1
BE (Booster Efficiency)
Write data into DDRAM
MF0
DS1
DS0
Read the internal status
ICON=0: ICON disable
ICON control ON/OFF
0
0
1
0
1
0
0
0
1
ICON
ICON=1: ICON enable & set
page address to 16
Set page address
0
0
1
0
1
1
P3
P2
P1
P0
Set page address
Set column address MSB
0
0
0
0
0
1
0
Y7
Y6
Y5
Set column address MSB
Set column address LSB
0
0
0
0
0
0
Y4
Y3
Y2
Y1
Set column address LSB
Set Read-modify-Write
0
0
1
1
1
0
0
0
0
0
Read: No change
Reset Read-modify-Write
0
0
1
1
1
0
1
1
1
0
Release read-modify-write
Display ON/OFF
0
0
1
0
1
0
1
1
1
D
0
0
0
1
0
0
0
0
x'
x'
0
0
x'
S6
S5
S4
S3
S2
S1
S0
to realize vertical scrolling
0
0
0
1
0
0
0
1
x'
x'
2-byte command
0
0
x'
C6
C5
C4
C3
C2
C1
C0
0
0
0
1
0
0
1
0
x'
x'
2-byte command
0
0
L7
L6
L5
L4
L3
L2
L1
L0
Set partial display line number
0
0
0
1
0
0
1
1
x'
x'
2-byte command
0
0
x'
x'
x'
N4
N3
N2
N1
N0
Release N-line Inversion
0
0
1
1
1
0
0
1
0
0
Reverse Display ON/OFF
0
0
1
0
1
0
0
1
1
REV
Entire Display ON/OFF
0
0
1
0
1
0
0
1
0
EON
DDRAM address control:
Write: column address +1
Set Initial Display Line
Set N-line Inversion
Ver 1.9
D=1: Display ON
2-byte command
Specify the initial display line
Set Initial COM0
Set Partial Display Duty
D=0: Display OFF
Specify the first COM0 to
33/78
move display window
Set N-line inversion register
Exit N-line inversion mode
REV=0: normal display
REV=1: reverse display
EON=0: normal display
EON=1: entire display ON
2007/9/3
ST7541
Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Power Control
0
0
0
0
1
0
1
VC
VR
VF
Set power circuits ON/OFF
Select DC-DC step-up
0
0
0
1
1
0
0
1
DC1
DC0
Select built-in booster step
Select Regulator Register
0
0
0
0
1
0
0
R2
R1
R0
0
0
1
0
0
0
0
0
0
1
0
0
x'
x'
EV5
EV4
EV3
EV2
EV1
EV0
0
0
0
1
0
1
0
B2
B1
B0
Select LCD bias
0
0
1
1
1
1
0
1
1
1
2-byte command
0
0
0
0
0
1
1
0
1
0
Enable High Power Mode
0
0
1
1
1
1
0
0
1
1
2-byte command
0
0
0
0
0
0
1
1
0
1
Controls high driving mode
0
0
1
1
0
0
SHL
x'
x'
x'
Select Electronic Volume
Select LCD bias
High Power Mode
High Power Mode Control
Description
Select the internal resistance
ratio of the regulator resistor
2-byte command
Adjust contrast level
COM bi-directional selection
SHL select
SHL=0: normal direction
SHL=1: reverse direction
SEG bi-direction selection
ADC select
0
0
1
0
1
0
0
0
0
ADC
ADC=0: normal direction
ADC=1: reverse direction
Oscillator ON
0
0
1
0
1
0
1
0
1
1
Set power save mode
0
0
1
0
1
0
1
0
0
P
Release power save mode
0
0
1
1
1
0
0
0
0
1
RESET
0
0
1
1
1
0
0
0
1
0
Set display data length
x'
x'
1
1
1
0
1
0
0
0
(DDL)
x'
x'
D7
D6
D5
D4
D3
D2
D1
D0
Start the built-in oscillator
P=0: normal mode
P=1: sleep mode
Release power save mode
Software reset
Refer to RESET CIRCUIT
2-byte command
Specify the number of data
bytes. (3-Line SPI only)
FRC: 1=3FRC, 0=4FRC
PWM[1:0]:
Set FRC/PWM mode
0
0
1
0
0
1
0
FRC
PWM1 PWM0 (0,0)=(0,1)=9PWM
(1,0)=12PWM
(1,1)=15PWM
NOP
0
0
1
1
1
0
0
0
1
1
No operation
Test Instruction
0
0
1
1
1
1
x'
x'
x'
x'
Don't use this instruction
Ver 1.9
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2007/9/3
ST7541
Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
White palette (1 /2 frame)
0
0
1
0
0
0
1
0
0
0
set PWM pulse width
0
0
WB3
WB2
WB1
WB0
WA3
WA2
WA1
WA0
White palette (3rd/4th frame)
0
0
1
0
0
0
1
0
0
1
set PWM pulse width
0
0
WD3
WD2
WD1
WD0
WC3
WC2
WC1
WC0
Light palette (1st/2nd frame)
0
0
1
0
0
0
1
0
1
0
set PWM pulse width
0
0
LB3
LB2
LB1
LB0
LA3
LA2
LA1
LA0
Light palette (3rd/4th frame)
0
0
1
0
0
0
1
0
1
1
set PWM pulse width
0
0
LD3
LD2
LD1
LD0
LC3
LC2
LC1
LC0
Dark palette (1st/2nd frame)
0
0
1
0
0
0
1
1
0
0
set PWM pulse width
0
0
DB3
DB2
DB1
DB0
DA3
DA2
DA1
DA0
Dark palette (3rd/4th frame)
0
0
1
0
0
0
1
1
0
1
set PWM pulse width
0
0
DD3
DD2
DD1
DD0
DC3
DC2
DC1
DC0
Black palette (1st/2nd frame)
0
0
1
0
0
0
1
1
1
0
set PWM pulse width
0
0
BB3
BB2
BB1
BB0
BA3
BA2
BA1
BA0
Black palette (3rd/4th frame)
0
0
1
0
0
0
1
1
1
1
set PWM pulse width
0
0
BD3
BD2
BD1
BD0
BC3
BC2
BC1
BC0
st
Ver 1.9
nd
35/78
Description
Set white mode palette
1st/2nd frame
Set white mode palette
3rd/4th frame
Set light gray mode palette
1st/2nd frame
Set light gray mode palette
3rd/4th frame
Set dark gray mode palette
1st/2nd frame
Set dark gray mode palette
3rd/4th frame
Set black mode palette
1st/2nd frame
Set black mode palette
3rd/4th frame
2007/9/3
ST7541
COMMAND DESCRIPTION
Mode Set
2-byte instruction to set FR (Frame frequency control) and BE (Booster efficiency control)
st
The 1 Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
1
1
0
0
0
0
nd
The 2
Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
FR3
FR2
FR1
FR0
0
BE
x'
0
Frame Rate
This command is used to set the frame frequency.
FR3
FR2
FR1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
FR0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FR frequency
77 Hz (default)
51 Hz
55 Hz
58 Hz
63 Hz
67 Hz
68 Hz
70 Hz
73 Hz
75 Hz
80 Hz
85 Hz
91 Hz
102 Hz
113 Hz
123 Hz
Booster Efficiency
The ST7541 incorporates software configurable Booster Efficiency Command. It could be used with Voltage multiplier to get
the suitable Vout and Power consumption. Default setting is Level 2.
Flag
BE
Description
0
1
Booster Efficiency Level 1
Booster Efficiency Level 2
Read Display Data
8-bit data from Display Data RAM specified by the column address and page address can be read by this instruction. As the
column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data
from the addressed page. A dummy read is required after loading an address into the column address register. Display Data
cannot be read through the serial interface.
A0
RW
DB7
1
1
Read data
Ver 1.9
DB6
DB5
DB4
36/78
DB3
DB2
DB1
DB0
2007/9/3
ST7541
Write Display Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and
page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to
the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
A0
RW
DB7
1
1
Write data
DB6
DB5
DB4
DB3
DB2
Set Page Address
Set Page Address
Set Column Address
Set Column Address
Data Write
Dummy Data Read
Column = Column + 1
Column = Column + 1
YES
DB1
DB0
Data Read
Data Write Continue ?
Column = Column + 1
NO
Optional Status
YES
Data Read Continue ?
NO
Optional Status
Figure 18 Sequence for Writing Display Data (Left) and Sequence for Reading Display Data (Right)
Ver 1.9
37/78
2007/9/3
ST7541
Read Status
Indicates the internal status of the ST7541
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BUSY
D
RES
MF2
MF1
MF0
DS1
DS0
Flag
Description
BUSY
The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low.
0: chip is active, 1: chip is being busy
D
Indicates display ON / OFF status
0: display OFF, 1: display ON
RES
Indicates the initialization is in progress by RST signal or RESET instruction.
0: chip is active, 1: chip is being reset
MF
Manufacturer ID; recommended value: MF2 MF1 MF0 = [0 0 0]
The value of MF2, MF1 and MF0 will follow the hardware selection.
Display size ID; recommended value: DS1 DS0 = [0 0]
The value of DS1 and DS2 will follow the hardware selection.
DS
ICON Control ON/OFF
This instruction makes ICON enable or disable. By default, ICON display is disabled (ICON= 0). When ICON control register
is set to “1”, ICON display is enabled and page address is set to “16”. Then user can write data for icons. It is impossible to
set the page address to “16” by Set Page Address instruction. Therefore, when writing data for icons, ICON control register
ON instruction would be used to set the page address to “16”. When ICON control register is set to “0”, ICON display is
disabled.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
0
1
ICON
ICON=0: ICON disable (default)
ICON=1: ICON enable & set the page address to 16
Set Page Address
Sets the Page Address of display data RAM from the microprocessor into the page address register. Any RAM data bit can
be accessed when its Page Address and column address are specified. Along with the column address, the Page Address
defines the address of the display RAM to write or read display data. Changing the Page Address doesn't affect the display
status. Set Page Address instruction can not be used to set the page address to “16”. Use ICON control register ON/OFF
instruction to set the page address to “16”.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
P3
P2
P1
P0
P3
P2
P1
P0
Page
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
1
1
1
0
14
1
1
1
1
15
Ver 1.9
38/78
2007/9/3
ST7541
Set Column Address
Sets the Column Address of display RAM from the microprocessor into the column address register. Along with the Column
Address, the Column Address defines the address of the display RAM to write or read display data.
When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically
increased.
Set Column Address MSB
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
0
Y7
Y6
Y5
Set Column Address LSB
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
Y4
Y3
Y2
Y1
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Column Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
1
1
1
1
1
1
0
126
1
1
1
1
1
1
1
127
Set Read-modify-Write
This instruction stops the automatic increment of the column address by the read display data instruction, but the column
address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a
specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Read-modify-Write
instruction.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
0
0
Ver 1.9
39/78
2007/9/3
ST7541
Reset Read-modify-Write
This instruction releases the Read-modify-Write mode, and makes the column address return to its initial value just before
the set Read-modify-Write instruction.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
1
1
1
0
Read-Modify-Write
Set Page Address
Set Column Address (N)
Set Read-modify-Write
Dummy Read
Data Read
Modify Data
No
Data Write (at same Address)
Internal address +1
Finished?
Yes
Release Read-modify-Write
Internal address return to N
Done
Figure 19 Sequence for Read-modify-Write
Display ON / OFF
Turns the display ON or OFF. This command has priority over Entire Display On/Off and Reverse Display On/Off.
Commands are accepted while the display is off, but the visual state of the display does not change.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
1
1
1
DON
DON = 1: display ON
DON = 0: display OFF
Ver 1.9
40/78
2007/9/3
ST7541
Set Initial Display Line
Sets the line address of display RAM to determine the initial display line using 2-byte instruction. The RAM display data is
displayed at the top of row(COM0) of LCD panel.
st
The 1 Instruction
A0
0
nd
The 2
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
0
0
x
x
Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
x
S6
S5
S4
S3
S2
S1
S0
S6
S5
S4
S3
S2
S1
S0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
1
1
3
:
:
:
:
:
:
:
:
1
1
1
1
1
0
0
124
1
1
1
1
1
0
1
125
1
1
1
1
1
1
0
126
1
1
1
1
1
1
1
127
S e ttin g In itia l D is p la y L in e S ta rt
1 st I n s tr u c tio n f o r M o d e s e ttin g
2 nd In s tru c tio n fo r In itia l D is p la y L in e s e ttin g
S e ttin g In itia l D is p la y L in e E n d
Figure 20 Sequence For Setting Initial Display Line
Ver 1.9
41/78
2007/9/3
ST7541
Set Initial COM0
Sets the initial row (COM) of the LCD panel using the 2-byte instruction. By using this instruction, it is possible to realize the
window moving without the change of display data.
st
The 1 Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
0
0
1
x
x
nd
The 2
Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
x
C6
C5
C4
C3
C2
C1
C0
C6
C5
C4
C3
C2
C1
C0
0
0
0
0
0
0
0
COM0
0
0
0
0
0
0
1
COM1
0
0
0
0
0
1
0
COM2
0
0
0
0
0
1
1
COM3
Initial COM0
:
:
:
:
:
:
:
:
1
1
1
1
1
0
0
COM124
1
1
1
1
1
0
1
COM125
1
1
1
1
1
1
0
COM126
1
1
1
1
1
1
1
COM127
S e tt in g I n itia l C O M 0 S ta r t
1 s t I n s tr u c ti o n f o r M o d e s e tt in g
2 n d I n s t r u c ti o n f o r I n i ti a l C O M 0 s e ttin g
S e ttin g I n it ia l C O M 0 E n d
Figure 21 Sequence For Setting Initial COM0
Ver 1.9
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2007/9/3
ST7541
Set Partial Display Duty
Sets the duty within range of 16 ~ 128 (ICON disabled) or 17 to 129 (ICON enabled) to realize partial display by using the
2-byte instruction.
st
The 1 Instruction
A0
0
nd
The 2
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
1
0
x
x
Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
L7
L6
L5
L4
L3
L2
L1
L0
Valid Display Lines
Valid Display Lines
(ICON disabled)
(ICON enabled)
No operation
No operation
0
16 lines
16+1 lines
1
17 lines
17+1 lines
:
:
:
:
1
0
0
100 lines
100+1 lines
:
:
:
:
:
1
1
1
1
127 lines
127+1 lines
0
0
0
0
128 lines
128+1 lines
0
0
0
1
No Operation
No Operation
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
:
:
:
:
:
:
0
1
1
0
0
:
:
:
:
:
0
1
1
1
1
0
0
0
1
0
0
0
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
S e ttin g P a rtia l D is p la y S ta rt
1 s t I n s tr u c tio n fo r M o d e s e ttin g
2 n d I n s tr u c tio n f o r P a rtia l D is p la y D u ty s e ttin g
S e ttin g P a rtia l D is p la y E n d
Figure 22 Sequence For Setting Partial Display
Ver 1.9
43/78
2007/9/3
ST7541
Set N-line Inversion
Sets the inverted line number within range of 3 to 33 to improve the display quality. It controls the phase of the internal LCD
frame signal. To get better performance, the display duty (L) should not be complete divide by N-line setting (N). If “L” can be
complete divide by “N” (assume K = L / N), the factor (K) should not be even number.
st
The 1 Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
1
1
x
x
0
nd
The 2
Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
x
x
x
0
0
0
0
0
N4
N3
N2
N1
N0
Selected n-line inversion
0
0
0
0
0
0-line inversion (frame inversion)
0
0
0
0
1
3-line inversion
0
0
0
1
0
4-line inversion
0
0
0
1
1
5-line inversion
:
:
:
:
:
:
1
1
1
0
1
31-line inversion
1
1
1
1
0
32-line inversion
1
1
1
1
1
33-line inversion
Setting N -line Inversion Start
1 st Instruction for M ode setting
2 nd Instruction for N -line Inversion setting
Setting N -line Inversion End
Figure 23 Sequence For N-line Inversion
Release N-line Inversion
Returns to the frame inversion condition from the n-line inversion condition.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
1
0
0
Ver 1.9
44/78
2007/9/3
ST7541
Reverse Display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the display data RAM.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
1
1
REV
REV
DDRAM data = “00”
DDRAM data = “01”
DDRAM data = “10”
DDRAM data = “11”
0 (Normal)
White (“00”)
Light gray (“01”)
Dark gray (“10”)
Black (“11”)
1 (Reverse)
Black (“11”)
Dark gray (“10”)
Light gray (“01”)
White (“00”)
Entire Display ON / OFF
Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of
the display data RAM are held. This instruction has priority over the Reverse Display ON / OFF instruction.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
1
0
EON
EON
DDRAM data = “00”
DDRAM data = “01”
DDRAM data = “10”
DDRAM data = “11”
0 (Normal)
White (“00”)
Light gray (“01”)
Dark gray (“10”)
Black (“11”)
1 (Entire)
Black (“11”)
Black (“11”)
Black (“11”)
Black (“11”)
Power Control
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power
supply functions can be used simultaneously.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
1
VC
VR
VF
VC
0
1
VR
VF
–
–
0
–
Internal voltage converter circuit is OFF
Internal voltage converter circuit is ON
Internal voltage regulator circuit is OFF
–
1
–
Status of internal power supply circuits
–
Internal voltage regulator circuit is ON
0
Internal voltage follower circuit is OFF
1
Internal voltage follower circuit is ON
Select DC-DC Step-up
Selects one of 4 DC-DC step-up to reduce the power consumption by this instruction. It is very useful to realize the partial
display function.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
1
0
0
1
DC1
DC0
Ver 1.9
DC1
DC0
Selected DC-DC converter circuit
0
0
3 times boosting circuit
0
1
4 times boosting circuit
1
0
5 times boosting circuit
1
1
6 times boosting circuit
45/78
2007/9/3
ST7541
Select Regulator Resistor
Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power
supply circuit.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
0
R2
R1
R0
R2
R1
R0
1+ (Rb / Ra)
0
0
0
2.3
0
0
1
3.0
0
1
0
3.7
0
1
1
4.4
1
0
0
5.1
1
0
1
5.8
1
1
0
6.5
1
1
1
7.2
Set Electronic Volume
Consist of 2-byte Instructions. The 1st instruction set Reference Voltage mode, the 2nd one updates the contents of
reference voltage register. After second instruction, Reference Voltage mode is released.
st
The 1 Instruction: Set Reference Voltage Select Mode
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
0
0
0
0
1
0
nd
The 2
Instruction: Set Reference Voltage Register
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
x
x
EV5
EV4
EV3
EV2
EV1
EV0
EV5
EV4
EV3
EV2
EV1
EV0
Reference voltage parameter (a)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
High Power Mode Enable
This 2-byte Instruction enables the high power mode. The high power mode control command is valid after this
2-byte Instruction.
st
The 1 Instruction
A0
0
nd
The 2
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
1
0
1
1
1
Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
1
0
Ver 1.9
46/78
2007/9/3
ST7541
High Power Mode Control
This double command controls the high power mode. The driving strength is enhanced and the current
consumption will be larger.
st
The 1 Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
1
0
0
1
1
0
nd
The 2
Instruction
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
1
0
1
Select LCD Bias
Selects LCD bias ratio of the voltage required for driving the LCD.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
1
0
B2
B1
B0
B2
B1
B0
LCD bias
0
0
0
1/5
0
0
1
1/6
0
1
0
1/7
0
1
1
1/8
1
0
0
1/9
1
0
1
1/10
1
1
0
1/11
1
1
1
1/12
SHL Select
COM output scanning direction is selected by this instruction which determines the LCD driver output status.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
0
0
SHL
x
x
x
SHL = 0: normal direction (COM0 → COM127)
SHL = 1: reverse direction (COM127 → COM0)
ADC Select
Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins
could be reversed by software. This makes IC layout flexible in LCD module assembly.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
0
0
ADC
ADC = 0: normal direction (SEG0 → SEG127)
ADC = 1: reverse direction (SEG127 → SEG0)
Oscillator ON
This instruction enables the built-in oscillator circuit.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
1
0
1
1
Ver 1.9
47/78
2007/9/3
ST7541
Power Save
The ST7541 enters the Power Save status to reduce the power consumption to the static power consumption value and
returns to the normal operation status by the following instructions.
Set Power Save Mode
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
1
0
0
P
P = 0: normal mode , P = 1: sleep mode
Release Power Save Mode
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
0
1
Set Power Save Mode (Sleep Mode)
Sleep Mode
Oscillator Circuit: OFF
LCD Power Supply Circuit: OFF
All COM / SEG Output Level: VSS
Consumption Current < 2uA
Release Power Save Mode (Sleep Mode)
Figure 24 Power Save Routine
RESET
RESET instruction initial display line, column address, page address, and common output status select to their initial status,
but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is
initialized by the RST pin.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
1
0
Ver 1.9
48/78
2007/9/3
ST7541
Set Display Data Length (3-Line SPI Mode)
Consists of 2 bytes instruction.
This command is used in 3-Line SPI mode only(PS0 = ”L” and PS1 = ”L” ). It will be two continuous commands, the first byte
control the data direction(write mode only) and inform the LCD driver the second byte will be number of data bytes will be
write. When A0 is not used, the Display Data Length instruction is used to indicate that a specified number of display data
bytes are to be transmitted. The next byte after the display data string is handled as command data.
st
The 1 Instruction: Set Data Direction (Only Write Mode)
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
x
1
1
1
0
1
0
0
0
X
nd
The 2
Instruction: Set Display Data Length (DDL) Register
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
x
x
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Display Data Length
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
1
0
3
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
0
1
254
1
1
1
1
1
1
1
0
255
1
1
1
1
1
1
1
1
256
Set PWM & FRC mode
Selects 3/4 FRC and 9 / 12 / 15 PWM
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
1
0
FRC
PWM1
PWM0
FRC
PWM1
PWM0
–
–
0
0 or 1
9PWM
1
0
12PWM
1
1
15PWM
0
1
–
Status of PWM & FRC
4FRC
3FRC
NOP
No operation
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
1
1
Test Instruction
This instruction is for testing IC. Please do not use it.
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
1
x
x
x
x
Ver 1.9
49/78
2007/9/3
ST7541
Set Gray Scale Mode & Register
Consists of 2 bytes instruction. The first byte sets grayscale mode and the second byte updates the contents of gray scale
register without issuing any other instruction.
− Set Gray Scale Mode
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
0
1
GM2
GM1
GM0
GM2
0
0
0
0
1
1
1
1
GM1
0
0
1
1
0
0
1
1
GM0
0
1
0
1
0
1
0
1
DB1
DB0
Description
st
nd
In case of setting whit mode and 1 / 2 frame
rd
th
In case of setting whit mode and 3 / 4 frame
st
nd
In case of setting light gray mode and 1 / 2 frame
rd
th
In case of setting light gray mode and 3 / 4 frame
st
nd
In case of setting dark gray mode and 1 / 2 frame
rd
th
In case of setting dark gray mode and 3 / 4 frame
st
nd
In case of setting black mode and 1 / 2 frame
rd
th
In case of setting black mode and 3 / 4 frame
--Set Gray Scale Register
A0
RW
DB7
DB6
DB5
DB4
DB3
DB2
0
0
GB3
GB2
GB1
GB0
GA3
GA2
GA1
GA0
0
0
GD3
GD2
GD1
GD0
GC3
GC2
GC1
GC0
Pulse width
Pulse width
Pulse width
GA3, GB3, GA2, GB2, GA1, GB1, GA0, GB0,
GC3, GD3 GC2, GD2 GC1, GD1 GC0, GD0
(9 PWM)
(12 PWM)
(15 PWM)
0
0
0
0
0/9
0/12
0/15
0
0
0
1
1/9
1/12
1/15
:
:
:
:
:
:
:
1
0
0
1
9/9
9/12
9/15
1
0
1
0
0/9
10/12
10/15
1
0
1
0
0/9
11/12
11/15
1
1
0
0
0/9
12/12
12/15
1
1
0
1
0/9
0/12
13/15
1
1
1
0
0/9
0/12
14/15
1
1
1
1
0/9
0/12
15/15
* GA3=WA3, LA3, DA3, BA3 GA2=WA2, LA2, DA2, BA2 GA1=WA1, LA1, DA1, BA1 GA0=WA0, LA0, DA0, BA0
GB3=WB3, LB3, DB3, BB3 GA2=WB2, LB2, DB2, BB2 GA1=WB1, LB1, DB1, BB1 GA0=WB0, LB0, DB0, BB0
GC3=WC3, LC3, DC3, BC3 GA2=WC2, LC2, DC2, BC2 GA1=WC1, LC1, DC1, BC1 GA0=WC0, LC0, DC0, BC0
GD3=WD3, LD3, DD3, BD3 GA2=WD2, LD2, DD2, BD2 GA1=WD1, LD1, DD1, BD1 GA0=WD0, LD0, DD0, BD0
Ver 1.9
50/78
2007/9/3
ST7541
COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
Figure 25 Initializing with the Built-in Power Supply Circuits
Ver 1.9
51/78
2007/9/3
ST7541
Referential Instruction Setup Flow: Initializing without the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON(VDD-VSS) Keeping the RST Pin="L"
Waiting for Stabilizing the Power
RST Pin="H"
Set Power Save
User Application Setup by Internal Instructions
[Display Duty Select]
[ADC Select]
[SHL Select]
[COM0 Register Select]
User LCD Power Setup by Internal Instructions
[Oscillator ON]
[Regulator Resistor]
[Electronic Volume Register Select]
[LCD Bias Register Select]
[Power Control VC,VR,VF=0,0,0]
Release Power Save
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 26 Initializing without Built-in Power Supply Circuits
Ver 1.9
52/78
2007/9/3
ST7541
Referential Instruction Setup Flow: Data Displaying
End of Initialization
Display Data RAM Addressing by Instruction
[Initial Display Line]
[Set Page Address]
[Set Column Address]
Write Display Data by Instruction
[Display Data Write]
Turn Display ON/OFF Instruction
[Display ON/OFF]
End of Data Display
Figure 27 Data Displaying
Referential Instruction Setup Flow: Power OFF
Optional Status
Set Power Save by Instruction
Power OFF(VDD-VSS)
End of Power OFF
Figure 28 Power OFF
Ver 1.9
53/78
2007/9/3
ST7541
LIMITING VALUES
In accordance with the Absolutely Maximum Rating System, please refer to note 1 and 2.
Parameter
Symbol
Conditions
Unit
Power Supply Voltage
VDD
–0.3 ~ +3.6
V
Power supply voltage
VDD2
1.7 ~ 3.3
V
Power supply voltage
V0
3.5 ~ 15
V
Power supply voltage
VOUT_IN
–0.5 ~ +20
V
Power supply voltage
V1, V2, V3, V4
0.3 to VOUT_IN
V
VIN
–0.5 to VDD+0.5
V
Input voltage
Output voltage
VO
–0.5 to VDD+0.5
V
Operating temperature
TOPR
–30 to +85
°C
Storage temperature
TSTR
–65 to +150
°C
VLCD
V1 to V4
VDD
VDD
VSS
VSS
System (MPU) side
VSS
ST7541 chip side
Note:
1.
Stresses above those listed under Limiting Values may cause permanent damage to the device.
2.
Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS
unless otherwise noted.
3.
Insure that the voltage levels of V1, V2, V3, and V4 are always such that
VOUT_IN ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ Vss
Ver 1.9
54/78
2007/9/3
ST7541
DC CHARACTERISTICS
VDD = 1.8 V to 3.3V; VSS = 0 V; VLCD = 3.5 to 15.0V; Tamb=–30~+85°C; unless otherwise specified.
Item
Symbol
Condition
Rating
Min.
Typ.
Max.
Units
Applicabl
e Pin
Operating Voltage (1)
VDD
1.8
—
3.3
V
VDD*1
Operating Voltage (2)
VDD2
2.4
—
3.3
V
VDD2
High-level Input Voltage
VIHC
0.7 x VDD
—
VDD
V
*2
Low-level Input Voltage
VILC
VSS
—
0.3 x VDD
V
*2
High-level Output Voltage
VOHC
0.7 x VDD
—
VDD
V
*3
Low-level Output Voltage
VOLC
VSS
—
0.3 x VDD
V
*3
Input leakage current
ILI
VIN = VDD or VSS
–1.0
—
1.0
μA
*4
Output leakage current
ILO
VIN = VDD or VSS
–3.0
—
3.0
μA
*5
—
2.0
3.5
VOUT_IN
Liquid Crystal Driver ON
RON
Resistance
Ta = 25°C
= 15.0 V
VOUT_IN
= 8.0 V
Internal
fOSC
Oscillator
Oscillator
Frequency
External
fCL
Input
Frame Rate
Item
Step-up Circuit output
voltage
Voltage regulator
operating Voltage
Ver 1.9
1/128 duty
SEGn
COMn *6
—
3.2
5.4
—
443.5
462.5
kHz
*7
—
88.7
92.5
kHz
OSC
—
77
85
Hz
Ta = 25°C
9 PWM
fFRAME
Symbol
KΩ
Condition
Rating
Units
Applicable Pin
15
V
VOUT_OUT
15
V
VOUT_IN
Min.
Typ.
Max.
VOUT_OUT
—
—
VOUT_IN
—
—
55/78
2007/9/3
ST7541
Bare Dice Consumption Current : During Display, with the Internal Power Supply, Current consumed by total ICs when an
external power supply(VDD,VDD2) is used .
Test pattern
Symbol
Condition
Rating
Units
Notes
650
μA
*8
2
μA
*9
Min.
Typ.
Max.
—
550
—
0.01
VDD = 3.3 V,
Display Pattern SNOW
ISS
V0 – VSS = 10.7 V
5X booster
1/11 bias
Power Down
ISS
Ta = 25°C
Notes to the DC characteristics
1. The maximum possible VOUT voltage that may be generated is dependent on voltage, temperature and (display) load.
2. Internal clock
3. Power-down mode. During power down all static currents are switched off.
4. If external VLCD, the display load current is not transmitted to IDD.
5. VOUT external voltage applied to VOUT_IN pin; VOUT_IN disconnected from VOUT_OUT
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage while the MPU is being accessed.
*2 The A0, D0 to D5, D6 (SI), D7 (SCL), /RD (E), /WR ,/(R/W), CSB, IMS, OSC, P/S, /DOF, RST ,and MODE terminals.
*3 The D0 to D7, and OSC terminals.
*4 The A0,/RD (E), /WR ,/(R/W), CSB, IMS, OSC, P/S, /DOF, RST ,and MODE terminals.
*5 Applies when the D0 to D5, D6 (SI), D7 (SCL) terminals are in a high impedance state.
*6 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the
various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range.
RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.)
*7 The relationship between the oscillator frequency and the frame rate frequency.
*8,9 It indicates the current consumed on IC alone when the internal oscillator circuit and display are turned on.
Ver 1.9
56/78
2007/9/3
ST7541
TIMING CHARACTERISTICS
System Bus Read/Write Characteristics (For the 8080 Series MPU)
Figure 29
(VDD = 3.3V, Ta=–30~85°C)
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Write L pulse width
Write H pulse width
Read L pulse width
Read H pulse width
/WR
/RD
Data setup time (Write)
Write Data hold time (Write)
Data access time (Read)
Output disable time (Read)
Ver 1.9
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH8
0
—
tAW8
0
—
tCYC8
240
—
tCCLW
80
—
tCCHW
80
—
tCCLR
140
—
tCCHR
80
tDS8
40
—
tDH8
10
—
tACC8
CL = 100 pF
—
70
tOH8
CL = 100 pF
5
50
57/78
Units
ns
2007/9/3
ST7541
(VDD = 2.7V, Ta=–30~85°C)
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Write L pulse width
Write H pulse width
Read L pulse width
Read H pulse width
/WR
/RD
Data setup time (Write)
Write Data hold time (Write)
Data access time (Read)
D0 to D7
Output disable time (Read)
Symbol
Condition
Rating
Min.
Max.
tAH8
0
—
tAW8
0
—
tCYC8
400
—
tCCLW
220
—
tCCHW
180
—
tCCLR
220
—
tCCHR
180
—
tDS8
40
—
tDH8
15
—
tACC8
CL = 100 pF
—
140
tOH8
CL = 100 pF
10
100
Units
ns
(VDD = 1.8V, Ta=–30~85°C)
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Write L pulse width
Write H pulse width
Read L pulse width
Read H pulse width
/WR
/RD
Data setup time (Write)
Write Data hold time (Write)
Data access time (Read)
Output disable time (Read)
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH8
0
—
tAW8
0
—
tCYC8
640
—
tCCLW
360
—
tCCHW
280
—
tCCLR
360
—
tCCHR
280
tDS8
80
—
tDH8
30
—
tACC8
CL = 100 pF
—
240
tOH8
CL = 100 pF
10
200
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
Ver 1.9
58/78
2007/9/3
ST7541
System Bus Read/Write Characteristics (For the 6800 Series MPU)
Figure 30
(VDD = 3.3 V, Ta=–30~85°C)
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH6
0
—
tAW6
0
—
System cycle time
tCYC6
240
—
Enable L pulse width (WRITE)
tEWLW
80
—
tEWHW
80
—
tEWLR
80
—
Enable H pulse width (READ)
tEWHR
140
WRITE Data setup time
tDS6
40
—
tDH6
10
—
Address hold time
Address setup time
Enable H pulse width (WRITE)
Enable L pulse width (READ)
WRITE Data hold time
READ access time
READ Output disable time
Ver 1.9
A0, R/W
E
D0 to D7
tACC6
CL = 100 pF
—
70
tOH6
CL = 100 pF
5
50
59/78
Units
ns
2007/9/3
ST7541
(VDD = 2.7V, Ta=–30~85°C)
Item
Signal
Symbol
Rating
Condition
Min.
Max.
tAH6
0
—
tAW6
0
—
System cycle time
tCYC6
400
—
Enable L pulse width (WRITE)
tEWLW
220
—
tEWHW
180
—
tEWLR
220
—
Enable H pulse width (READ)
tEWHR
180
—
WRITE Data setup time
tDS6
40
—
tDH6
15
—
Address hold time
Address setup time
Enable H pulse width (WRITE)
Enable L pulse width (READ)
WRITE Data hold time
READ access time
A0, R/W
E
D0 to D7
READ Output disable time
tACC6
CL = 100 pF
—
140
tOH6
CL = 100 pF
10
100
Units
ns
(VDD =1.8V, Ta=–30~85°C)
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH6
0
—
tAW6
0
—
System cycle time
tCYC6
640
—
Enable L pulse width (WRITE)
tEWLW
360
—
tEWHW
280
—
tEWLR
360
—
Enable H pulse width (READ)
tEWHR
280
—
WRITE Data setup time
tDS6
80
—
tDH6
30
—
Address hold time
Address setup time
Enable H pulse width (WRITE)
Enable L pulse width (READ)
WRITE Data hold time
READ access time
READ Output disable time
A0, R/W
E
D0 to D7
tACC6
CL = 100 pF
—
240
tOH6
CL = 100 pF
10
200
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CSB being “L” and E.
Ver 1.9
60/78
2007/9/3
ST7541
Serial Interface (4-Line Interface)
First bit
Last bit
Figure 31
(VDD=3.3V, Ta=–30~85°C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
A0
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
50
—
tSHW
25
—
tSLW
25
—
tSAS
20
—
tSAH
10
—
tSDS
20
—
tSDH
10
—
tCSS
20
—
tCSH
40
—
Units
ns
(VDD=2.7V, Ta=–30~85°C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
Ver 1.9
A0
SI
CSB
Symbol
Condition
Rating
Min.
Max.
tSCYC
100
—
tSHW
50
—
tSLW
50
—
tSAS
30
—
tSAH
20
—
tSDS
30
—
tSDH
20
—
tCSS
30
—
tCSH
60
—
61/78
Units
ns
2007/9/3
ST7541
(VDD=1.8V, Ta=–30~85°C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
A0
SI
CSB
Symbol
Condition
Rating
Min.
Max.
tSCYC
200
—
tSHW
80
—
tSLW
80
—
tSAS
60
—
tSAH
30
—
tSDS
60
—
tSDH
30
—
tCSS
40
—
tCSH
100
—
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.9
62/78
2007/9/3
ST7541
Serial Interface (3-Line Interface)
First bit
Last bit
Figure 32
(VDD=3.3V, Ta=–30~85°C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
50
—
tSHW
25
—
tSLW
25
—
tSDS
20
—
tSDH
10
—
tCSS
20
—
tCSH
40
—
Units
ns
(VDD=2.7V, Ta=–30~85°C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
100
—
tSHW
50
—
tSLW
50
—
tSDS
30
—
tSDH
20
—
tCSS
30
—
tCSH
60
—
Units
ns
(VDD=1.8V, Ta=–30~85°C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
Symbol
Condition
Rating
Min.
Max.
tSCYC
200
—
tSHW
80
—
SCL “L” pulse width
tSLW
80
—
Data setup time
tSDS
60
—
tSDH
30
—
tCSS
40
—
tCSH
100
—
Data hold time
CS-SCL time
CS-SCL time
SI
CSB
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.9
63/78
2007/9/3
ST7541
Serial Interface (IIC Interface)
(VDD=3.3V, Ta=–30~85°C)
Item
Signal Symbol
Rating
Condition
Min.
Max.
Units
SCL clock frequency
SCL
FSCLK
-
400
kHZ
SCL clock low period
SCL
TLOW
1.3
-
us
SCL clock high period
SCL
THIGH
0.6
-
us
Data set-up time
SI
TSU;Data
100
-
ns
Data hold time
SI
THD;Data
0
0.9
us
SCL,SDA rise time
SCL
TR
20+0.1Cb 300
ns
SCL,SDA fall time
SCL
TF
20+0.1Cb 300
ns
Cb
-
400
pF
Setup time for a repeated START condition
SI
TSU;SUA
0.6
-
us
Start condition hold time
SI
Capacitive load represented by each bus line
THD;STA
0.6
-
us
Setup time for STOP ondition
TSU;STO
0.6
-
us
Tolerable spike width on bus
TSW
-
50
ns
TBUF
1.3
BUS free time between a STOP and StART condition
Ver 1.9
SCL
64/78
us
2007/9/3
ST7541
RESET TIMING
tRW
RST
tR
Internal
Status
During Reset ...
Reset Finished
Figure 33
(VDD = 3.3V, Ta=–30~85°C)
Item
Signal
Reset time
Reset “L” pulse width
RST
Symbol
Condition
Rating
Max.
Units
Min.
Typ.
tR
—
—
1
us
tRW
1
—
—
us
(VDD = 2.7V, Ta=–30~85°C)
Item
Signal
Reset time
Reset “L” pulse width
RST
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
1.5
us
tRW
1.5
—
—
us
(VDD = 1.8V, Ta=–30~85°C)
Item
Signal
Reset time
Reset “L” pulse width
Ver 1.9
RST
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
2.0
us
tRW
2.0
—
—
us
65/78
2007/9/3
ST7541
POWER PAD CONNECT
The pinning of the ST7541 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display
size: 129 X 128 pixels.
Display 129 X 128 pixels
COM
COM
VOUT_OUT
VOUT_IN
SEG
VSS1
VSS2
VDD2
VDD
ST7541
*6 if external oscillator 5
Cvout
I/O
CVDD VSS
VDD
Figure 34 Application diagram: internal charge pump is used and s single
VDD
Display 129 X 128 pixels
COM
COM
VOUT_OUY
VOUT_IN
SEG
*6 if external oscillator 5
VSS1
VSS2
VDD2
VDD
ST7541
VDD1 CVDD1
Cvout
I/O VDD2
CVDD2 VSS
Figure 35 Application diagram: Internal charge pump is used and two
separate VDD(VDD2)
Ver 1.9
66/78
2007/9/3
ST7541
Display 129 X 128 pixels
SEG
COM
VSS1
VSS2
VDD2
VDD1
ST7541
*6 if external oscillator 5
VOUT_OUT
VOUT_IN
COM
VL2
I/O VDD2
CVDD VSS
Figure 36 application diagram: External high voltage generation is used
The required minimum value for the external capacitors in an application with the ST7541 are: CVLCD = min. 100nF
min. 1.0 μF
CVDD,2=
Higher capacitor values are recommended for ripple reduction.
Ver 1.9
67/78
2007/9/3
ST7541
THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7541 Series can be connected to either60X86 Series MPUs or to 6800Swries MPUs. Moreover, using the serial
interface it is possible to operate the ST7541 series chips with fewer signal lines.
The display area can be enlarged by using multiple ST7541 Series chips. When this is done, the chip select signal can be
used to select the individual Ics to access.
(1) 8080 Series MPUs
VDD
VCC
VDD
A0
A0
MPU
D0 to D7
E (/RD)
R/W (/WR)
/RES
DO to D7
RD
WR
RES
GND
ST7541
CSB
CS1
VSS
RESET
VSS
(2) 6800 Series MPUs
V DD
V CC
A0
MPU
DO to D7
E
R/W
RES
ST7541
CSB
CS1
GND
V DD
IM S
A0
D0 to D7
/RD (E)
/W R (R/W )
/RES
PS
V SS
RESET
V SS
(3) Using the Serial Interface (4-line interface)
V DD
VCC
V DD
A0
C SB
P ort 1
P ort 2
R ES
SI
SC L
/R E S
MPU
CS1
ST7541
A0
GND
V SS
R E SET
V SS
Ver 1.9
68/78
2007/9/3
ST7541
(4) Using the Serial Interface (3-line interface)
V DD
V DD
CSB
Port 1
Port 2
RES
SI
SCL
/RES
MPU
CS1
ST7541
V CC
GND
V SS
RESET
V SS
(5) Using the Serial Interface (IIC interface)
V DD
V DD
V CC
R
Port 1
Port 2
RES
ST7541
MPU
R
SDA
SCL
/RES
RESET
V SS
GND
V SS
Ver 1.9
69/78
2007/9/3
ST7541
APPLICATION Program Example
4-Gray programming example for ST7541
SETP
0
1
2
SERIAL BUS BYTE
Start
3.b
CSB IS going low.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Mode Set.
0
0
1
1
1
0
0
FR[3:0] = 0000
0
0
0
0
0
0
1
x’
0
BE= 1
0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
1
0
1
OSC ON
1
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Set DC-DC Step up
0
Set Vout
0
1
1
0
0
1
DC1 DC0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Set Ra/Rb
0
Set R[2:0]
0
0
1
0
0
R2
R1
R0
Set EV
3.c A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
3.d
OPERATION
0
0
3.a
DISPLAY
0
1
0
0
0
x’
x’
Ev5
0
0
Ev4
0
Ev3
0
1
Ev2
Ev1
Set Ev[5:0]
Ev0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Set Bias
0
Set B[2:0]
0
1
0
1
0
B2
B1
B0
4.a
SET pulse width of Gray scale
Gray-Scale Setting
4.b
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Mode Set.
5.a
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
x’
0
0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SET Power Control
0
Booster ON
0
0
1
0
1
1
1
1
Regulator ON
Follower ON
5.b
6
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display control.
0
Display on
1
0
1
0
1
1
1
1
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Data Write.
1
0
0
1
0
0
1
1
0
Y,X are initialized to 0 by
1
0
0
1
0
0
1
1
0
default, so they aren’t set
here…
7
8
9
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
Ver 1.9
Data Write.
70/78
2007/9/3
ST7541
10
11
12
13
14
15
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display Control.
0
Set Reverse display mode
1
0
1
0
0
1
1
1
REV=1
16
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Set column address of RAM.
0
0
0
0
1
0
0
0
0
Set address to “00000000”.
0
0
0
0
0
0
0
0
0
Y[7:0]=00000000
(Y0 default is 0)
17
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Ver 1.9
Data Write.
71/78
2007/9/3
ST7541
programming example for ST7541(Use IIC Interface)
SETP
1
2
3
4
SERIAL BUS BYTE
DISPLAY
IIC INTERFACE Start
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Slave address for write
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Control byte with cleared Co
0
0
0
0
0
0
0
0
bit and A0 set to logic 0
Mode Set.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
1
1
0
0
0
0
0
0
1
0
x’
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
6.a
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
6.b
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
6.c
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
1
0
1
1
1
1
0
0
x’
x’
Ev5
0
0
0
0
1
0
0
1
0
0
Ev3
0
1
Ev2
Ev1
7.a
SET pulse width of Gray scale
7.b
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
Set DC-DC Step up
B2
B1
Set Vout
Set Ra/Rb
R0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
OSC ON
1
6.d
0
BE= 1
DC1 DC0
R2 R1
0
Ev4
1
FR[3:0] = 0000
0
0
5
8.a
OPERATION
Set R[2:0]
Set EV
Set Ev[5:0]
Ev0
Set Bias
B0
Set B[2:0]
Gray-Scale Setting
0
0
1
1
1
0
0
0
0
0
0
0
1
x’
Mode Set.
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
0
1
1
1
SET Power Control
1
Booster ON
Regulator ON
Follower ON
8.b
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
9
10
11
0
1
0
1
1
1
Display control.
1
Display on
IIC INTERFACE Start
restart
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Slave address for write
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Control byte with clear Co bit
0
1
0
0
0
0
0
0
and A0 set to logic 1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
12
0
0
1
0
0
1
1
0
Y,X are initialized to 0 by
0
0
1
0
0
1
1
0
default, so they aren’t set
here…
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
13
Ver 1.9
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
Data Write.
72/78
2007/9/3
ST7541
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
14
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
15
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
16
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
0
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
18
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
19
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
20
21
22
23
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
Data Write.
IIC INTERFACE start
restart
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Slave address for write
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Control byte with set Co bit
1
0
0
0
0
0
0
0
and A0 set to logic 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
1
1
Display Control.
1
Set Reverse display mode
24
25
REV=1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Ver 1.9
1
0
0
0
0
0
0
Control byte with set Co bit
0
and A0 set to logic 0
73/78
2007/9/3
ST7541
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
26
Set column address of RAM.
0
0
0
1
0
0
0
0
Set address to “00000000”.
0
0
0
0
0
0
0
0
Y[7:0]=00000000
(Y0 default is 00)
27
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
1
0
0
0
0
0
Control byte with set Co bit
0
and A0 set to logic 1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Write.
IIC INTERFACE start
restart
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Slave address for write
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Control byte with set Co bit
1
0
0
0
0
0
0
0
and A0 set to logic 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
Set X address of RAM.
0
Set address to “0000000”.
32
33
Control byte with cleared Co
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Ver 1.9
1
0
0
0
0
0
0
bit and A0 set to logic 0
0
74/78
2007/9/3
ST7541
ST7541 APPICATION NOTE
ST7541
Internal analog circuit
Resolution : 129(128COM+ICOM)*128(SEG)
Interface:8080 series
OSC1:External for input
(the same pin shoud be connected together,
for example,pin246(D0) connect to pin247(D0)
exclude power pin)
PS0:VDD
PS1:VSS
PS2:VSS
TA:VSS
TB:VSS
REF:VDD
INTRS:VDD
VR:OPEN
VEXT:OPEN
T0~T9:OPEN
MF[2:0]:VDD OR VSS=(0,0,0)
DS[1:0]:VDD OR VSS=(0,0)
(MF[2:0]&DS[1:0] is ID of this
IC,
these pins cannot be left open)
C=1uF
365
COM52
353
COM63
351~352
V0
350
V1
349
V2
348
V3
347
V4
345~346
VR
344
VDD
342~343
OSC1
341
VSS
340
INTRS
31
COM0
339
VDD
32
COMS1
338
VEXT
33
SEG0
337
VSS
336
REF
335
VDD
T8~T0
320~325
VOUT_IN
314~319
VOUT_OUT
313
VDD
DS0
310
MF0
309
MF1
308
MF2
21
V0
307
TB
20
V1
306
TA
19
V2
300~305
VSS
18
V3
284~299
VSS2
17
V4
268~283
VDD2
262~267
VDD
16
VOUT
260~261
D7
15
D7
258~259
D6
14
D6
256~257
D5
13
D5
254~255
D4
12
D4
252~253
D3
11
D3
D2
160
SEG127
250~251
D2
10
161~164
RESERVE
248~249
D1
9
165
COM64
246~247
D0
8
D0
244~245
E_RD
7
E_RD
242~243
RW_WR
6
RW_WR
A0
5
A0
RST
4
RST
236~237
CSB
3
CSB
235
VSS
2
VSS
234
PS2
1
VDD
233
PS1
232
PS0
231
VDD
230
T9
COMS2
228
COM127
217
197
................
218
COM117
COM 116
C OM 96
COM95
... ........... ..
229
... ........... ..
.. ........... ........... ................................
196
D1
238~239
240~241
C C C
DS1
311
C
ST7541
312
C
... ........... ........... ...................... ........
... ........... ........... ...................... ........
326~334
........ ........... .......... ...................... .....
..... .......
364
..... .......
................
COM 51
COM30
.......... ........... .......... ...........
.......... ........... .......... ...........
1
COM 31
385
................
................
Ver 1.9
75/78
2007/9/3
ST7541
ST7541
Internal analog circuit
Resolution : 129(128COM+ICOM)*128(SEG)
Interface : 4 SPI
OSC1:External for input
(if use internal oscillator,OSC1 must be fixed to VDD)
(the same pin shoud be connected together,
for example,pin246(D0) connect to pin247(D0))
VR:OPEN
VEXT:OPEN
T0~T9:OPEN
MF[2:0]:VDD OR VSS=(0,0,0)
DS[1:0]:VDD OR VSS=(0,0)
(MF[2:0]&DS[1:0] is ID of this IC,
these pins cannot be left open)
C=1uF
PS0:VSS
PS1:VDD
PS2:VSS
TA:VSS
TB:VSS
REF:VDD
INTRS:VDD
365
364
COM52
COM63
351~352
V0
350
V1
V2
348
V3
347
V4
VR
345~346
344
VDD
342~343
OSC1
341
VSS
340
INTRS
339
VDD
COMS1
338
VEXT
SEG0
337
VSS
336
REF
335
VDD
326~334
T8~T0
320~325
VOUT_IN
314~319
VOUT_OUT
313
VDD
ST7541
.......................................................
312
DS1
311
DS0
310
MF0
309
MF1
308
MF2
22
V0
307
TB
21
V1
306
TA
20
V2
300~305
VSS
19
284~299
VSS2
18
V4
268~283
VDD2
17
OSC1
262~267
VDD
16
VOUT
260~261
D7
15
SID
258~259
D6
14
SCLK
256~257
D5
13
254~255
D4
12
252~253
D3
11
160
SEG127
250~251
D2
10
161~164
RESERVE
248~249
D1
9
165
COM64
246~247
D0
8
244~245
E_RD
7
242~243
RW_WR
6
240~241
A0
5
238~239
RST
4
RST
236~237
CSB
3
CSB
235
VSS
2
VSS
234
PS2
1
VDD
233
PS1
232
PS0
231
VDD
230
T9
COM127
................
COMS2
228
................
229
A0
217
197
................
218
COM117
COM116
COM95
COM96
196
V3
C
33
C
32
C
COM0
C
31
C
..........................................
353
349
........................................................
..........................................
.......................................................
........................................................
............
................
............
COM30
COM51
1
COM31
385
................
................
Ver 1.9
76/78
2007/9/3
ST7541
ST7541
Internal analog circuit
Resolution : 129(128COM+ICOM)*128(SEG)
Interface : I2C
OSC1:External for input
(the same pin shoud be connected together,
for example,pin246(D0) connect to pin247(D0)
exclude power pin)
SA[1:0]:VDD OR VSS=(0,0)
(SA[1:0] are Slave address of I2C)
PS0:VSS
PS1:VSS
PS2:VDD
TA:VSS
TB:VSS
REF:VDD
INTRS:VDD
VR:OPEN
VEXT:OPEN
T0~T9:OPEN
MF[2:0]:VDD OR VSS=(0,0,0)
DS[1:0]:VDD OR VSS=(0,0)
(MF[2:0]&DS[1:0] is ID of this IC,
these pins cannot be left open)
C=1uF ; R=10K歐姆
365
364
COM52
COM63
351~352
V0
350
V1
349
V2
348
V3
347
V4
345~346
VR
344
VDD
342~343
OSC1
341
VSS
340
INTRS
339
VDD
COMS1
338
VEXT
SEG0
337
VSS
VDD
T8~T0
320~325
VOUT_IN
314~319
VOUT_OUT
313
VDD
DS0
310
MF0
309
MF1
308
MF2
11
V0
307
TB
10
V1
306
TA
9
V2
300~305
VSS
8
V3
284~299
VSS2
7
V4
268~283
VDD2
262~267
VDD
6
VOUT
260~261
D7(SCL)
5
SCL
258~259
D6(SDA_IN)
4
SDA
256~257
D5(SDA_IN)
254~255
D4(SDA_IN)
3
RST
252~253
D3(SDA_OUT)
160
SEG127
250~251
D2(SDA_OUT)
161~164
RESERVE
248~249
D1(SA1)
165
COM64
246~247
D0(SA0)
244~245
E_RD
242~243
RW_WR
A0
238~239
RST
236~237
CSB
235
VSS
2
VSS
234
PS2
1
VDD
233
PS1
232
PS0
231
VDD
230
T9
COMS2
228
COM127
217
197
................
218
COM117
CO M116
COM96
COM95
........... .....
229
........... .....
........................................................
240~241
196
C
ST7541
DS1
311
C
312
...... ........... ......................................
...... ........... ......................................
REF
335
326~334
C
33
C
32
C
COM0
R
31
R
................. ...................... ...
................. ...................... ...
353
336
........................................................
............
................
............
COM30
COM51
1
COM31
385
................
................
Ver 1.9
77/78
2007/9/3
ST7541
ST7541
Internal analog circuit
Resolution : 129(128COM+ICOM)*128(SEG)
Interface : 3 SPI
OSC1:External for input
(the same pin shoud be connected together,
for example,pin246(D0) connect to pin247(D0)
exclude power pin)
PS0:VSS
PS1:VDD
PS2:VSS
TA:VSS
TB:VSS
REF:VDD
INTRS:VDD
VR:OPEN
VEXT:OPEN
T0~T9:OPEN
MF[2:0]:VDD OR VSS=(0,0,0)
DS[1:0]:VDD OR VSS=(0,0)
(MF[2:0]&DS[1:0] is ID of this IC,
these pins cannot be left open)
C=1uF
365
364
COM52
COM63
351~352
V0
350
V1
349
V2
348
V3
347
V4
345~346
VR
344
VDD
342~343
OSC1
341
VSS
340
INTRS
31
COM0
339
VDD
32
COMS1
338
VEXT
33
SEG0
337
VSS
VDD
T8~T0
320~325
VOUT_IN
314~319
VOUT_OUT
313
VDD
309
MF1
308
MF2
12
V0
307
TB
11
V1
306
TA
10
V2
300~305
VSS
9
V3
284~299
VSS2
8
V4
268~283
VDD2
262~267
VDD
7
VOUT
260~261
D7
6
SID
258~259
D6
5
SCLK
256~257
D5
254~255
D4
RST
252~253
D3
160
SEG127
250~251
D2
161~164
RESERVE
248~249
165
COM64
246~247
D0
244~245
E_RD
242~243
RW_WR
D1
240~241
A0
238~239
RST
4
236~237
CSB
3
235
VSS
2
VSS
234
PS2
1
VDD
233
PS1
232
PS0
231
VDD
230
T9
COM127
................
COMS2
228
................
229
CSB
217
197
................
218
COM117
CO M116
COM95
C OM96
196
C
MF0
C
DS0
310
C
DS1
311
C
ST7541
........................................ ...............
312
........................................................
........................................ ...............
REF
335
326~334
C
..........................................
..........................................
353
336
........................................................
............
................
............
COM30
COM51
1
COM31
385
................
................
Ver 1.9
78/78
2007/9/3