ST
Sitronix
ST7546T
66 x 102 Dot Matrix LCD Controller/Driver
1. INTRODUCTION
The ST7546T is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 102 segment
and 65 common with 1 ICON driver circuits. This chip is connected directly to a microprocessor, accepts 8-bit parallel
2
interface、3-line or 4-line serial peripheral interface (SPI)、I C interface, display data can stores in an on-chip display
data RAM of 66 x 102 bits. It performs display data RAM read/write operation with no external operating clock to
minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible
to make a display system with the fewest components.
2. FEATURES
Single-chip LCD controller & driver
-
Driver Output Circuits
Oscillator requires no external components
(external clock also possible)
102 segment / 65 common + 1 ICON
-
Voltage converter (x4, x5)
On-chip Display Data ram
-
Voltage regulator(temperature gradient
-
-0.11%/°C)
Capacity: 66X102=6,732 bits
Microprocessor Interface
-
8-bit parallel bi-directional interface with
-
Voltage follower
-
On-chip electronic contrast control function (255
6800-series or 8080-series
-
-
steps)
4-line SPI (serial peripheral interface) available
External RESB (reset) pin
(only write operation)
Logic supply voltage range VDD1,2 -VSS
3-line SPI (serial peripheral interface) available
2
I C (Inter-Integrated Circuit) Interface
On-chip Low Power Analog Circuit
-
VDD1 -VSS : 1.7 to 3.3V
-
VDD2 -VSS : 2.4 to 3.3V
Display supply voltage range VLCD -VSS
Generation of LCD supply voltage (externally
-
Vout voltage supply is possible)
-
-
4.5 to 13.5V
Temperature range: -40 to +85 degree
Generation of intermediate LCD bias voltages
ST7546T-G2
6800 , 8080 ,
4-Line , 3-Line interface
(without I2C interface)
ST7546Ti-G2
I2C interface
Ver 1.2
1/48
2006/01/26
ST7546T
3. ST7546T-G2 Pad Arrangement (COG)
Chip Size: 8,200 um × 1020 um
Bump Pitch:
PAD NO 1 ~ 11 , 12 ~ 147 , 207 ~ 230 : 55 um ;
PAD NO 11 ~ 12 : 56 um ;
PAD NO 148 ~ 216 : max : 175 um , min : 72 um
Bump Size:
PAD NO 188 ~ 193 : 45 (x)um × 60 (y) um
;
PAD NO 148 ~ 187 , 194 ~ 206 : 55 (x) um × 60 (y) um
;
PAD NO 124 ~ 137 , 217 ~ 230: 96 (x) um × 37 (y) um
;
PAD NO 1 ~ 123 , 138 ~ 147 , 207 ~ 216 :
37 (x) um × 96 (y) um
;
Bump Height: 17 um
Chip Thickness: 480 um
Ver 1.2
2/48
2006/01/26
ST7546T
Pad Center Coordinates(TMY=0)
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
1
COM[41]
3677
371
31
SEG[19]
2026
371
2
COM[40]
3622
371
32
SEG[20]
1971
371
3
COM[39]
3567
371
33
SEG[21]
1916
371
4
COM[38]
3512
371
34
SEG[22]
1861
371
5
COM[37]
3457
371
35
SEG[23]
1806
371
6
COM[36]
3402
371
36
SEG[24]
1751
371
7
COM[35]
3347
371
37
SEG[25]
1696
371
8
COM[34]
3292
371
38
SEG[26]
1641
371
9
COM[33]
3237
371
39
SEG[27]
1586
371
10
COM[32]
3182
371
40
SEG[28]
1531
371
11
Reserved
3127
371
41
SEG[29]
1476
371
12
SEG[0]
3071
371
42
SEG[30]
1421
371
13
SEG[1]
3016
371
43
SEG[31]
1366
371
14
SEG[2]
2961
371
44
SEG[32]
1311
371
15
SEG[3]
2906
371
45
SEG[33]
1256
371
16
SEG[4]
2851
371
46
SEG[34]
1201
371
17
SEG[5]
2796
371
47
SEG[35]
1146
371
18
SEG[6]
2741
371
48
SEG[36]
1091
371
19
SEG[7]
2686
371
49
SEG[37]
1036
371
20
SEG[8]
2631
371
50
SEG[38]
981
371
21
SEG[9]
2576
371
51
SEG[39]
926
371
22
SEG[10]
2521
371
52
SEG[40]
871
371
23
SEG[11]
2466
371
53
SEG[41]
816
371
24
SEG[12]
2411
371
54
SEG[42]
761
371
25
SEG[13]
2356
371
55
SEG[43]
706
371
26
SEG[14]
2301
371
56
SEG[44]
651
371
27
SEG[15]
2246
371
57
SEG[45]
596
371
28
SEG[16]
2191
371
58
SEG[46]
541
371
29
SEG[17]
2136
371
59
SEG[47]
486
371
30
SEG[18]
2081
371
60
SEG[48]
431
371
Ver 1.2
3/48
2006/01/26
ST7546T
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
61
SEG[49]
376
371
91
SEG[79]
-1274
371
62
SEG[50]
321
371
92
SEG[80]
-1329
371
63
SEG[51]
266
371
93
SEG[81]
-1384
371
64
SEG[52]
211
371
94
SEG[82]
-1439
371
65
SEG[53]
156
371
95
SEG[83]
-1494
371
66
SEG[54]
101
371
96
SEG[84]
-1549
371
67
SEG[55]
46
371
97
SEG[85]
-1604
371
68
SEG[56]
-9
371
98
SEG[86]
-1659
371
69
SEG[57]
-64
371
99
SEG[87]
-1714
371
70
SEG[58]
-119
371
100
SEG[88]
-1769
371
71
SEG[59]
-174
371
101
SEG[89]
-1824
371
72
SEG[60]
-229
371
102
SEG[90]
-1879
371
73
SEG[61]
-284
371
103
SEG[91]
-1934
371
74
SEG[62]
-339
371
104
SEG[92]
-1989
371
75
SEG[63]
-394
371
105
SEG[93]
-2044
371
76
SEG[64]
-449
371
106
SEG[94]
-2099
371
77
SEG[65]
-504
371
107
SEG[95]
-2154
371
78
SEG[66]
-559
371
108
SEG[96]
-2209
371
79
SEG[67]
-614
371
109
SEG[97]
-2264
371
80
SEG[68]
-669
371
110
SEG[98]
-2319
371
81
SEG[69]
-724
371
111
SEG[99]
-2374
371
82
SEG[70]
-779
371
112
SEG[100]
-2429
371
83
SEG[71]
-834
371
113
SEG[101]
-2484
371
84
SEG[72]
-889
371
114
COMS
-2540
371
85
SEG[73]
-944
371
115
COM[0]
-2595
371
86
SEG[74]
-999
371
116
COM[1]
-2650
371
87
SEG[75]
-1054
371
117
COM[2]
-2705
371
88
SEG[76]
-1109
371
118
COM[3]
-2760
371
89
SEG[77]
-1164
371
119
COM[4]
-2815
371
90
SEG[78]
-1219
371
120
COM[5]
-2870
371
Ver 1.2
4/48
2006/01/26
ST7546T
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
121
COM[6]
-2925
371
151
VDD1
-1929
-389
122
COM[7]
-2980
371
152
VDD1
-1856
-389
123
COM[8]
-3035
371
153
VDD1
-1783
-389
124
COM[9]
-3981
352
154
PS0
-1710
-389
125
COM[10]
-3981
297
155
PS1
-1591
-389
126
COM[11]
-3981
242
156
PS2
-1518
-389
127
COM[12]
-3981
187
157
BR
-1399
-389
128
COM[13]
-3981
132
158
VSS
-1326
-389
129
COM[14]
-3981
77
159
T6
-1253
-389
130
COM[15]
-3981
22
160
T7
-1134
-389
131
COM[16]
-3981
-33
161
CP
-1061
-389
132
COM[17]
-3981
-88
162
T8
-942
-389
133
COM[18]
-3981
-143
163
T9
-869
-389
134
COM[19]
-3981
-198
164
VDD2
-766
-389
135
COM[20]
-3981
-253
165
VDD2
-693
-389
136
COM[21]
-3981
-308
166
VDD2
-620
-389
137
COM[22]
-3981
-363
167
VDD2
-547
-389
138
COM[23]
-3678
-371
168
RESB
-410
-389
139
COM[24]
-3623
-371
169
CSB
-291
-389
140
COM[25]
-3568
-371
170
/WR
-218
-389
141
COM[26]
-3513
-371
171
/RD
-99
-389
142
COM[27]
-3458
-371
172
A0
-26
-389
143
COM[28]
-3403
-371
173
VDD1
77
-389
144
COM[29]
-3348
-371
174
D7
150
-389
145
COM[30]
-3293
-371
175
D6
269
-389
146
COM[31]
-3238
-371
176
D5
342
-389
147
Reserved
-3183
-371
177
D4
461
-389
148
TMX
-2194
-389
178
D3
534
-389
149
TMY
-2075
-389
179
D2
653
-389
150
VDD1
-2002
-389
180
D1
726
-389
Ver 1.2
5/48
2006/01/26
ST7546T
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
181
D0
845
-389
211
COM[61]
3403
-371
182
OSC
918
-389
212
COM[60]
3458
-371
183
VSS
1021
-389
213
COM[59]
3513
-371
184
VSS
1094
-389
214
COM[58]
3568
-371
185
VSS
1167
-389
215
COM[57]
3623
-371
186
VSS
1240
-389
216
COM[56]
3678
-371
187
VRS
1313
-389
217
COM[55]
3981
-363
188
T0
1385
-389
218
COM[54]
3981
-308
189
T1
1534
-389
219
COM[53]
3981
-253
190
T2
1609
-389
220
COM[52]
3981
-198
191
T3
1784
-389
221
COM[51]
3981
-143
192
T4
1859
-389
222
COM[50]
3981
-88
193
T5
2034
-389
223
COM[49]
3981
-33
194
VSS
2108
-389
224
COM[48]
3981
22
195
VSS
2181
-389
225
COM[47]
3981
77
196
VSS
2254
-389
226
COM[46]
3981
132
197
VSS
2327
-389
227
COM[45]
3981
187
198
VLCDOUT
2415
-389
228
COM[44]
3981
242
199
VLCDOUT
2488
-389
229
COM[43]
3981
297
200
VLCDIN
2561
-389
230
COM[42]
3981
352
201
VLCDIN
2634
-389
202
V0
2793
-389
203
V1
2883
-389
204
V2
2956
-389
205
V3
3029
-389
206
V4
3102
-389
207
COMS
3183
-371
208
COM[64]
3238
-371
209
COM[63]
3293
-371
210
COM[62]
3348
-371
Ver 1.2
6/48
2006/01/26
ST7546T
Pad Center Coordinates(TMY=1)
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
1
COM[23]
3677
371
31
SEG[19]
2026
371
2
COM[24]
3622
371
32
SEG[20]
1971
371
3
COM[25]
3567
371
33
SEG[21]
1916
371
4
COM[26]
3512
371
34
SEG[22]
1861
371
5
COM[27]
3457
371
35
SEG[23]
1806
371
6
COM[28]
3402
371
36
SEG[24]
1751
371
7
COM[29]
3347
371
37
SEG[25]
1696
371
8
COM[30]
3292
371
38
SEG[26]
1641
371
9
COM[31]
3237
371
39
SEG[27]
1586
371
10
Reserved
3182
371
40
SEG[28]
1531
371
11
Reserved
3127
371
41
SEG[29]
1476
371
12
SEG[0]
3071
371
42
SEG[30]
1421
371
13
SEG[1]
3016
371
43
SEG[31]
1366
371
14
SEG[2]
2961
371
44
SEG[32]
1311
371
15
SEG[3]
2906
371
45
SEG[33]
1256
371
16
SEG[4]
2851
371
46
SEG[34]
1201
371
17
SEG[5]
2796
371
47
SEG[35]
1146
371
18
SEG[6]
2741
371
48
SEG[36]
1091
371
19
SEG[7]
2686
371
49
SEG[37]
1036
371
20
SEG[8]
2631
371
50
SEG[38]
981
371
21
SEG[9]
2576
371
51
SEG[39]
926
371
22
SEG[10]
2521
371
52
SEG[40]
871
371
23
SEG[11]
2466
371
53
SEG[41]
816
371
24
SEG[12]
2411
371
54
SEG[42]
761
371
25
SEG[13]
2356
371
55
SEG[43]
706
371
26
SEG[14]
2301
371
56
SEG[44]
651
371
27
SEG[15]
2246
371
57
SEG[45]
596
371
28
SEG[16]
2191
371
58
SEG[46]
541
371
29
SEG[17]
2136
371
59
SEG[47]
486
371
30
SEG[18]
2081
371
60
SEG[48]
431
371
Ver 1.2
7/48
2006/01/26
ST7546T
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
61
SEG[49]
376
371
91
SEG[79]
-1274
371
62
SEG[50]
321
371
92
SEG[80]
-1329
371
63
SEG[51]
266
371
93
SEG[81]
-1384
371
64
SEG[52]
211
371
94
SEG[82]
-1439
371
65
SEG[53]
156
371
95
SEG[83]
-1494
371
66
SEG[54]
101
371
96
SEG[84]
-1549
371
67
SEG[55]
46
371
97
SEG[85]
-1604
371
68
SEG[56]
-9
371
98
SEG[86]
-1659
371
69
SEG[57]
-64
371
99
SEG[87]
-1714
371
70
SEG[58]
-119
371
100
SEG[88]
-1769
371
71
SEG[59]
-174
371
101
SEG[89]
-1824
371
72
SEG[60]
-229
371
102
SEG[90]
-1879
371
73
SEG[61]
-284
371
103
SEG[91]
-1934
371
74
SEG[62]
-339
371
104
SEG[92]
-1989
371
75
SEG[63]
-394
371
105
SEG[93]
-2044
371
76
SEG[64]
-449
371
106
SEG[94]
-2099
371
77
SEG[65]
-504
371
107
SEG[95]
-2154
371
78
SEG[66]
-559
371
108
SEG[96]
-2209
371
79
SEG[67]
-614
371
109
SEG[97]
-2264
371
80
SEG[68]
-669
371
110
SEG[98]
-2319
371
81
SEG[69]
-724
371
111
SEG[99]
-2374
371
82
SEG[70]
-779
371
112
SEG[100]
-2429
371
83
SEG[71]
-834
371
113
SEG[101]
-2484
371
84
SEG[72]
-889
371
114
COMS
-2540
371
85
SEG[73]
-944
371
115
COM[64]
-2595
371
86
SEG[74]
-999
371
116
COM[63]
-2650
371
87
SEG[75]
-1054
371
117
COM[62]
-2705
371
88
SEG[76]
-1109
371
118
COM[61]
-2760
371
89
SEG[77]
-1164
371
119
COM[60]
-2815
371
90
SEG[78]
-1219
371
120
COM[59]
-2870
371
Ver 1.2
8/48
2006/01/26
ST7546T
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
121
COM[58]
-2925
371
151
VDD1
-1929
-389
122
COM[57]
-2980
371
152
VDD1
-1856
-389
123
COM[56]
-3035
371
153
VDD1
-1783
-389
124
COM[55]
-3981
352
154
PS0
-1710
-389
125
COM[54]
-3981
297
155
PS1
-1591
-389
126
COM[53]
-3981
242
156
PS2
-1518
-389
127
COM[52]
-3981
187
157
BR
-1399
-389
128
COM[51]
-3981
132
158
VSS
-1326
-389
129
COM[50]
-3981
77
159
T6
-1253
-389
130
COM[49]
-3981
22
160
T7
-1134
-389
131
COM[48]
-3981
-33
161
CP
-1061
-389
132
COM[47]
-3981
-88
162
T8
-942
-389
133
COM[46]
-3981
-143
163
T9
-869
-389
134
COM[45]
-3981
-198
164
VDD2
-766
-389
135
COM[44]
-3981
-253
165
VDD2
-693
-389
136
COM[43]
-3981
-308
166
VDD2
-620
-389
137
COM[42]
-3981
-363
167
VDD2
-547
-389
138
COM[41]
-3678
-371
168
RESB
-410
-389
139
COM[40]
-3623
-371
169
CSB
-291
-389
140
COM[39]
-3568
-371
170
/WR
-218
-389
141
COM[38]
-3513
-371
171
/RD
-99
-389
142
COM[37]
-3458
-371
172
A0
-26
-389
143
COM[36]
-3403
-371
173
VDD1
77
-389
144
COM[35]
-3348
-371
174
D7
150
-389
145
COM[34]
-3293
-371
175
D6
269
-389
146
COM[33]
-3238
-371
176
D5
342
-389
147
COM[32]
-3183
-371
177
D4
461
-389
148
TMX
-2194
-389
178
D3
534
-389
149
TMY
-2075
-389
179
D2
653
-389
150
VDD1
-2002
-389
180
D1
726
-389
Ver 1.2
9/48
2006/01/26
ST7546T
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
181
D0
845
-389
211
COM[3]
3403
-371
182
OSC
918
-389
212
COM[4]
3458
-371
183
VSS
1021
-389
213
COM[5]
3513
-371
184
VSS
1094
-389
214
COM[6]
3568
-371
185
VSS
1167
-389
215
COM[7]
3623
-371
186
VSS
1240
-389
216
COM[8]
3678
-371
187
VRS
1313
-389
217
COM[9]
3981
-363
188
T0
1385
-389
218
COM[10]
3981
-308
189
T1
1534
-389
219
COM[11]
3981
-253
190
T2
1609
-389
220
COM[12]
3981
-198
191
T3
1784
-389
221
COM[13]
3981
-143
192
T4
1859
-389
222
COM[14]
3981
-88
193
T5
2034
-389
223
COM[15]
3981
-33
194
VSS
2108
-389
224
COM[16]
3981
22
195
VSS
2181
-389
225
COM[17]
3981
77
196
VSS
2254
-389
226
COM[18]
3981
132
197
VSS
2327
-389
227
COM[19]
3981
187
198
VLCDOUT
2415
-389
228
COM[20]
3981
242
199
VLCDOUT
2488
-389
229
COM[21]
3981
297
200
VLCDIN
2561
-389
230
COM[22]
3981
352
201
VLCDIN
2634
-389
202
V0
2793
-389
203
V1
2883
-389
204
V2
2956
-389
205
V3
3029
-389
206
V4
3102
-389
207
COMS
3183
-371
208
COM[0]
3238
-371
209
COM[1]
3293
-371
210
COM[2]
3348
-371
Ver 1.2
10/48
2006/01/26
ST7546T
4. BLOCK DIAGRAM
SEG0 TO SEG101
COM0 TO COM64+ICOM
SEGMENT DRIVERS
COMMON DRIVERS
DATA LATCHES
COMMON
OUTPUT
CONTROLLER
CIRCUIT
BIAS
VOLTAGE
GENERATOR
VLCDIN
VLCDOUT
RESET
VLCD
GENERATOR
DISPLAY DATA RAM
(DDRAM)
[66X102]
ADDRESS COUNTER
VDD1
VDD2
DATA
REGISTER
INSTRUCTION
REGISTER
BUS
HOLDER
INSTRUCTION
DECODER
OSCILLATOR
/RESB
OSC
TIMING
GENERATOR
DISPLAY
ADDRESS
COUNTER
Vss
PS0
PS1
PS2
MPU INTERFACE(PARALLEL & SERIAL)
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
WR(R/W)
/RD(E)
A0
/CSB
/RESB
Fig.1 block diagram
Ver 1.2
11/48
2006/01/26
ST7546T
5. PINNING DESCRIPTIONS
Pin Name
I/O
Description
No. of Pins
Lcd driver outputs
LCD segment driver outputs
This display data and the M signal control the output voltage of segment
driver.
Segment driver output voltage
Display data M (Internal) Normal display Reverse display
SEG0 to SEG101
O
H
H
H
L
L
H
L
L
Power down mode
V0
VSS
V2
V3
VSS
102
V2
V3
V0
VSS
VSS
COM0 to COM64
O
LCD common driver outputs
This internal scanning data and M signal control the output voltage of
common driver.
Common driver output voltage
Display data M(Internal)
Normal display Reverse display
H
H
VSS
H
L
V0
L
H
V1
L
L
V4
Power down mode
VSS
COMS
O
Common output for the icons.
The output signals of two pins are same. When not used, this pin should
be left open.
2
Microprocessor interface select input pin
PS2
State
PS0 PS1
"L" "L"
" L " 4 Pin-SPI MPU interface
"L" "L"
" H " 3 Pin-SPI MPU interface
"L" "H"
" L " 8080-series parallel MPU interface
"L" "H"
" H " 6800-series parallel MPU interface
2
"H"
"H"
" H " I C interface
3
65
MICROPROCESSOR INTERFACE
PS[2:0]
I
CSB
I
RESB
I
A0
I
Ver 1.2
Chip select input pins
Data/instruction I/O is enabled only when CSB is " L ". When chip select
is non-active, DB0 to DB7 is high impedance.
This pin is only used in 8-bit parallel interface.
When using serial interface , this pin must be fixed to “H”
Reset input pin
When RESB is " L ", initialization is executed.
It determines whether the data bits are data or a command.
A0=" H “: Indicates that D0 to D7 are display data.
A0=" L “: Indicates that D0 to D7 are control data.
This pin is only used in 8-bit parallel interface.
When using serial interface , this pin must be fixed to “H”
12/48
1
1
1
2006/01/26
ST7546T
Read/Write execution control pin (PS[0:1]=[L:H])
/WR(R/W)
PS2
MPU type
/WR(R/W)
H
6800-series
R/W
I
L
8080-series
/WR
Description
Read/Write control input pin
R/W=" H “: read
R/W=" L”: write
Write enable clock input pin
The data on D0 to D7 are latched
at the rising edge of the /WR
signal
1
When in the serial interface must fix to ” H”
Read/Write execution control pin (PS[0:1]=[L:H])
PS2
/RD (E)
I
MPU Type
/RD (E)
H
6800-series
E
L
8080-series
/RD
Description
Read/Write control input pin
R/W=" H “: When E is " H ", D0 to D7
are in an output status.
R/W=" L “: The data on D0 to D7 are
latched at the falling edge of the E
signal.
Read enable clock input pin
When /RD is " L ", D0 to D7 are in an
output status.
1
When in the serial interface must fix to ” H”
D7(SCLK)
D6(SDA)
D5(A0)
D4(CSB)
D3 to D0
I/O
D7(SCLK)
D6 (SDA_IN)
D5(X)
D4(X)
D3 to D2 (SDA_OUT)
D1 (SA1)
D0 (SA0)
Ver 1.2
When using 8-bit parallel interface : 6800 . 8080
8-bit bi-directional data bus that is connected to the standard 8-bit
microprocessor data bus.
When chip select is not active, D0 to D7 is high impedance.
When using serial interface: 4-LINE.3-LINE
D7: serial input clock (SCLK) ; D6: serial input data (SDA)
D5: command/data selection (A0) ; D4: chip select pin(CSB)
D3,D2.D1.D0: must fix to ” H”
When using 3-line A0 must fix to “H”
2
When using I C interface
D7: serial clock input (SCLK)
D6: serial input data (SDA_IN)
2
D3, D2: (SDA_OUT) serial data acknowledge for the I C interface. By
connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully
2
I C interface compatible. Having the acknowledge output separated
from the serial data line is advantageous in chip on glass (COG)
applications. In COG application where the track resistance from the
SDA_OUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the ITO track
resistance. It is possible the during the acknowledge cycle the ST7546T
will not be able to create a valid logic 0 level. By splitting the SDA_IN
input from the SDA_OUT output the device could be used in a mode
that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track
resistance from the SDA_OUT pad to the system SDA line to guarantee
a valid low level.
D6, D3,D2 must be connected together (SDA)
D4, D5: must fix to ” H”
D1, D0: Is slave address (SA0,SA1), must fix to “H” or “L”
Chip select input pins “CSB” not used must fix to “H”
13/48
8
2006/01/26
ST7546T
LCD DRIVER SUPPLY
OSC
I
When the on-chip oscillator is used, this input must be connected
to VDD. An external clock signal, if used, is connected to this input. If
the oscillator and external clock are both inhibited by connecting the
OSC pin to VSS the display is not clocked and may be left in a DC state.
To avoid this, the chip should always be put into Power Down Mode
before stopping the clock.
1
Power Supply Pins
VSS
VDD1
VDD2
VLCDIN
VLCDOUT
V0, V1, V2, V3, V4
VRS
Power
Ground.
9
Supply
Power
Supply
Power
Supply
Power
Supply
Power
Supply
Power
Digital Supply voltage.
The 2 supply rails VDD1 and VDD2 could be connected together.
If Digital Option pin is high, must be this level
Analog Supply voltage.
The 2 supply rails VDD1 and VDD2 could be connected together.
If the internal voltage generator is used, the V LCDIN & VLCDOUT must be
connected together. An external supply voltage can be supplied using
the VLCDIN pad. This pad is for external multiple voltage input. In this
case, VLCDOUT has to be left open,
If the internal voltage generator is used, the V LCDIN & VLCDOUT must be
connected together and series one capacitor to VSS
If an external supply is used this pin must be left open.
Supply
This is a multi-level power supply for the liquid crystal.
VLCDIN ≥V0 ≥V1≥V2≥V3≥V4≥VSS
Power
Monitor Voltage Regulator level, must be left open.
Supply
5
4
2
2
5
1
Configuration Pins
TMX
I
Mirror X: SEG bi-direction selection
TMX connect to VSS : normal direction (SEG0àSEG101)
1
TMX connect to VDD : reverse direction (SEG101àSEG0)
TMY
I
Mirror Y: COM bi-direction selection
TMY connect to VSS (TMY=0): normal direction
TMY connect to VDD (TMY=1): reverse direction
1
See Pad Center Coordinates at page 3~10.
CP
I
BR
I
Set Booster stages. (VSS=4X;VDD=5X)
Set LCD bias ratio. (VSS=1/7;VDD=1/9)
After reset , the bias ratio will be the setting value.
1
1
Test Pin
T0~T9
T
Reserved
-
Ver 1.2
T0~T5 must floating
T7.T8 must connect to VDD
T6.T9 must connect to VSS
All Reserved pins must floating
14/48
10
2
2006/01/26
ST7546T
ST7546T I/O PIN ITO Resister Limitation
PIN Name
ITO Resister
PS[2:0],OSC,CP,BR,T6~T9,TMX,TMY
No Limitation
T0~T5,VRS, V1 , V2 , V3 , V4
Floating
Vdd1, Vdd2, Vss, Vlcdin , Vlcdout
<100Ω
V0
<500Ω
A0,/WR,/RD,CSB, D0 …D7
<1KΩ
RESB
<10KΩ
6. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There is CSB pin for chip selection. The ST7546T can interface with an MPU when CSB is "L". When CSB is “H”, these
pins are set to any other combination, A0, /RD(E), and /WR(R/W) inputs are disabled and D0 to D7 are to be high
impedance. And, in case of serial interface, the internal shift register and the counter are reset.
Parallel / Serial Interface
ST7546T has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial
interface is determined by PS [0:2] pin as shown in table 1.
Table 1. Parallel/Serial Interface Mode
PS0
"L"
"L"
"L"
"L"
"H"
PS1
"L"
"L"
"H"
"H"
"H"
PS2
"L"
"H"
"L"
"H"
"H"
State
4 Pin-SPI MPU interface
3 Pin-SPI MPU interface
8080-series parallel MPU interface
6800-series parallel MPU interface
2
I C interface
Parallel Interface (PS[0:1] = "L;H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS2 as shown in table 2.
The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in t able 3.
PS0
L
L
Common
A0
H
H
L
L
PS1
H
H
Table 2. Microprocessor Selection for Parallel Interface
PS2 CSB
A0
/RD (E) /WR (R/W) DB0 to DB7
MPU bus
H
CSB
A0
E
R/W
DB0 to DB7 6800-series
L
CSB
A0
/RD
/WR
DB0 to DB7 8080-series
6800-series
E
R/W
(/RD)
(/WR)
H
H
H
L
H
H
H
L
Table 3. Parallel Data Transfer
8080-series
Description
/RD
/WR
(E)
(R/W)
L
H
Display data read out
H
L
Display data write
L
H
Register status read
H
L
Writes to internal register (instruction)
NOTE: When /RD (E) pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case,
interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, /WR(R/W)
as in case of 6800-series mode.
Ver 1.2
15/48
2006/01/26
ST7546T
Serial Interface
Serial Mode
4-line SPI interface
3-line SPI interface
2
I C interface
PS0
L
L
PS1
L
L
PS2
L
H
H
H
H
PS0=” L “, PS1=” L “, PS2=” L “: 4-line SPI interface
When the ST7546T is active (CSB=”L”), serial data (D1) and serial clock (D0) inputs are enabled. And not active, the
internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via
software or the Register Select (A0) Pin, based on the setting of PS[2:0]. When the A0 pin is used , data is display data
when A0 is high, and command data when A0 is low. When A0 is not used , the LCD Driver will receive command from
MCU by default. If messages on the data pin are data rather than command, MCU should send Data direction command to
control the data direction and then one more command to define the number of data bytes will be write. After these two
continuous commands are sending, the following messages will be data rather than command. Serial data can be read on
the rising edge of serial clock going into D0 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM
column address pointer will be increased by one automatically. The next bytes after the display data string are handled as
command data.
/CSB
SDA
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB2
DB1
DB0
A0
SCLK
A0
Fig. 2
4-line SPI Timing
PS0=” L “, PS1=” L “, PS2=” H “: 3-line SPI interface
/CSB
SDA
A0
DB7
DB6
DB5
DB4
DB3
SCLK
Fig. 3
Ver 1.2
3-line SPI Timing
16/48
2006/01/26
ST7546T
2
PS0=” H “, PS1=” H “, PS2=” H “: I C Interface
2
2
The I C interface receives and executes the commands sent via the I C Interface. It also receives RAM data and sends it to
the RAM.
2
The I C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial
Data line (SDA) and a Serial Clock line (SCLK). Both lines must be connected to a positive supply via a pull-up resistor.
Data transfer may be initiated only when the bus is not busy.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated
in Fig.4.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock
is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined
as the STOP condition (P). The START and STOP conditions are illustrated in Fig.5.
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.6.
· Transmitter: the device, which sends the data to the bus
· Receiver: the device, which receives the data from the bus
· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
· Slave: the device addressed by a master
· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed
to do so and the message is not corrupted
· Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a
2
STOP condition. Acknowledgement on the I C Interface is illustrated in Fig.7.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Fig .4 Bit transfer
SDA
SCL
Ver 1.2
S
P
START con dition
STOP con dition
Fig .5 Definition of START
17/48
and STOP conditions
2006/01/26
ST7546T
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER (1)
0111100
SLAVE
RECEIVER (2)
0111101
SLAVE
RECEIVER (3)
0111110
SLAVE
RECEIVER (4)
0111111
SDA
SCL
Fig .6 System configuration
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
S
9
clock pulse for
acknowledge ment
START
condition
2
Fig .7 Acknowledgement on the I C Interface
2
I C Interface protocol
The ST7546T supports command, data write addressed slaves on the bus.
2
Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Four 7-bit slave
addresses (0111100,0111101, 0111110 and 0111111) are reserved for the ST7546T. The least significant bit of the slave
address is set by connecting the input SA0 and SA1 to either logic 0 (or logic 1 (VDD1).
2
The I C Interface protocol is illustrated in Fig.8.
2
The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave address.
2
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface transfer. After
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and A0, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer
is automatically updated and the data is directed to the intended ST7546T device. If the A0 bit of the last control byte is set
to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
2
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I C
INTERFACE-bus master issues a STOP condition (P).If the R/W bit is set to logic 1 the chip will output data immediately
after the slave address if the A0 bit, which was sent during the last write access, is set to logic 0. If no acknowledge is
generated by the master after a byte, the driver stops transferring data to the master.
Ver 1.2
18/48
2006/01/26
ST7546T
Fig .8
Co
0
1
2
I C Interface protocol
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by s STOP or RE-START condition.
Another control byte will follow the data byte unless a STOP or RE-START condition is received.
Data Transfer
The ST7546T uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU
to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 9. And when reading
data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU
reads this stored data from bus holder for the next data read cycle as shown in figure 10. This means that a dummy read
cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the
data of the specified address cannot be output with the read display data instruction right after the address sets, but can be
output at the second read of data.
MPU signal
A0
/WR
D0 to D7
N
D(N)
D(N+1) D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
N+1
N+2
N+3
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
Fig.9 Write Timing
Ver 1.2
19/48
2006/01/26
ST7546T
MPU signal
A0
/W R
/RD
D0 to D7
N
Dummy
D(N)
D(N+1)
Internal signals
/W R
/RD
BUS HOLDER
COLUMN ADDRESS
N
N
D(N)
D(N+1)
D(N+2)
D(N)
D(N+1)
D(N+2)
Fig.10 Read Timing
DISPLAY DATA RAM (DDRAM)
The ST7546T contains a 66X102 bit static RAM that stores the display data. The display data RAM store the dot data for
the LCD. It has a 66(8 pageX8 bit +1 pageX1 bit +1 pageX1 bit) X 102 . There is a direct correspondence between
X-address and column output number. It is 66-row by 102-column addressable array. Each pixel can be selected when the
page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines (0~63 COM) and 8th page with
single line (D0) (64COM) and 9th page with a single line (D0) (COMS for ICON). Data is read from or written to the 8 lines
of each page directly through D0 to D7. The display data of D0 to D7 from the microprocessor correspond to the LCD
common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller
operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD
flicker.
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by
only the “Set Page” instruction. Page Address 9 is a special RAM area for the icons and display data D0 is only valid.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line
Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of
on-chip RAM as shown in figure 10. It incorporates 7-bit Line Address register changed by only the initial display line
instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line
counter which is increased by CL signal and generates the line address for transferring the 102-bit RAM data to the display
data latch circuit. When icon is selected by setting icon page address, display data of icons are not scrolled because the
MPU cannot access Line Address of icons.
Ver 1.2
20/48
2006/01/26
ST7546T
Column Address Circuit
Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM. The display
data RAM column address is specified by the Column Address Set command. The specified column address is
incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed
continuously.
ADDRESSING
Data is downloaded in bytes into the RAM matrix of ST7546T. The display RAM has a matrix of 66 by 102 bits. The
address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101),Y 0 to 9 (1001) .Addresses outside
these ranges are not allowed.In vertical addressing mode (V=1) the Y address increments after each byte. After the last Y
address (Y = 8), Y wraps around to 0 and X increments to address the next column.In horizontal addressing mode (V=0)
the X address increments after each byte. After the last X address(X = 101) X wraps around to 0 and Y increments to
address the next row.After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0)
D0
D7
LSB
0
1
2
3
4
5
6
7
8
9
MSB
LSB
MSB
1 bit
0
X-address
101
RAM format, addressing
Ver 1.2
21/48
2006/01/26
Y-address
Data structure
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0
917
X-address
0
1
2
3
4
5
6
7
8
9
Y-address
ST7546T
101
0 1 2
102103104
204205206
306307308
408409410
510511512
612613614
714715716
816817818
0
917
X-address
101
0
1
2
3
4
5
6
7
8
9
Y-address
Sequence of writing data bytes into RAM with vertical addressing (V=1)
Sequence of writing data bytes into RAM with horizontal addressing (V=0)
Ver 1.2
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ST7546T
Page Address
Data
D3 D2 D1 D0
60
5F
5E
5D
S5
S6
S7
S8
DO
MX
61
S4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
ICON (COMS)
Column
address
62
S3
0
63
S2
1
64
S1
DO
65
S0
COM Output
Regardless of the display start
line address,
1/66duty => 65th line
LCD
Out
Page 8
Page 9
65
0
1
64
0
0
00
0
0
S101
1
1
Page 7
63
1
01
1
S100
1
62
0
Page 6
02
0
S99
1
61
1
03
0
Page 5
S98
1
60
0
04
1
S97
0
Page 4
5F
0
05
0
S96
1
5E
0
Page 3
06
1
S95
1
5D
0
07
0
Page 2
08
0
S94
1
S93
0
08
0
Page 1
07
1
06
0
05
0
04
0
When the common
output is normal
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
Page 0
03
0
02
0
01
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D0
00
0
Line
Address
Display Data RAM Map (66 COM)
Ver 1.2
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ST7546T
Oscillator
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC
input must be connected to VDD. An external clock signal, if used, is connected to this input.
LCD DRIVER CIRCUIT
66-channel common drivers and 102-channel segment drivers configure this driver circuit. This LCD panel driver voltage
depends on the combination of display data and M signal.
COM0
M
VDD
VSS
COM0
V0
V1
V2
V3
V4
VSS
COM1
V0
V1
V2
V3
V4
VSS
COM2
V0
V1
V2
V3
V4
VSS
SEG0
V0
V1
V2
V3
V4
VSS
SEG1
V0
V1
V2
V3
V4
VSS
COM0
to
SEG0
V0
V1
V2
V3
V4
VSS
-V4
-V3
-V2
-V1
-V0
COM0
to
SEG1
V0
V1
V2
V3
V4
VSS
-V4
-V3
-V2
-V1
-V0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG 0
1
2
3
4
Typical LCD driver waveforms
Ver 1.2
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ST7546T
7. RESET CIRCUIT
Setting RESB to “L” or Reset instruction can initialize internal function.
When RESB becomes “L”, following procedure is occurred.
Page address: 0
Column address: 0
Display control: Display blank
Oscillator: OFF
Power down mode (PD = 1)
Horizontal addressing (V = 0)
Normal instruction set (H = 0)
Display blank (E = D = 0)
Address counter X [6:0] = 0, Y [3:0] = 0
Bias system (BS [2:0] = BR setting)
VLCD is equal to 0; the HV generator is switched off (VOP [6:0] = 0)
After power-on, RAM data are undefined
While RESB is “L” or reset instruction is executed, no instruction except read status can be accepted. Reset status
appears at DB0. After DB0 becomes ”L”, any instruction can be accepted. RESB must be connected to the reset pin of
the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESB is essential before used.
Ver 1.2
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ST7546T
8. INSTRUCTION TABLE
INSTRUCTION
A0
WR
(R/W)
COMMAND BYTE
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
H=0 or 1
NOP
0
0
0
0
0
0
0
0
0
0
No operation
Function set
0
0
0
0
1
0
0
PD
V
H
Power-down; entry mode;
Write data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data to RAM
A0
WR
(R/W)
D0
INSTRUCTION
COMMAND BYTE
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
H=0
Set VLCD range
Display control
Set Y address of
RAM
Set X address of
RAM
H=1
Reserved
Bias system
Reserved
Set VOP
Ver 1.2
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
D
0
E
Sets display configuration
0
0
0
1
0
0
Y3
Y2
Y1
Y0
Sets Y address of RAM
0≦Y≦9
0
0
1
X6
X5
X4
X3
X2
X1
X0
Sets X address of RAM
0≦X≦101
0
0
0
0
0
0
0
0
1
X
Do not use
0
0
0
0
0
1
0
BS2
BS1
BS0
0
0
0
1
X
X
X
X
X
X
0
0
1
VOP6
VOP5
VOP4
VOP3
VOP2
VOP1
26/48
PRS VLCD range L/H select
Sets bias system (BSx)
Do not use(reserved for test)
VOP0 Write VOP to register
2006/01/26
ST7546T
9. INSTRUCTION DESCRIPTION
H= “0” or “1”
Function Set
A0
0
Flag
PD
V
H
WR(R/W)
0
D7
0
D6
0
D5
1
D4
0
D3
0
D2
PD
D1
V
D0
H
Description
All LCD outputs at VSS (display off), bias generator and VLCD generator off, VLCD can be
disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data
can be written.
PD=0:chip is active
PD=1:chip is in power down mode
When V = 0, the horizontal addressing is selected.
When V = 1, the vertical addressing is selected.
When H = 0 the commands ‘display control’, ‘set Y address’ and ‘set X address’ can be
performed, when H = 1 the others can be executed. The commands ‘write data’ and ‘function
set’ can be executed in both cases.
Write data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and
page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data
to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
A0
1
WR(R/W)
D7
D6
D5
D4
D3
Write data
D2
D1
D0
D5
0
D4
1
D3
0
D2
0
D1
0
D0
PRS
D5
0
D4
0
D3
1
D2
D
D1
0
D0
E
0
H= “0”
Set VLCD range
VLCD range L/H select
A0
D7
D6
WR(R/W)
0
0
0
0
PRS=0: VLCD programming range LOW
PRS=1: VLCD programming range HIGH
Display Control
This bits D and E selects the display mode.
A0
0
Flag
D,E
Ver 1.2
WR(R/W)
0
D7
0
D6
0
Description
D E The bits D and E select the display mode.
0 0 Display blank
1 0 Normal display
0 1 All display segments on
1 1 Inverse video mode
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ST7546T
Set Y address of RAM
Y [3:0] defines the Y address vector address of the display RAM.
A0
D7
D6
D5
D4
D3
WR(R/W)
0
0
0
1
0
0
Y3
Y3
0
0
0
0
0
0
0
0
1
1
Y2
0
0
0
0
1
1
1
1
0
0
Y1
0
0
1
1
0
0
1
1
0
0
Y0
0
1
0
1
0
1
0
1
0
1
CONTENT
Page0 (display RAM)
Page1 (display RAM)
Page2 (display RAM)
Page3 (display RAM)
Page4 (display RAM)
Page5 (display RAM)
Page6 (display RAM)
Page7 (display RAM)
Page8 (display RAM)
Page9 (display RAM)
D2
Y2
D1
Y1
D0
Y0
ALLOWED X-RANGE
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
Set X address of RAM
The X address points to the columns. The range of X is 0…101.
A0
D7
D6
D5
D4
WR(R/W)
0
0
1
X6
X5
X4
X6
0
0
0
0
:
1
1
1
1
X5
0
0
0
0
:
1
1
1
1
X4
0
0
0
0
:
0
0
0
0
X3
0
0
0
0
:
0
0
0
0
X2
0
0
0
0
:
0
0
1
1
X1
0
0
1
1
:
1
1
0
0
D3
X3
X0
0
1
0
1
:
0
1
0
1
D2
X2
D1
X1
D0
X0
Column address
0
1
2
3
:
98
99
100
101
H= “1”
System Bias
Select LCD bias ratio of the voltage required for driving the LCD.
A0
D7
D6
D5
D4
D3
WR(R/W)
0
0
0
0
0
1
0
BS2
0
0
0
0
1
1
1
1
Ver 1.2
BS1
0
0
1
1
0
0
1
1
BS0
0
1
0
1
0
1
0
1
Bias
11
10
9
8
7
6
5
4
D2
BS2
D1
BS1
D0
BS0
Recommend Duty
1:100
1:81
1:65/1:68
1:49
1/40:1/36
1/24
1:18/1:16
1:10/1:9/1:8
28/48
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ST7546T
Set VOP value
A0
D7
D6
D5
WR(R/W)
0
0
1
VOP6
VOP5
The operation voltage VLCD can be set by software.
D4
VOP4
D3
VOP3
D2
VOP2
D1
VOP1
D0
VOP0
VLCD=( a + VOP×b )
(1)
The maximum voltage that can be generated is depending on the VDD1 voltage and the display load current. Two
overlapping VLCD ranges are selectable via the command “Booster control”. For the LOW (PRS=0) range a=a1 and for
the HIGH (PRS=1) range a=a2 with steps equal to “b” in both ranges. Note that the charge pump is turned off if VOP
[6;0] and the bit PRS are all set to zero
Table 4 Typical values for parameter for the HV-Generator programming
SYMBOL
VALUE
UNIT
a1
2.94(PRS=0)
V
a2
6.75(PRS=1)
V
b
0.03
V
VL2
Charge pump off
b
00
a2
a1+b
01
02
03
04
05
06
.....
7D
7E
7F
00
01
02
03
LOW(PRS=0)
04
05
06
.....
7D
7E
7F
HIGH(PRS=1)
VOP [6:0](programmed) {00 hex… 7F hex}
Fig.23 VOP programming of ST7546T
Ver 1.2
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ST7546T
10. COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON(VDD-VSS) Keeping the /RESB Pin="L"
Waiting for Stabilizing the Power
Release the reset state. (/RESB pin="H")
Waiting reset circuit stablized(>1ms)
Function set PD=0 ,V=0 , H=1
SET Bias system
SET VOP
Function set PD=0 , V=0 , H=0
Set VLCD Range(PRS)
Display control D=1 E=0 (Normal)
Set X , Y address
End of Initialization
Initializing with the Built-in Power Supply Circuits
Ver 1.2
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ST7546T
11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2.
Parameter
Symbol
Conditions
Unit
Power Supply Voltage
VDD1
-0.5 ~ 5
V
Power supply voltage
VDD2
-0.5 ~ 5
V
Power supply voltage (VDD standard)
VLCDIN
4.5~13.5
V
Power supply voltage (VDD standard)
V1, V2, V3, V4
0.3 to Vlcdin
V
Operating temperature
TOPR
–40 to +85
°C
Storage temperature
TSTR
–65 to +150
°C
Notes
1. Stresses above those listed under Limiting Values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3. Insure that the voltage levels of V0, V1, V2, V3, and V4 are always such that
VLCDIN ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ Vss
Ver 1.2
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ST7546T
12. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
13. DC CHARACTERISTICS
VDD1 = 1.7 V to 3.3V; VSS = 0 V; Vout = 3.0 to 13.0V; Tamb = -40℃ to +85℃; unless otherwise specified.
Item
Symbol Condition
Operating Voltage (1)
VDD1
Operating Voltage (2)
VDD2
High-level Input Voltage
VIHC
Low-level Input Voltage
Rating
Units
Applicable
Pin
Min.
Typ.
Max.
1.7
—
3.3
V
Vss
2.4
—
3.3
V
VSS
0.7 x VDD —
VDD
V
VILC
VSS
0.3 x VDD V
High-level Output Voltage
VOHC
0.7 x VDD —
VDD
Low-level Output Voltage
VOLC
VSS
—
0.3 x VDD V
Input leakage current
ILI
–1.0
—
1.0
μA
Output leakage current
ILO
–3.0
—
3.0
μA
—
2.0
3.5
Liquid Crystal Driver ON
Resistance
RON
(Relative to VSS)
Ta =
VLCDIN =
25°C
13.0 V
(Relative VLCDIN = 8.0
To VSS) V
Frame frequency
Item
Internal Power
Input voltage
Supply Step-up output
voltage Circuit
FR
Symbol
Condition
VDD1
—
V
KΩ
—
3.2
5.4
65.7
73
80.3
Rating
SEGn
COMn *6
Hz
Units
Applicable Pin
Min.
Typ.
Max.
(Relative To VSS)
1.7
—
3.3
V
VLCDOUT
(Relative To VSS)
—
—
13.5
V
VLCDOUT
VLCDIN
(Relative To VSS)
—
—
13.5
V
VLCDIN
Voltage regulator
Circuit Operating
Voltage
Ver 1.2
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ST7546T
Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs(bare
die)
Test pattern
Display Pattern
SNOW
Power Down
Symbol
Rating
Condition
Units
Min.
Typ.
Max.
—
300
—
μA
—
0.01
2
μA
Notes
VDD = 3.0 V,
ISS
Booster X4
V0 – VSS = 9.0 V
ISS
Ta = 25°C
Notes to the DC characteristics
1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load.
2. Internal clock
3. Power-down mode. During power down all static currents are switched off.
4. If external VLCDIN, the display load current is not transmitted to I DD.
5. VOUT external voltage applied to VLCDIN pin; VLCDIN disconnected from VLCDOUT (no connect)
Ver 1.2
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ST7546T
14. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
/CSB
tCYC8
tCCLR,tCCLW
WR,RD
tCCHR,tCCHW
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Figure 26.
(VDD = 3.3V , Ta =25°C)
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Ver 1.2
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH8
10
—
tAW8
100
—
tCYC8
400
—
tCCLW
80
—
tCCHW
80
—
tCCLR
140
—
tCCHR
80
tDS8
80
—
tDH8
10
—
tACC8
CL = 100 pF
—
70
tOH8
CL = 100 pF
5
50
34/48
Units
ns
2006/01/26
ST7546T
(VDD = 2.7 V , Ta = 25°C )
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
D0 to D7
READ Output disable time
Symbol
Condition
Rating
Min.
Max.
tAH8
15
—
tAW8
150
—
tCYC8
600
—
tCCLW
220
—
tCCHW
180
—
tCCLR
220
—
tCCHR
180
—
tDS8
120
—
tDH8
15
—
tACC8
CL = 100 pF
—
140
tOH8
CL = 100 pF
10
100
Units
ns
(VDD = 1.8V , Ta = 25°C )
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH8
30
—
tAW8
200
—
tCYC8
1000
—
tCCLW
360
—
tCCHW
280
—
tCCLR
360
—
tCCHR
280
tDS8
200
—
tDH8
30
—
tACC8
CL = 100 pF
—
240
tOH8
CL = 100 pF
10
200
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
Ver 1.2
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ST7546T
System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0
R/W
tAW6
tAH6
CSB
tCYC6
tCCLR,tCCLW
E
tCCHR,tCCHW
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Figure 27.
(VDD = 3.3 V , Ta = 25°C )
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Ver 1.2
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH6
10
—
tAW6
0
—
tCYC6
240
—
tEWLW
80
—
tEWHW
80
—
tEWLR
80
—
tEWHR
140
tDS6
80
—
tDH6
10
—
tACC6
CL = 100 pF
—
70
tOH6
CL = 100 pF
5
50
36/48
Units
ns
2006/01/26
ST7546T
(VDD = 2.7V , Ta =25°C )
Item
Signal
Address hold time
A0
Address setup time
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
RD
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
D0 to D7
READ Output disable time
Symbol
Rating
Condition
Min.
Max.
tAH6
15
—
tAW6
0
—
tCYC6
400
—
tEWLW
220
—
tEWHW
180
—
tEWLR
220
—
tEWHR
180
—
tDS6
120
—
tDH6
15
—
tACC6
CL = 100 pF
—
140
tOH6
CL = 100 pF
10
100
Units
ns
(VDD =1.8V , Ta =25°C )
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH6
30
—
tAW6
0
—
tCYC6
640
—
tEWLW
360
—
tEWHW
280
—
tEWLR
360
—
tEWHR
280
—
tDS6
200
—
tDH6
30
—
tACC6
CL = 100 pF
—
240
tOH6
CL = 100 pF
10
200
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CSB being “L” and E.
Ver 1.2
37/48
2006/01/26
ST7546T
SERIAL INTERFACE(4-Line Interface)
tCCSS
tCSH
/CSB
tSAS
tSAH
A0
tSCYC
tSLW
SCLK
tSHW
tf
tr
tSDS
tSDH
SDA
Fig 28.
(VDD=3.3V,Ta=25℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
A0
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
150
—
tSHW
75
—
tSLW
75
—
tSAS
20
—
tSAH
100
—
tSDS
20
—
tSDH
10
—
tCSS
20
—
tCSH
140
—
Units
ns
(VDD=2.7V,Ta=25℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
Ver 1.2
A0
SI
CSB
Symbol
Condition
Rating
Min.
Max.
tSCYC
300
—
tSHW
150
—
tSLW
150
—
tSAS
30
—
tSAH
150
—
tSDS
30
—
tSDH
20
—
tCSS
30
—
tCSH
200
—
38/48
Units
ns
2006/01/26
ST7546T
(VDD=1.8V,Ta=25℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
A0
SI
CSB
Symbol
Condition
Rating
Min.
Max.
tSCYC
500
—
tSHW
250
—
tSLW
250
—
tSAS
60
—
tSAH
250
—
tSDS
60
—
tSDH
50
—
tCSS
40
—
tCSH
350
—
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.2
39/48
2006/01/26
ST7546T
SERIAL INTERFACE(3-Line Interface)
tCCSS
tCSH
/CS1
(CS2="1")
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Fig 28.
(VDD=3.3V,Ta=25℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
150
—
tSHW
75
—
tSLW
75
—
tSDS
20
—
tSDH
10
—
tCSS
20
—
tCSH
140
—
Units
ns
(VDD=2.7V,Ta=25℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
Data hold time
CS-SCL time
CS-SCL time
Ver 1.2
SI
CSB
Symbol
Condition
Rating
Min.
Max.
tSCYC
300
—
tSHW
150
—
tSLW
150
—
tSDS
30
—
tSDH
20
—
tCSS
30
—
tCSH
200
—
40/48
Units
ns
2006/01/26
ST7546T
(VDD=1.8V,Ta=25℃)
Item
Signal
Serial Clock Period
SCL
SCL “H” pulse width
SCL “L” pulse width
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Rating
Condition
Min.
Max.
tSCYC
500
—
tSHW
250
—
tSLW
250
—
tSDS
60
—
tSDH
50
—
tCSS
40
—
tCSH
350
—
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
2
SERIAL INTERFACE(I C Interface)
SD A
tBU F
t H IG H
tLO W
SCL
t D H ;S T A
t H D ;D A T
t S U ;D A T
(VDD=3.3V,Ta=25℃)
Item
Signal Symbol
Rating
Condition
Min.
Max.
Units
SCL clock frequency
SCL
FSCLK
-
400
kHZ
SCL clock low period
SCL
TLOW
1.3
-
us
SCL clock high period
SCL
THIGH
0.6
-
us
Data set-up time
SI
TSU;Data
100
-
ns
Data hold time
SI
THD;Data
0
0.9
us
SCL,SDA rise time
SCL
TR
20+0.1Cb 300
ns
SCL,SDA fall time
SCL
TF
20+0.1Cb 300
ns
Cb
-
400
pF
Capacitive load represented by each bus line
Setup time for a repeated START condition
SI
TSU;SUA
0.6
-
us
Start condition hold time
SI
THD;STA
0.6
-
us
Setup time for STOP condition
TSU;STO
0.6
-
us
Tolerable spike width on bus
TSW
-
50
ns
BUS free time between a STOP and START condition SCL
TBUF
1.3
Ver 1.2
41/48
us
2006/01/26
ST7546T
15. RESET TIMING
tRW
/RES
tR
Internal
status
During reset
Reset complete
Fig 29.
(VDD = 3.3V , Ta = –40 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
1
us
tRW
1
—
—
us
(VDD = 2.7V , Ta = –40 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
2.0
us
tRW
2.0
—
—
us
(VDD = 1.8V , Ta = –40 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
Ver 1.2
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
3.0
us
tRW
3.0
—
—
us
42/48
2006/01/26
ST7546T
APPICATION NOTE
Ver 1.2
43/48
2006/01/26
ST7546T
Ver 1.2
44/48
2006/01/26
ST7546T
Ver 1.2
45/48
2006/01/26
ST7546T
Ver 1.2
46/48
2006/01/26
ST7546T
Ver 1.2
47/48
2006/01/26
ST7546T
History
Version
History
V0.x
Preliminary
V1.0
Complete release
Notes
Revise I2C pin description
P13,P47
V1.1
Change Thickness to be 480um
Add Frame Rate maximum and minimum value.
V1.2
Change –G2 definition:
Model Name: ST7546T
Part Number: ST7546T-G2 and ST7546Ti-G2
Ver 1.2
48/48
2006/01/26