ST Sitronix ST7787 262K Color Single-Chip TFT Controller/Driver 1. Introduction The ST7787 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 720 source line and 320 gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial Peripheral Interface (SPI), 8-bits/9-bits/16-bits/18-bits parallel interface. Display data can be stored in the on-chip display data RAM of 240x320x18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. 2. Features Single chip TFT-LCD controller/driver with display data RAM Display resolution: 240(H) x RGB x 320(V) Display data RAM (frame memory): 240 x 320 x 18-bits = 1,382,400 bits Operation Frequency: DC~30MHz (30MHz for 6 bits, 10MHz for 18 bits) Output: - 240ch source outputs (240RGB) - 320ch gate outputs - Common electrode output Display mode (color mode) - Full color mode (idle mode off): 262K-colors - Reduce color mode (idle mode on): 8-colors (1-bit for individual R, G, B color depth) Display resolution option - 240 x 320 Display with 240 x 18-bits x 320 display RAM Supported LC type option - MVA LC type (When LCM[1]=0,LCM[0]=0 ) - Transflective LC type (When LCM[1]=0,LCM[0]=1 ) - Transmissive LC type (When LCM[1]=1,LCM[0]=0 ) Supported data format on display host interface - 12-bits/pixel: RGB= (444) using the 1382k bits frame memory and LUT - 16-bits/pixel: RGB= (565) using the 1382k bits frame memory and LUT - 18-bits/pixel: RGB= (666) using the 1382k bits frame memory Supported MCU Interface - 3-line serial interface - 8-bits, 9-bits, 16-bits, 18-bits interface with 8080-series MCU - 8-bits, 9-bits, 16-bits, 18-bits interface with 6800-series MCU - 6-bits, 16-bits, 18-bits RGB interface with graphic controller Display features - Area scrolling - Partial display mode - Software programmable color depth mode Build-in circuit - DC/DC converter - Adjustable VCOM generation - Non-volatile (NV) memory to store initial register setting - Oscillator for display clock generation - Timing controller - 4 preset gamma curve for γ=1.0/1.8/2.2/2.5 (supporting Transflective) and 1 preset gamma curve for γ=2.2 (supporting MVA, Ttransmissive type LC) - Factory default value (contrast, module ID, module version, etc) are stored in NV memory - Line inversion, frame inversion NV Memory - 8-bits for ID1 - 7-bits for ID2 - 8-bits for ID3 - 8-bits for VCOM adjustment Supply voltage range - Analog supply voltage range (VDD to AGND): 2.45V – 3.3V - I/O supply voltage range (VDDI to DGND): 1.65V – 3.3V Sitronix Technology Corp. reserves the right to change 1 the contents in this document without prior notice. ST7787 Output voltage level - Source output voltage range (GVDD to AGND): 3.0V to 5.0V - Power supply range for driver circuit (AVDD to AGND): 5.2V (VDD=2.6V) to 6.0V (VDD=3.0V) - Output range of HIGH level of VCOM (VCOMH to AGND): 2.5V to 5.0V - Output range of LOW level of VCOM (VCOML to AGND): -2.5V to 0.0V - Output range of HIGH level of gate driver (VGH to AGND): +12V to +16.5V - Output range of LOW level of gate driver (VGL to AGND): -14V to –5V Lower power consumption, suitable for battery operated systems - CMOS compatible inputs - Optimized layout for COG assembly - Operate temperature range: -30 ℃ to +70℃ V1.7 2 2008.04.18 ST7787 3. Pad arrangement Dummy Dummy Dummy G317 G1 Dummy S2 Dummy Dummy G319 G3 Dummy S1 S3 S719 Dummy S718 S720 Dummy G2 Dummy G4 G318 Dummy Dummy Dummy G320 Dummy Dummy V1.7 Dummy Dummy EXTC DGNDO IM0 VDDIO IM1 DGNDO IM2 VDDIO P68 DGNDO RCM0 VDDIO RCM1 DGNDO SRGB VDDIO SMX DGNDO SMY VDDIO IDM DGNDO REV VDDIO RL DGNDO TB VDDIO SHUT DGNDO GS LCM1 LCM0 VDDIO TP0 TP1 TP2 TP3 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 DGNDO Dummy TEST_EN D7 D6 D5 D4 D3 D2 D1 D0 TPO0 TPO1 TPO2 TPO3 TPO4 TPO5 TPO6 TPO7 OSC TE CSX RDX WRX SDA Dummy AUTO RESX DGND D/CX DGND PCLK DGND DE HS VS DGND DGND DGND DGND DGND DGND DGND DGND VDDI VDDI VDDI VDDI VREF VREF VREF REGP REGPT VCC VCC VCC VCC VCC VCC Dummy Dummy VCI1 VCI1 VCI1 VCI1 AGND AGND AGND AGND AGND AGND AGND AGND VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDDO AVDDO AVDDS C1SO C1SO VC1S VC1S VC1S VC1S GVDD GVDD GVDD C11P C11P C11P C11P C11P C11P C11N C11N C11N C11N C11N C11N C12P C12P C12P C12P C12P C12P C12N C12N C12N C12N C12N C12N Dummy Dummy AGND AGND AGND AGND AGND AGND AGND AGND Dummy Dummy VCL VCL VCL VCLO VCLO VCLS C21P C21P C21P C21P C21N C21N C21N C21N C22P C22P C22P C22P C22N C22N C22N C22N C23P C23P C23P C23P C23N C23N C23N C23N Dummy Dummy VGL VGL VGL VGL VGLS Dummy Dummy VGH VGH VGHO VGHO VGHS Dummy Dummy VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML VCOML VCOML VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM Dummy Dummy VPP VPP VPP VPP Dummy Dummy View point: bump view Chip size (um): 19384 x 1170 PAD coordinate: pad center Coordinate origin: chip center Chip thickness (um): 300 Bump height (um): 15 Bump hardness (HV): 75± ±25 Pad arrangement (Unit: um): Output: pad No. 1 ~ 1069 = 16 x 97 20 16 97 45 18 Input: pad No. 1070 ~ 1335 = 55 x 110 Alignment mark (unit: um): (-9533,-248.77) 3 (9544,-248.77) 2008.04.18 ST7787 4. Pad Center Coordinates PAD No. PIN Name X Y PAD No. PIN Name X Y 1 DUMMY 9612 486.72 41 G250 8892 486.72 2 DUMMY 9594 344.72 42 G248 8874 344.72 3 DUMMY 9576 486.72 43 G246 8856 486.72 4 DUMMY 9558 344.72 44 G244 8838 344.72 5 DUMMY 9540 486.72 45 G242 8820 486.72 6 G320 9522 344.72 46 G240 8802 344.72 7 G318 9504 486.72 47 G238 8784 486.72 8 G316 9486 344.72 48 G236 8766 344.72 9 G314 9468 486.72 49 G234 8748 486.72 10 G312 9450 344.72 50 G232 8730 344.72 11 G310 9432 486.72 51 G230 8712 486.72 12 G308 9414 344.72 52 G228 8694 344.72 13 G306 9396 486.72 53 G226 8676 486.72 14 G304 9378 344.72 54 G224 8658 344.72 15 G302 9360 486.72 55 G222 8640 486.72 16 G300 9342 344.72 56 G220 8622 344.72 17 G298 9324 486.72 57 G218 8604 486.72 18 G296 9306 344.72 58 G216 8586 344.72 19 G294 9288 486.72 59 G214 8568 486.72 20 G292 9270 344.72 60 G212 8550 344.72 21 G290 9252 486.72 61 G210 8532 486.72 22 G288 9234 344.72 62 G208 8514 344.72 23 G286 9216 486.72 63 G206 8496 486.72 24 G284 9198 344.72 64 G204 8478 344.72 25 G282 9180 486.72 65 G202 8460 486.72 26 G280 9162 344.72 66 G200 8442 344.72 27 G278 9144 486.72 67 G198 8424 486.72 28 G276 9126 344.72 68 G196 8406 344.72 29 G274 9108 486.72 69 G194 8388 486.72 30 G272 9090 344.72 70 G192 8370 344.72 31 G270 9072 486.72 71 G190 8352 486.72 32 G268 9054 344.72 72 G188 8334 344.72 33 G266 9036 486.72 73 G186 8316 486.72 34 G264 9018 344.72 74 G184 8298 344.72 35 G262 9000 486.72 75 G182 8280 486.72 36 G260 8982 344.72 76 G180 8262 344.72 37 G258 8964 486.72 77 G178 8244 486.72 38 G256 8946 344.72 78 G176 8226 344.72 39 40 G254 8928 486.72 79 G174 8208 486.72 G252 8910 344.72 80 G172 8190 344.72 V1.7 4 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 81 G170 8172 486.72 121 G90 7452 486.72 82 G168 8154 344.72 122 G88 7434 344.72 83 G166 8136 486.72 123 G86 7416 486.72 84 G164 8118 344.72 124 G84 7398 344.72 85 G162 8100 486.72 125 G82 7380 486.72 86 G160 8082 344.72 126 G80 7362 344.72 87 G158 8064 486.72 127 G78 7344 486.72 88 G156 8046 344.72 128 G76 7326 344.72 89 G154 8028 486.72 129 G74 7308 486.72 90 G152 8010 344.72 130 G72 7290 344.72 91 G150 7992 486.72 131 G70 7272 486.72 92 G148 7974 344.72 132 G68 7254 344.72 93 G146 7956 486.72 133 G66 7236 486.72 94 G144 7938 344.72 134 G64 7218 344.72 95 G142 7920 486.72 135 G62 7200 486.72 96 G140 7902 344.72 136 G60 7182 344.72 97 G138 7884 486.72 137 G58 7164 486.72 98 G136 7866 344.72 138 G56 7146 344.72 99 G134 7848 486.72 139 G54 7128 486.72 100 G132 7830 344.72 140 G52 7110 344.72 101 G130 7812 486.72 141 G50 7092 486.72 102 G128 7794 344.72 142 G48 7074 344.72 103 G126 7776 486.72 143 G46 7056 486.72 104 G124 7758 344.72 144 G44 7038 344.72 105 G122 7740 486.72 145 G42 7020 486.72 106 G120 7722 344.72 146 G40 7002 344.72 107 G118 7704 486.72 147 G38 6984 486.72 108 G116 7686 344.72 148 G36 6966 344.72 109 G114 7668 486.72 149 G34 6948 486.72 110 G112 7650 344.72 150 G32 6930 344.72 111 G110 7632 486.72 151 G30 6912 486.72 112 G108 7614 344.72 152 G28 6894 344.72 113 G106 7596 486.72 153 G26 6876 486.72 114 G104 7578 344.72 154 G24 6858 344.72 115 G102 7560 486.72 155 G22 6840 486.72 116 G100 7542 344.72 156 G20 6822 344.72 117 G98 7524 486.72 157 G18 6804 486.72 118 G96 7506 344.72 158 G16 6786 344.72 119 G94 7488 486.72 159 G14 6768 486.72 120 G92 7470 344.72 160 G12 6750 344.72 V1.7 5 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 161 G10 6732 486.72 201 S691 6012 486.72 162 G8 6714 344.72 202 S690 5994 344.72 163 G6 6696 486.72 203 S689 5976 486.72 164 G4 6678 344.72 204 S688 5958 344.72 165 G2 6660 486.72 205 S687 5940 486.72 166 DUMMY 6642 344.72 206 S686 5922 344.72 167 DUMMY 6624 486.72 207 S685 5904 486.72 168 DUMMY 6606 344.72 208 S684 5886 344.72 169 DUMMY 6588 486.72 209 S683 5868 486.72 170 DUMMY 6570 344.72 210 S682 5850 344.72 171 DUMMY 6552 486.72 211 S681 5832 486.72 172 S720 6534 344.72 212 S680 5814 344.72 173 S719 6516 486.72 213 S679 5796 486.72 174 S718 6498 344.72 214 S678 5778 344.72 175 S717 6480 486.72 215 S677 5760 486.72 176 S716 6462 344.72 216 S676 5742 344.72 177 S715 6444 486.72 217 S675 5724 486.72 178 S714 6426 344.72 218 S674 5706 344.72 179 S713 6408 486.72 219 S673 5688 486.72 180 S712 6390 344.72 220 S672 5670 344.72 181 S711 6372 486.72 221 S671 5652 486.72 182 S710 6354 344.72 222 S670 5634 344.72 183 S709 6336 486.72 223 S669 5616 486.72 184 S708 6318 344.72 224 S668 5598 344.72 185 S707 6300 486.72 225 S667 5580 486.72 186 S706 6282 344.72 226 S666 5562 344.72 187 S705 6264 486.72 227 S665 5544 486.72 188 S704 6246 344.72 228 S664 5526 344.72 189 S703 6228 486.72 229 S663 5508 486.72 190 S702 6210 344.72 230 S662 5490 344.72 191 S701 6192 486.72 231 S661 5472 486.72 192 S700 6174 344.72 232 S660 5454 344.72 193 S699 6156 486.72 233 S659 5436 486.72 194 S698 6138 344.72 234 S658 5418 344.72 195 S697 6120 486.72 235 S657 5400 486.72 196 S696 6102 344.72 236 S656 5382 344.72 197 S695 6084 486.72 237 S655 5364 486.72 198 S694 6066 344.72 238 S654 5346 344.72 199 S693 6048 486.72 239 S653 5328 486.72 200 S692 6030 344.72 240 S652 5310 344.72 V1.7 6 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 241 S651 5292 486.72 281 S611 4572 486.72 242 S650 5274 344.72 282 S610 4554 344.72 243 S649 5256 486.72 283 S609 4536 486.72 244 S648 5238 344.72 284 S608 4518 344.72 245 S647 5220 486.72 285 S607 4500 486.72 246 S646 5202 344.72 286 S606 4482 344.72 247 S645 5184 486.72 287 S605 4464 486.72 248 S644 5166 344.72 288 S604 4446 344.72 249 S643 5148 486.72 289 S603 4428 486.72 250 S642 5130 344.72 290 S602 4410 344.72 251 S641 5112 486.72 291 S601 4392 486.72 252 S640 5094 344.72 292 S600 4374 344.72 253 S639 5076 486.72 293 S599 4356 486.72 254 S638 5058 344.72 294 S598 4338 344.72 255 S637 5040 486.72 295 S597 4320 486.72 256 S636 5022 344.72 296 S596 4302 344.72 257 S635 5004 486.72 297 S595 4284 486.72 258 S634 4986 344.72 298 S594 4266 344.72 259 S633 4968 486.72 299 S593 4248 486.72 260 S632 4950 344.72 300 S592 4230 344.72 261 S631 4932 486.72 301 S591 4212 486.72 262 S630 4914 344.72 302 S590 4194 344.72 263 S629 4896 486.72 303 S589 4176 486.72 264 S628 4878 344.72 304 S588 4158 344.72 265 S627 4860 486.72 305 S587 4140 486.72 266 S626 4842 344.72 306 S586 4122 344.72 267 S625 4824 486.72 307 S585 4104 486.72 268 S624 4806 344.72 308 S584 4086 344.72 269 S623 4788 486.72 309 S583 4068 486.72 270 S622 4770 344.72 310 S582 4050 344.72 271 S621 4752 486.72 311 S581 4032 486.72 272 S620 4734 344.72 312 S580 4014 344.72 273 S619 4716 486.72 313 S579 3996 486.72 274 S618 4698 344.72 314 S578 3978 344.72 275 S617 4680 486.72 315 S577 3960 486.72 276 S616 4662 344.72 316 S576 3942 344.72 277 S615 4644 486.72 317 S575 3924 486.72 278 S614 4626 344.72 318 S574 3906 344.72 279 S613 4608 486.72 319 S573 3888 486.72 280 S612 4590 344.72 320 S572 3870 344.72 V1.7 7 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 321 S571 3852 486.72 361 S531 3132 486.72 322 S570 3834 344.72 362 S530 3114 344.72 323 S569 3816 486.72 363 S529 3096 486.72 324 S568 3798 344.72 364 S528 3078 344.72 325 S567 3780 486.72 365 S527 3060 486.72 326 S566 3762 344.72 366 S526 3042 344.72 327 S565 3744 486.72 367 S525 3024 486.72 328 S564 3726 344.72 368 S524 3006 344.72 329 S563 3708 486.72 369 S523 2988 486.72 330 S562 3690 344.72 370 S522 2970 344.72 331 S561 3672 486.72 371 S521 2952 486.72 332 S560 3654 344.72 372 S520 2934 344.72 333 S559 3636 486.72 373 S519 2916 486.72 334 S558 3618 344.72 374 S518 2898 344.72 335 S557 3600 486.72 375 S517 2880 486.72 336 S556 3582 344.72 376 S516 2862 344.72 337 S555 3564 486.72 377 S515 2844 486.72 338 S554 3546 344.72 378 S514 2826 344.72 339 S553 3528 486.72 379 S513 2808 486.72 340 S552 3510 344.72 380 S512 2790 344.72 341 S551 3492 486.72 381 S511 2772 486.72 342 S550 3474 344.72 382 S510 2754 344.72 343 S549 3456 486.72 383 S509 2736 486.72 344 S548 3438 344.72 384 S508 2718 344.72 345 S547 3420 486.72 385 S507 2700 486.72 346 S546 3402 344.72 386 S506 2682 344.72 347 S545 3384 486.72 387 S505 2664 486.72 348 S544 3366 344.72 388 S504 2646 344.72 349 S543 3348 486.72 389 S503 2628 486.72 350 S542 3330 344.72 390 S502 2610 344.72 351 S541 3312 486.72 391 S501 2592 486.72 352 S540 3294 344.72 392 S500 2574 344.72 353 S539 3276 486.72 393 S499 2556 486.72 354 S538 3258 344.72 394 S498 2538 344.72 355 S537 3240 486.72 395 S497 2520 486.72 356 S536 3222 344.72 396 S496 2502 344.72 357 S535 3204 486.72 397 S495 2484 486.72 358 S534 3186 344.72 398 S494 2466 344.72 359 S533 3168 486.72 399 S493 2448 486.72 360 S532 3150 344.72 400 S492 2430 344.72 V1.7 8 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 401 S491 2412 486.72 441 S451 1692 486.72 402 S490 2394 344.72 442 S450 1674 344.72 403 S489 2376 486.72 443 S449 1656 486.72 404 S488 2358 344.72 444 S448 1638 344.72 405 S487 2340 486.72 445 S447 1620 486.72 406 S486 2322 344.72 446 S446 1602 344.72 407 S485 2304 486.72 447 S445 1584 486.72 408 S484 2286 344.72 448 S444 1566 344.72 409 S483 2268 486.72 449 S443 1548 486.72 410 S482 2250 344.72 450 S442 1530 344.72 411 S481 2232 486.72 451 S441 1512 486.72 412 S480 2214 344.72 452 S440 1494 344.72 413 S479 2196 486.72 453 S439 1476 486.72 414 S478 2178 344.72 454 S438 1458 344.72 415 S477 2160 486.72 455 S437 1440 486.72 416 S476 2142 344.72 456 S436 1422 344.72 417 S475 2124 486.72 457 S435 1404 486.72 418 S474 2106 344.72 458 S434 1386 344.72 419 S473 2088 486.72 459 S433 1368 486.72 420 S472 2070 344.72 460 S432 1350 344.72 421 S471 2052 486.72 461 S431 1332 486.72 422 S470 2034 344.72 462 S430 1314 344.72 423 S469 2016 486.72 463 S429 1296 486.72 424 S468 1998 344.72 464 S428 1278 344.72 425 S467 1980 486.72 465 S427 1260 486.72 426 S466 1962 344.72 466 S426 1242 344.72 427 S465 1944 486.72 467 S425 1224 486.72 428 S464 1926 344.72 468 S424 1206 344.72 429 S463 1908 486.72 469 S423 1188 486.72 430 S462 1890 344.72 470 S422 1170 344.72 431 S461 1872 486.72 471 S421 1152 486.72 432 S460 1854 344.72 472 S420 1134 344.72 433 S459 1836 486.72 473 S419 1116 486.72 434 S458 1818 344.72 474 S418 1098 344.72 435 S457 1800 486.72 475 S417 1080 486.72 436 S456 1782 344.72 476 S416 1062 344.72 437 S455 1764 486.72 477 S415 1044 486.72 438 S454 1746 344.72 478 S414 1026 344.72 439 S453 1728 486.72 479 S413 1008 486.72 440 S452 1710 344.72 480 S412 990 344.72 V1.7 9 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 481 S411 972 486.72 521 S371 252 486.72 482 S410 954 344.72 522 S370 234 344.72 483 S409 936 486.72 523 S369 216 486.72 484 S408 918 344.72 524 S368 198 344.72 485 S407 900 486.72 525 S367 180 486.72 486 S406 882 344.72 526 S366 162 344.72 487 S405 864 486.72 527 S365 144 486.72 488 S404 846 344.72 528 S364 126 344.72 489 S403 828 486.72 529 S363 108 486.72 490 S402 810 344.72 530 S362 90 344.72 491 S401 792 486.72 531 S361 72 486.72 492 S400 774 344.72 532 DUMMY 54 344.72 493 S399 756 486.72 533 DUMMY 36 486.72 494 S398 738 344.72 534 DUMMY 18 344.72 495 S397 720 486.72 535 DUMMY 0 486.72 496 S396 702 344.72 536 DUMMY -18 344.72 497 S395 684 486.72 537 DUMMY -36 486.72 498 S394 666 344.72 538 DUMMY -54 344.72 499 S393 648 486.72 539 S360 -72 486.72 500 S392 630 344.72 540 S359 -90 344.715 501 S391 612 486.72 541 S358 -108 486.72 502 S390 594 344.72 542 S357 -126 344.715 503 S389 576 486.72 543 S356 -144 486.72 504 S388 558 344.72 544 S355 -162 344.715 505 S387 540 486.72 545 S354 -180 486.72 506 S386 522 344.72 546 S353 -198 344.715 507 S385 504 486.72 547 S352 -216 486.72 508 S384 486 344.72 548 S351 -234 344.715 509 S383 468 486.72 549 S350 -252 486.72 510 S382 450 344.72 550 S349 -270 344.715 511 S381 432 486.72 551 S348 -288 486.72 512 S380 414 344.72 552 S347 -306 344.715 513 S379 396 486.72 553 S346 -324 486.72 514 S378 378 344.72 554 S345 -342 344.715 515 S377 360 486.72 555 S344 -360 486.72 516 S376 342 344.72 556 S343 -378 344.715 517 S375 324 486.72 557 S342 -396 486.72 518 S374 306 344.72 558 S341 -414 344.715 519 S373 288 486.72 559 S340 -432 486.72 520 S372 270 344.72 560 S339 -450 344.715 V1.7 10 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 561 S338 -468 486.72 601 S298 -1188 486.72 562 S337 -486 344.715 602 S297 -1206 344.715 563 S336 -504 486.72 603 S296 -1224 486.72 564 S335 -522 344.715 604 S295 -1242 344.715 565 S334 -540 486.72 605 S294 -1260 486.72 566 S333 -558 344.715 606 S293 -1278 344.715 567 S332 -576 486.72 607 S292 -1296 486.72 568 S331 -594 344.715 608 S291 -1314 344.715 569 S330 -612 486.72 609 S290 -1332 486.72 570 S329 -630 344.715 610 S289 -1350 344.715 571 S328 -648 486.72 611 S288 -1368 486.72 572 S327 -666 344.715 612 S287 -1386 344.715 573 S326 -684 486.72 613 S286 -1404 486.72 574 S325 -702 344.715 614 S285 -1422 344.715 575 S324 -720 486.72 615 S284 -1440 486.72 576 S323 -738 344.715 616 S283 -1458 344.715 577 S322 -756 486.72 617 S282 -1476 486.72 578 S321 -774 344.715 618 S281 -1494 344.715 579 S320 -792 486.72 619 S280 -1512 486.72 580 S319 -810 344.715 620 S279 -1530 344.715 581 S318 -828 486.72 621 S278 -1548 486.72 582 S317 -846 344.715 622 S277 -1566 344.715 583 S316 -864 486.72 623 S276 -1584 486.72 584 S315 -882 344.715 624 S275 -1602 344.715 585 S314 -900 486.72 625 S274 -1620 486.72 586 S313 -918 344.715 626 S273 -1638 344.715 587 S312 -936 486.72 627 S272 -1656 486.72 588 S311 -954 344.715 628 S271 -1674 344.715 589 S310 -972 486.72 629 S270 -1692 486.72 590 S309 -990 344.715 630 S269 -1710 344.715 591 S308 -1008 486.72 631 S268 -1728 486.72 592 S307 -1026 344.715 632 S267 -1746 344.715 593 S306 -1044 486.72 633 S266 -1764 486.72 594 S305 -1062 344.715 634 S265 -1782 344.715 595 S304 -1080 486.72 635 S264 -1800 486.72 596 S303 -1098 344.715 636 S263 -1818 344.715 597 S302 -1116 486.72 637 S262 -1836 486.72 598 S301 -1134 344.715 638 S261 -1854 344.715 599 S300 -1152 486.72 639 S260 -1872 486.72 600 S299 -1170 344.715 640 S259 -1890 344.715 V1.7 11 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 641 S258 -1908 486.72 681 S218 -2628 486.72 642 S257 -1926 344.715 682 S217 -2646 344.715 643 S256 -1944 486.72 683 S216 -2664 486.72 644 S255 -1962 344.715 684 S215 -2682 344.715 645 S254 -1980 486.72 685 S214 -2700 486.72 646 S253 -1998 344.715 686 S213 -2718 344.715 647 S252 -2016 486.72 687 S212 -2736 486.72 648 S251 -2034 344.715 688 S211 -2754 344.715 649 S250 -2052 486.72 689 S210 -2772 486.72 650 S249 -2070 344.715 690 S209 -2790 344.715 651 S248 -2088 486.72 691 S208 -2808 486.72 652 S247 -2106 344.715 692 S207 -2826 344.715 653 S246 -2124 486.72 693 S206 -2844 486.72 654 S245 -2142 344.715 694 S205 -2862 344.715 655 S244 -2160 486.72 695 S204 -2880 486.72 656 S243 -2178 344.715 696 S203 -2898 344.715 657 S242 -2196 486.72 697 S202 -2916 486.72 658 S241 -2214 344.715 698 S201 -2934 344.715 659 S240 -2232 486.72 699 S200 -2952 486.72 660 S239 -2250 344.715 700 S199 -2970 344.715 661 S238 -2268 486.72 701 S198 -2988 486.72 662 S237 -2286 344.715 702 S197 -3006 344.715 663 S236 -2304 486.72 703 S196 -3024 486.72 664 S235 -2322 344.715 704 S195 -3042 344.715 665 S234 -2340 486.72 705 S194 -3060 486.72 666 S233 -2358 344.715 706 S193 -3078 344.715 667 S232 -2376 486.72 707 S192 -3096 486.72 668 S231 -2394 344.715 708 S191 -3114 344.715 669 S230 -2412 486.72 709 S190 -3132 486.72 670 S229 -2430 344.715 710 S189 -3150 344.715 671 S228 -2448 486.72 711 S188 -3168 486.72 672 S227 -2466 344.715 712 S187 -3186 344.715 673 S226 -2484 486.72 713 S186 -3204 486.72 674 S225 -2502 344.715 714 S185 -3222 344.715 675 S224 -2520 486.72 715 S184 -3240 486.72 676 S223 -2538 344.715 716 S183 -3258 344.715 677 S222 -2556 486.72 717 S182 -3276 486.72 678 S221 -2574 344.715 718 S181 -3294 344.715 679 S220 -2592 486.72 719 S180 -3312 486.72 680 S219 -2610 344.715 720 S179 -3330 344.715 V1.7 12 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 721 S178 -3348 486.72 761 S138 -4068 486.72 722 S177 -3366 344.715 762 S137 -4086 344.715 723 S176 -3384 486.72 763 S136 -4104 486.72 724 S175 -3402 344.715 764 S135 -4122 344.715 725 S174 -3420 486.72 765 S134 -4140 486.72 726 S173 -3438 344.715 766 S133 -4158 344.715 727 S172 -3456 486.72 767 S132 -4176 486.72 728 S171 -3474 344.715 768 S131 -4194 344.715 729 S170 -3492 486.72 769 S130 -4212 486.72 730 S169 -3510 344.715 770 S129 -4230 344.715 731 S168 -3528 486.72 771 S128 -4248 486.72 732 S167 -3546 344.715 772 S127 -4266 344.715 733 S166 -3564 486.72 773 S126 -4284 486.72 734 S165 -3582 344.715 774 S125 -4302 344.715 735 S164 -3600 486.72 775 S124 -4320 486.72 736 S163 -3618 344.715 776 S123 -4338 344.715 737 S162 -3636 486.72 777 S122 -4356 486.72 738 S161 -3654 344.715 778 S121 -4374 344.715 739 S160 -3672 486.72 779 S120 -4392 486.72 740 S159 -3690 344.715 780 S119 -4410 344.715 741 S158 -3708 486.72 781 S118 -4428 486.72 742 S157 -3726 344.715 782 S117 -4446 344.715 743 S156 -3744 486.72 783 S116 -4464 486.72 744 S155 -3762 344.715 784 S115 -4482 344.715 745 S154 -3780 486.72 785 S114 -4500 486.72 746 S153 -3798 344.715 786 S113 -4518 344.715 747 S152 -3816 486.72 787 S112 -4536 486.72 748 S151 -3834 344.715 788 S111 -4554 344.715 749 S150 -3852 486.72 789 S110 -4572 486.72 750 S149 -3870 344.715 790 S109 -4590 344.715 751 S148 -3888 486.72 791 S108 -4608 486.72 752 S147 -3906 344.715 792 S107 -4626 344.715 753 S146 -3924 486.72 793 S106 -4644 486.72 754 S145 -3942 344.715 794 S105 -4662 344.715 755 S144 -3960 486.72 795 S104 -4680 486.72 756 S143 -3978 344.715 796 S103 -4698 344.715 757 S142 -3996 486.72 797 S102 -4716 486.72 758 S141 -4014 344.715 798 S101 -4734 344.715 759 S140 -4032 486.72 799 S100 -4752 486.72 760 S139 -4050 344.715 800 S99 -4770 344.715 V1.7 13 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 801 S98 -4788 486.72 841 S58 -5508 486.72 802 S97 -4806 344.715 842 S57 -5526 344.715 803 S96 -4824 486.72 843 S56 -5544 486.72 804 S95 -4842 344.715 844 S55 -5562 344.715 805 S94 -4860 486.72 845 S54 -5580 486.72 806 S93 -4878 344.715 846 S53 -5598 344.715 807 S92 -4896 486.72 847 S52 -5616 486.72 808 S91 -4914 344.715 848 S51 -5634 344.715 809 S90 -4932 486.72 849 S50 -5652 486.72 810 S89 -4950 344.715 850 S49 -5670 344.715 811 S88 -4968 486.72 851 S48 -5688 486.72 812 S87 -4986 344.715 852 S47 -5706 344.715 813 S86 -5004 486.72 853 S46 -5724 486.72 814 S85 -5022 344.715 854 S45 -5742 344.715 815 S84 -5040 486.72 855 S44 -5760 486.72 816 S83 -5058 344.715 856 S43 -5778 344.715 817 S82 -5076 486.72 857 S42 -5796 486.72 818 S81 -5094 344.715 858 S41 -5814 344.715 819 S80 -5112 486.72 859 S40 -5832 486.72 820 S79 -5130 344.715 860 S39 -5850 344.715 821 S78 -5148 486.72 861 S38 -5868 486.72 822 S77 -5166 344.715 862 S37 -5886 344.715 823 S76 -5184 486.72 863 S36 -5904 486.72 824 S75 -5202 344.715 864 S35 -5922 344.715 825 S74 -5220 486.72 865 S34 -5940 486.72 826 S73 -5238 344.715 866 S33 -5958 344.715 827 S72 -5256 486.72 867 S32 -5976 486.72 828 S71 -5274 344.715 868 S31 -5994 344.715 829 S70 -5292 486.72 869 S30 -6012 486.72 830 S69 -5310 344.715 870 S29 -6030 344.715 831 S68 -5328 486.72 871 S28 -6048 486.72 832 S67 -5346 344.715 872 S27 -6066 344.715 833 S66 -5364 486.72 873 S26 -6084 486.72 834 S65 -5382 344.715 874 S25 -6102 344.715 835 S64 -5400 486.72 875 S24 -6120 486.72 836 S63 -5418 344.715 876 S23 -6138 344.715 837 S62 -5436 486.72 877 S22 -6156 486.72 838 S61 -5454 344.715 878 S21 -6174 344.715 839 S60 -5472 486.72 879 S20 -6192 486.72 840 S59 -5490 344.715 880 S19 -6210 344.715 V1.7 14 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 881 S18 -6228 486.72 921 G33 -6948 486.72 882 S17 -6246 344.715 922 G35 -6966 344.72 883 S16 -6264 486.72 923 G37 -6984 486.72 884 S15 -6282 344.715 924 G39 -7002 344.72 885 S14 -6300 486.72 925 G41 -7020 486.72 886 S13 -6318 344.715 926 G43 -7038 344.72 887 S12 -6336 486.72 927 G45 -7056 486.72 888 S11 -6354 344.715 928 G47 -7074 344.72 889 S10 -6372 486.72 929 G49 -7092 486.72 890 S9 -6390 344.715 930 G51 -7110 344.72 891 S8 -6408 486.72 931 G53 -7128 486.72 892 S7 -6426 344.715 932 G55 -7146 344.72 893 S6 -6444 486.72 933 G57 -7164 486.72 894 S5 -6462 344.715 934 G59 -7182 344.72 895 S4 -6480 486.72 935 G61 -7200 486.72 896 S3 -6498 344.715 936 G63 -7218 344.72 897 S2 -6516 486.72 937 G65 -7236 486.72 898 S1 -6534 344.715 938 G67 -7254 344.72 899 DUMMY -6552 486.72 939 G69 -7272 486.72 900 DUMMY -6570 344.72 940 G71 -7290 344.72 901 DUMMY -6588 486.72 941 G73 -7308 486.72 902 DUMMY -6606 344.72 942 G75 -7326 344.72 903 DUMMY -6624 486.72 943 G77 -7344 486.72 904 DUMMY -6642 344.72 944 G79 -7362 344.72 905 G1 -6660 486.72 945 G81 -7380 486.72 906 G3 -6678 344.72 946 G83 -7398 344.72 907 G5 -6696 486.72 947 G85 -7416 486.72 908 G7 -6714 344.72 948 G87 -7434 344.72 909 G9 -6732 486.72 949 G89 -7452 486.72 910 G11 -6750 344.72 950 G91 -7470 344.72 911 G13 -6768 486.72 951 G93 -7488 486.72 912 G15 -6786 344.72 952 G95 -7506 344.72 913 G17 -6804 486.72 953 G97 -7524 486.72 914 G19 -6822 344.72 954 G99 -7542 344.72 915 G21 -6840 486.72 955 G101 -7560 486.72 916 G23 -6858 344.72 956 G103 -7578 344.72 917 G25 -6876 486.72 957 G105 -7596 486.72 918 G27 -6894 344.72 958 G107 -7614 344.72 919 G29 -6912 486.72 959 G109 -7632 486.72 920 G31 -6930 344.72 960 G111 -7650 344.72 V1.7 15 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 961 G113 -7668 486.72 1001 G193 -8388 486.72 962 G115 -7686 344.72 1002 G195 -8406 344.72 963 G117 -7704 486.72 1003 G197 -8424 486.72 964 G119 -7722 344.72 1004 G199 -8442 344.72 965 G121 -7740 486.72 1005 G201 -8460 486.72 966 G123 -7758 344.72 1006 G203 -8478 344.72 967 G125 -7776 486.72 1007 G205 -8496 486.72 968 G127 -7794 344.72 1008 G207 -8514 344.72 969 G129 -7812 486.72 1009 G209 -8532 486.72 970 G131 -7830 344.72 1010 G211 -8550 344.72 971 G133 -7848 486.72 1011 G213 -8568 486.72 972 G135 -7866 344.72 1012 G215 -8586 344.72 973 G137 -7884 486.72 1013 G217 -8604 486.72 974 G139 -7902 344.72 1014 G219 -8622 344.72 975 G141 -7920 486.72 1015 G221 -8640 486.72 976 G143 -7938 344.72 1016 G223 -8658 344.72 977 G145 -7956 486.72 1017 G225 -8676 486.72 978 G147 -7974 344.72 1018 G227 -8694 344.72 979 G149 -7992 486.72 1019 G229 -8712 486.72 980 G151 -8010 344.72 1020 G231 -8730 344.72 981 G153 -8028 486.72 1021 G233 -8748 486.72 982 G155 -8046 344.72 1022 G235 -8766 344.72 983 G157 -8064 486.72 1023 G237 -8784 486.72 984 G159 -8082 344.72 1024 G239 -8802 344.72 985 G161 -8100 486.72 1025 G241 -8820 486.72 986 G163 -8118 344.72 1026 G243 -8838 344.72 987 G165 -8136 486.72 1027 G245 -8856 486.72 988 G167 -8154 344.72 1028 G247 -8874 344.72 989 G169 -8172 486.72 1029 G249 -8892 486.72 990 G171 -8190 344.72 1030 G251 -8910 344.72 991 G173 -8208 486.72 1031 G253 -8928 486.72 992 G175 -8226 344.72 1032 G255 -8946 344.72 993 G177 -8244 486.72 1033 G257 -8964 486.72 994 G179 -8262 344.72 1034 G259 -8982 344.72 995 G181 -8280 486.72 1035 G261 -9000 486.72 996 G183 -8298 344.72 1036 G263 -9018 344.72 997 G185 -8316 486.72 1037 G265 -9036 486.72 998 G187 -8334 344.72 1038 G267 -9054 344.72 999 G189 -8352 486.72 1039 G269 -9072 486.72 1000 G191 -8370 344.72 1040 G271 -9090 344.72 V1.7 16 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 1041 G273 -9108 486.72 1081 DGNDO -8705 -450.28 1042 G275 -9126 344.72 1082 RCM0 -8625 -450.28 1043 G277 -9144 486.72 1083 VDDIO -8545 -450.28 1044 G279 -9162 344.72 1084 RCM1 -8465 -450.28 1045 G281 -9180 486.72 1085 DGNDO -8385 -450.28 1046 G283 -9198 344.72 1086 SRGB -8305 -450.28 1047 G285 -9216 486.72 1087 VDDIO -8225 -450.28 1048 G287 -9234 344.72 1088 SMX -8145 -450.28 1049 G289 -9252 486.72 1089 DGNDO -8065 -450.28 1050 G291 -9270 344.72 1090 SMY -7985 -450.28 1051 G293 -9288 486.72 1091 VDDIO -7905 -450.28 1052 G295 -9306 344.72 1092 IDM -7825 -450.28 1053 G297 -9324 486.72 1093 DGNDO -7745 -450.28 1054 G299 -9342 344.72 1094 REV -7665 -450.28 1055 G301 -9360 486.72 1095 VDDIO -7585 -450.28 1056 G303 -9378 344.72 1096 RL -7505 -450.28 1057 G305 -9396 486.72 1097 DGNDO -7425 -450.28 1058 G307 -9414 344.72 1098 TB -7345 -450.28 1059 G309 -9432 486.72 1099 VDDIO -7265 -450.28 1060 G311 -9450 344.72 1100 SHUT -7185 -450.28 1061 G313 -9468 486.72 1101 DGNDO -7105 -450.28 1062 G315 -9486 344.72 1102 GS -7025 -450.28 1063 G317 -9504 486.72 1103 LCM1 -6945 -450.28 1064 G319 -9522 344.72 1104 LCM0 -6865 -450.28 1065 DUMMY -9540 486.72 1105 VDDIO -6785 -450.28 1066 DUMMY -9558 344.72 1106 TP0 -6705 -450.28 1067 DUMMY -9576 486.72 1107 TP1 -6625 -450.28 1068 DUMMY -9594 344.72 1108 TP2 -6545 -450.28 1069 DUMMY -9612 486.72 1109 TP3 -6465 -450.28 1070 DUMMY -9585 -450.28 1110 D17 -6385 -450.28 1071 DUMMY -9505 -450.28 1111 D16 -6305 -450.28 1072 EXTC -9425 -450.28 1112 D15 -6225 -450.28 1073 DGNDO -9345 -450.28 1113 D14 -6145 -450.28 1074 IM0 -9265 -450.28 1114 D13 -6065 -450.28 1075 VDDIO -9185 -450.28 1115 D12 -5985 -450.28 1076 IM1 -9105 -450.28 1116 D11 -5905 -450.28 1077 DGNDO -9025 -450.28 1117 D10 -5825 -450.28 1078 IM2 -8945 -450.28 1118 D9 -5745 -450.28 1079 VDDIO -8865 -450.28 1119 D8 -5665 -450.28 1080 P68 -8785 -450.28 1120 DGNDO -5585 -450.28 V1.7 17 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 1121 DUMMY -5505 -450.28 1161 DGND -2380 -450.28 1122 TEST_EN -5425 -450.28 1162 DGND -2315 -450.28 1123 D7 -5345 -450.28 1163 DGND -2250 -450.28 1124 D6 -5265 -450.28 1164 VDDI -2170 -450.28 1125 D5 -5185 -450.28 1165 VDDI -2105 -450.28 1126 D4 -5105 -450.28 1166 VDDI -2040 -450.28 1127 D3 -5025 -450.28 1167 VDDI -1975 -450.28 1128 D2 -4945 -450.28 1168 VREF -1895 -450.28 1129 D1 -4865 -450.28 1169 VREF -1830 -450.28 1130 D0 -4785 -450.28 1170 VREF -1765 -450.28 1131 TPO0 -4705 -450.28 1171 REGP -1685 -450.28 1132 TPO1 -4625 -450.28 1172 REGPT -1605 -450.28 1133 TPO2 -4545 -450.28 1173 VCC -1525 -450.28 1134 TPO3 -4465 -450.28 1174 VCC -1460 -450.28 1135 TPO4 -4385 -450.28 1175 VCC -1395 -450.28 1136 TPO5 -4305 -450.28 1176 VCC -1330 -450.28 1137 TPO6 -4225 -450.28 1177 VCC -1265 -450.28 1138 TPO7 -4145 -450.28 1178 VCC -1200 -450.28 1139 OSC -4065 -450.28 1179 DUMMY -1120 -450.28 1140 TE -3985 -450.28 1180 DUMMY -1040 -450.28 1141 CSX -3905 -450.28 1181 VCI1 -960 -450.28 1142 RDX -3825 -450.28 1182 VCI1 -895 -450.28 1143 WRX -3745 -450.28 1183 VCI1 -830 -450.28 1144 SDA -3665 -450.28 1184 VCI1 -765 -450.28 1145 DUMMY -3585 -450.28 1185 AGND -685 -450.28 1146 AUTO -3505 -450.28 1186 AGND -620 -450.28 1147 RESX -3425 -450.28 1187 AGND -555 -450.28 1148 DGND -3345 -450.28 1188 AGND -490 -450.28 1149 D/CX -3265 -450.28 1189 AGND -425 -450.28 1150 DGND -3185 -450.28 1190 AGND -360 -450.28 1151 PCLK -3105 -450.28 1191 AGND -295 -450.28 1152 DGND -3025 -450.28 1192 AGND -230 -450.28 1153 DE -2945 -450.28 1193 VDD -150 -450.28 1154 HS -2865 -450.28 1194 VDD -85 -450.28 1155 VS -2785 -450.28 1195 VDD -20 -450.28 1156 DGND -2705 -450.28 1196 VDD 45 -450.28 1157 DGND -2640 -450.28 1197 VDD 110 -450.28 1158 DGND -2575 -450.28 1198 VDD 175 -450.28 1159 DGND -2510 -450.28 1199 VDD 240 -450.28 1160 DGND -2445 -450.28 1200 VDD 305 -450.28 V1.7 18 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 1201 VDD 370 -450.28 1241 C12N 3075 -450.28 1202 VDD 435 -450.28 1242 C12N 3140 -450.28 1203 AVDD 515 -450.28 1243 C12N 3205 -450.28 1204 AVDD 580 -450.28 1244 C12N 3270 -450.28 1205 AVDD 645 -450.28 1245 C12N 3335 -450.28 1206 AVDD 710 -450.28 1246 DUMMY 3415 -450.28 1207 AVDD 775 -450.28 1247 DUMMY 3495 -450.28 1208 AVDD 840 -450.28 1248 AGND 3575 -450.28 1209 AVDD 905 -450.28 1249 AGND 3640 -450.28 1210 AVDDO 970 -450.28 1250 AGND 3705 -450.28 1211 AVDDO 1035 -450.28 1251 AGND 3770 -450.28 1212 AVDDS 1100 -450.28 1252 AGND 3835 -450.28 1213 C1SO 1180 -450.28 1253 AGND 3900 -450.28 1214 C1SO 1245 -450.28 1254 AGND 3965 -450.28 1215 VC1S 1310 -450.28 1255 AGND 4030 -450.28 1216 VC1S 1375 -450.28 1256 DUMMY 4110 -450.28 1217 VC1S 1440 -450.28 1257 DUMMY 4190 -450.28 1218 VC1S 1505 -450.28 1258 VCL 4270 -450.28 1219 GVDD 1585 -450.28 1259 VCL 4335 -450.28 1220 GVDD 1650 -450.28 1260 VCL 4400 -450.28 1221 GVDD 1715 -450.28 1261 VCLO 4465 -450.28 1222 C11P 1795 -450.28 1262 VCLO 4530 -450.28 1223 C11P 1860 -450.28 1263 VCLS 4595 -450.28 1224 C11P 1925 -450.28 1264 C21P 4675 -450.28 1225 C11P 1990 -450.28 1265 C21P 4740 -450.28 1226 C11P 2055 -450.28 1266 C21P 4805 -450.28 1227 C11P 2120 -450.28 1267 C21P 4870 -450.28 1228 C11N 2200 -450.28 1268 C21N 4950 -450.28 1229 C11N 2265 -450.28 1269 C21N 5015 -450.28 1230 C11N 2330 -450.28 1270 C21N 5080 -450.28 1231 C11N 2395 -450.28 1271 C21N 5145 -450.28 1232 C11N 2460 -450.28 1272 C22P 5225 -450.28 1233 C11N 2525 -450.28 1273 C22P 5290 -450.28 1234 C12P 2605 -450.28 1274 C22P 5355 -450.28 1235 C12P 2670 -450.28 1275 C22P 5420 -450.28 1236 C12P 2735 -450.28 1276 C22N 5500 -450.28 1237 C12P 2800 -450.28 1277 C22N 5565 -450.28 1238 C12P 2865 -450.28 1278 C22N 5630 -450.28 1239 C12P 2930 -450.28 1279 C22N 5695 -450.28 1240 C12N 3010 -450.28 1280 C23P 5775 -450.28 V1.7 19 2008.04.18 ST7787 PAD No. PIN Name X Y PAD No. PIN Name X Y 1281 C23P 5840 -450.28 1321 VCOM 8620 -450.28 1282 C23P 5905 -450.28 1322 VCOM 8685 -450.28 1283 C23P 5970 -450.28 1323 VCOM 8750 -450.28 1284 C23N 6050 -450.28 1324 VCOM 8815 -450.28 1285 C23N 6115 -450.28 1325 VCOM 8880 -450.28 1286 C23N 6180 -450.28 1326 VCOM 8945 -450.28 1287 C23N 6245 -450.28 1327 VCOM 9010 -450.28 1288 DUMMY 6325 -450.28 1328 DUMMY 9090 -450.28 1289 DUMMY 6405 -450.28 1329 DUMMY 9170 -450.28 1290 VGL 6485 -450.28 1330 VPP 9250 -450.28 1291 VGL 6550 -450.28 1331 VPP 9315 -450.28 1292 VGL 6615 -450.28 1332 VPP 9380 -450.28 1293 VGL 6680 -450.28 1333 VPP 9445 -450.28 1294 VGLS 6745 -450.28 1334 DUMMY 9525 -450.28 1295 DUMMY 6825 -450.28 1335 DUMMY 9605 -450.28 1296 DUMMY 6905 -450.28 1297 VGH 6985 -450.28 1298 VGH 7050 -450.28 1299 VGHO 7115 -450.28 1300 VGHO 7180 -450.28 1301 VGHS 7245 -450.28 1302 DUMMY 7325 -450.28 1303 DUMMY 7405 -450.28 1304 VCOMH 7485 -450.28 1305 VCOMH 7550 -450.28 1306 VCOMH 7615 -450.28 1307 VCOMH 7680 -450.28 1308 VCOMH 7745 -450.28 1309 VCOMH 7810 -450.28 1310 VCOMH 7875 -450.28 1311 VCOMH 7940 -450.28 1312 VCOML 8020 -450.28 1313 VCOML 8085 -450.28 1314 VCOML 8150 -450.28 1315 VCOML 8215 -450.28 1316 VCOML 8280 -450.28 1317 VCOML 8345 -450.28 1318 VCOML 8410 -450.28 1319 VCOML 8475 -450.28 1320 VCOM 8555 -450.28 V1.7 20 2008.04.18 ST7787 VCI1 VREF GVDD 5. Block diagram 320 Gate buffer Voltage reference 720 Source buffer Level shifter DAC Gamma circuit Gate decoder Level Shifter VCOMH Data Latch Gamma Table Vcom generator VCOM VCOML Display Ram 240 x 18 x 320 Color conversion LUT table Display control OSC C11P Instruction register C11N Mutiple OTP C12P C12N Booster 1/2/4 C21P C21N C22P C22N RGB I/F MCU IF C23P C23N 21 VDD VDDI AVDD VCL VGH VGL SMY SMX EXTC P68 IM [2:0] DC/X (SCL) CSX RDX WRX GS SRGB RCM [1:0] LCM [1:0] D[17:0] SDA VSYNC HSYNC DE PCLK SHUT TB RL REV IDM V1.7 2008.04.18 ST7787 6. Pin description 6.1 Power supply pin Name VDD VDDI VPP AGND DGND I/O I I I I I Description Power supply for analog, digital system and booster circuit Power supply for I/O system Power supply for OTP circuit System ground for analog system and booster circuit System ground for I/O system and internal digital system Count 10 4 4 16 11 Connect pin VDD VDDI VPP GND GND Count Connect pin 1 GND/VDDI 3 GND/VDDI 1 MCU 1 MCU 1 MCU 1 MCU 1 MCU 1 MCU DGND/VDDI 1 - 18 MCU 1 MCU 1 RGB interface 1 RGB interface 1 RGB interface 1 RGB interface 6.2 Interface logic pin Name I/O P68 I IM0~IM2 I RESX I CSX I D/CX (SCL) I RDX (E) I WRX I SDA I OSC O D[17:0] I/O TE I/O PCLK I VS I HS I DE I V1.7 Description -8080/6800 MCU interface mode select -P68=’1’, select 6800 MCU parallel interface -P68=’0’, select 8080 MCU parallel interface -If not used, please fix this pin at VDDI or DGND level -Selection for MCU parallel interface or serial interface -If not used, please connect this pin to VDDI or DGND IM2 MCU & SPI interface mode selection 0 SPI interface 1 MCU parallel interface -This signal will reset the device and it must be applied to properly initialize the chip -Signal is active low -Chip select input pin (“Low” is enable) -This pin can be permanently fixed “Low” in MCU interface mode only -Display data/command selection pin in MCU interface -D/CX=’1’: display data -D/CX=’0’: command data -In serial interface, this is used as SCL -If not used, please connect this pin to VDDI or DGND -Read enable in 8080 MCU parallel interface -Read/write operation enable pin in 6800 MCU parallel interface -If not used, please connect this pin to VDDI or DGND -Write enable in MCU parallel interface - Read/write operation enable pin in 8080 MCU parallel interface -If not used, please connect this pin to VDDI or DGND -In RGB interface, WRX are not used and should be connected to VDDI -When RCM1, RCM0=’1X’ (RGB interface), this pin is used as serial input/output pin. -When RCM1, RCM0=’0X’ (MCU interface), this pin is not used and please connect to VDDI or DGND level. The serial input/output pin in MCU interface mode is D0. -Monitoring pin of internal oscillator clock and is turned ON/OFF by S/W command -When this pin is inactive (function OFF), this pin is DGND level -If not used, please keep this pin open -When RCM=”1” (RGB interface), D[17:0] are used as RGB interface data bus -When RCM=”0” (MCU interface), D[17:0] are used as MCU parallel interface data bus -D0 is the serial input/output signal in serial interface mode -In serial interface, D[17:1] are not used and should be connected to VDDI or DGND -Tearing effect output pin to synchronies MCU to frame writing, activated by S/W command -External VSYNC signal input pin with MCU interface. -When this pin is not inactive, this pin is low -If not used, please open this pin -Pixel clock signal in RGB interface mode -If not used, please fix this pin at VDDI or DGND -Vertical sync. Signal in RGB interface mode -If not used, please fix this pin at VDDI or DGND -Horizontal sync. Signal in RGB interface mode -If not used, please fix this pin at VDDI or DGND -Data enable signal in RGB interface mode 22 2008.04.18 ST7787 -If not used, please fix this pin at VDDI or DGND Note1. If CSX is connected to ground in parallel interface mode, there will be no abnormal visible effect on the display module. Also there will be no restriction on using the parallel Read/Write protocols, power On/Off sequences or other functions. Furthermore there will be no influence to the power consumption of the display module. Note2. When in 8-line parallel mode (IM2 , IM1, IM0 =”001”) then if some data or signal appears on D[17:8] then it will have no influence to the system. (D[17:8] can be connected to”1” or ”0”’) Note3. When CSX=”1”, there is no influence to the parallel and serial interface. Note4. “1” = VDDI level, “0” = DGND level. V1.7 23 2008.04.18 ST7787 6.3 Mode selection pin Name I/O EXTC I Description -To use extended command set, please connect this pin to VDDI -During normal operation, please open this pin (internal Rpull-down=2MΩ) EXTC Enable/disable modification of extend command 0 Only use default command set Use extended command table 1 (command register can be modify by user) -Gamma arrangement selection pin when LCM[1]=0,LCM[0]=0 GS GC[7:0] Reg. LCM1 LCM0 LC Type 0 0 MVA 0 1 Transflective(TR) 01H GS I Transmissive(TM) 1 1 N/A 02H X X Transflective(TR) 1.8 04H X X Transflective(TR) 2.5 08H X X Transflective(TR) 1.0 01H X X Transflective(TR) 1.0 02H X X Transflective(TR) 2.5 0 0 MVA 0 1 Transflective(TR) 1 0 Transmissive(TM) 1 1 N/A X X 04H 08H IDM I LCM1, LCM0 I RCM1, RCM0 I SRGB I SMX I SMY I V1.7 1 VDDI/GND 1 VDDI/GND 1 VDDI/GND 1 VDDI/GND 2 VDDI/GND 1 VDDI/GND 1 VDDI/GND 1 VDDI/GND Curve 2.2 0 0 Connect pin Gamma 1 1 Count Curve 2.2 Transflective(TR) 1.8 -Normal mode and Idle mode selection pin -Please refer RGB interface for detail usage IDM Enable/disable idle mode 0 Normal display (can be changed to Idle mode by S/W) 1 Idle mode enable -Liquid crystal (LC) type selection pins LCM[1:0] Selection of LC type 0 0 MVA 0 1 Transflective 1 0 Transmissive 1 1 Reserved -RGB or MCU interface mode selection pins RCM[1:0] Selection of MCU or RGB interface 00 0 MCU Interface 01 1 MCU Interface 10 2 RGB Interface (1) 11 3 RGB Interface (2) -RGB arrangement selection pin for color filter design SRGB RGB arrangement S1, S2, S3 filter order = ’R’, ’G’, ’B’ 0 S1, S2, S3 filter order = ‘B’, ‘G’, ‘R’ 1 -Please refer chapter 14 for detail using -Scanning direction of source output selection pin SMX Scanning direction of source output 0 S1 -> S720 1 S720 -> S1 -Please refer chapter 14 for detail using -Scanning direction of gate output selection pin SMY Scanning direction of gate output 0 G1 -> G320 24 2008.04.18 ST7787 REV I SHUT I RL I TB I AUTO I TEST_EN I 1 G320 -> G1 -Please refer chapter 14 for detail using -Polarity of source output selection pin REV Polarity of source output 0 Data not reverse 1 Data reverse -Please refer RGB interface for detail using -If not used, please fix this pin at VDDI or DGND -Display On/Off control pin In RGB interface SHUT Display On/Off 0 Display On 1 Display Off -Please refer RGB interface for detail using -If not used, please fix this pin at VDDI or DGND -Scanning direction of source output selection pin in RGB interface RL SMX Scanning direction of source output 0 0 S1 -> S720 0 1 S720 -> S1 1 0 S720 -> S1 1 1 S1 -> S720 -Please refer RGB interface for detail using -If not used, please fix this pin at VDDI or DGND level -Scanning direction of gate output selection pin in RGB interface TB SMY Scanning direction of gate output 0 0 G1 -> G320 0 1 G320 -> G1 1 0 G320 -> G1 1 1 G1 -> G320 -Please refer RGB interface for detail using -If not used, please fix this pin at VDDI or DGND -Enable/disable the automatic power-on sequence AUTO Automatic power-on sequence enable/disable 0 Reserved 1 Enable (auto mode) -Enable/disable the test mode TEST_EN Test mode enable/disable 0 Disable 1 Enable 1 VDDI/GND 1 VDDI/GND 1 VDDI/GND 1 VDDI/GND 1 VDDI 1 VDDI/GND 6.4 Driver output pin Name S1 to S720 G1 to G320 I/O VCI1 I/O AVDD I AVDDO O AVDDS I VC1S I C1SO O VCL I VCLO O VCLS I VGH I VGHO O V1.7 Description Count Connect pin O -Source driver output pins 720 - O -Gate driver output pins 320 - 4 Capacitor 7 Capacitor 2 AVDD 1 AVDD 4 Capacitor 2 C1S 3 Capacitor 2 VCL 1 VCL 2 VGH 2 Capacitor -A reference voltage for step-up circuit 1 -Connect a capacitor for stabilization. -Power input pin for analog circuit block -In normal usage, connect it to AVDD -A power output pin that the voltage is generated from power block -Output of booster 1 circuit -Connect a capacitor for stabilization. - A reference voltage for step-up circuit 2 - A reference voltage for analog circuit including gamma, source and gate - Output of regulator in 2x boost system -Power input pin for VCOM circuit -In normal usage, connect it to VCL -A power output pin of step-up circuit 4 -When VCOML is higher than AGND, VCL=AGND -Connect a capacitor for stabilization - A reference voltage for step-up circuit 2 -Power input pin for gate driver circuit -In normal usage, connect it to VGH -Positive output pin of the step-up circuit 2 25 2008.04.18 ST7787 VGHS I VGL I VGLO O VGLS I VREF O GVDD O VCOMH O VCOML O VCOM O C11P, C11N C12P, C12N C21P, C21N C22P, C22N C23P, C23N VDDIO DGNDO -Connect a capacitor for stabilization - A reference voltage for step-up circuit 2 -Power input pin for gate driver circuit -In normal usage, connect it to VGL -Negative output of the step-up circuit 2 -Connect a capacitor for stabilization - A reference voltage for step-up circuit 2 -Reference voltage for power circuit block. -Connect a capacitor for stabilization -A standard level for grayscale voltage generator -Connect a capacitor for stabilization. -When internal GVDD generator is not used, connect an external power supply (AVDD-0.5V) -Positive voltage output of VCOM -Connect a capacitor for stabilization -Negative voltage output of VCOM -Connect a capacitor for stabilization 1 VGH 2 Capacitor 2 VGL 1 VGL 3 Capacitor 3 Capacitor 8 Capacitor 8 Capacitor -A power supply for the TFT-LCD common electrode 8 Common electrode O -Capacitor connecting pins for step-up circuit 1 (for AVDD) 24 Step-up Capacitor O -Capacitor connecting pins for step-up circuit 2 (for VGH, VGL, VCL) 24 Step-up Capacitor O O -VDDI voltage output level for monitoring -DGND voltage output level for monitoring -Monitoring pin of internal digital reference voltage -Connect a capacitor fir stabilization 8 9 - 6 Capacitor Test pin 2 Open Count Connect pin -Test pins. In regular usage, please open these pins 12 Open -These pins are dummy (have no function inside) -Can allow signal traces pass through under these pads on TFT glass 24 Open VCC O REGP REGPT O 6.5 Test pin Name TPI, TPO Dummy V1.7 I/O I/O Description 26 2008.04.18 ST7787 7. Driver electrical characteristics 7.1 Absolute operation range Item Symbol Rating Unit Supply voltage VDD - 0.3 ~ +4.6 V Supply voltage (Logic) VDDI - 0.3 ~ +4.6 V Supply voltage (Digital) VCC -0.3 ~ +4.6 V Driver supply voltage VGH-VGL -0.3 ~ +30.0 V Logic Input voltage range VIN 0.5 ~ VDDI + 0.5 V Logic Output voltage range VO 0.5 ~ VDDI + 0.5 V Operating temperature range TOPR -30 ~ +70 ℃ Storage temperature range TSTG -55 ~ +125 ℃ Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the recommend range. 7.2 ESD protection level Model Human Body Model Test Condition C = 100 pF, R = 1.5k ohm. 3 times zapping/each pin, 1sec/per zapping C = 200 pF, R = 0.0 ohm. Machine Model 3 times zapping/each pin, 1sec/per zapping Note: connecter pin is DATA BUS, Power, CSX, RDX, WRX, RESX, TE. Protection Level ±2500 for each pin ±3000 for connecter pin Unit ±250 for each pin V V 7.3 Latch-up protection level The device will not latch up at trigger current level less than ±100 mA. 7.4 Light Sensitivity The operation of the IC will not be materially altered by incident light. 7.5 DC characteristic Parameter Specification TYP Max Unit Related Pins 3.3 V Note 2 3.3 V Note 2 1.65 2.0 V Note 2 10 -14 16.5 -5 V V Note 3 Note 3 | VGH-VGL | 19 30 V Note 3 1.65 7.5 3.3 Operating voltage V V VDDI 0.3VDDI VDDI 0.2VDDI 1 Note 1,2,3 Note 1,2,3 Note 1,2,3 Note 1,2,3 Note 1,2,3 Note 1,2,3 Note 1,2,3 Symbol Condition VDD Operating voltage 2.45 2.78 VDDI I/O supply voltage 1.65 1.8/2.78 Digital operating voltage VCC Digital supply voltage Gate driver high voltage Gate driver low voltage Gate driver supply voltage I/O operating voltage OTP operation voltage Input / Output Logic-high input voltage Logic-low input voltage Logic-high output voltage Logic-low output voltage Logic-high input current Logic-low input current Input leakage current VCOM voltage VCOM high voltage VCOM low voltage VCOM amplitude Source driver Source output range Gamma reference voltage Source output settling time VGH VGL Power & operation voltage System voltage Interface operation voltage Output deviation voltage (Source output channel) V1.7 VPP Min 7.8 VIH VIL VOH VOL IIH IIL IIL IOH = -1.0mA IOL = +1.0mA VIN = VDDI or VSS IOH = -1.0mA -1 -0.1 +0.1 V V V V uA uA uA VCOMH VCOML VCOMAC Ccom=12nF Ccom=12nF |VCOMH-VCOML| 2.5 -2.5 4.0 5.0 0.0 6.0 V V V Note 3 Note 3 Note 3 Vsout 0.1 AVDD-0.1 V Note 4 GVDD 3.0 5.0 V Note 3 14 us Note 4,5 20 mV Note 4,5 15 mV Tr Vdev Below with 99% precision Sout >=4.2V, Sout<=0.8V 4.2V>Sout>0.8V 27 0.7VDDI VSS 0.8VDDI VSS 10 2008.04.18 ST7787 Output offset voltage Step-up circuit Internal reference voltage 1st step-up (VDDx2) voltage 1st step-up (VDDx2) drop voltage VOFSET 35 mv Note 6 % Note 3 6.0 V Note 3 4% % Note 3 VREF AVDD VDDx2,dorp 4.95 I AVDD = 2.5mA (include panel loading) Linear range VLinear 0.2 AVDD-0.2 V Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 ℃ Note 2, 3, 4: When the measurements are performed with LCD module, measured points are like below. Note 3: P68, CSX, RDX, WRX, D[17:0], D/CX, RESX, TE, PCLK, VS, HS, EXTC, GS, IDM, SCL, LCM[1:0], RCM[1:0], IM[2:0], SRGB, SMX, SMY, REV, SHUT, RL, TB and Test pins Note 5, Source channel loading= 2.2kohm , 10pF/channel, Gate channel loading=0.8kohm , 50pF/channel. Note 6, The Max. value is between measured point of note 4 and gamma setting value. Fig. 7.5.1 Example of measured point on the panel Fig. 7.5.2 Tr: the source output stabling time. Fig. 7.5.3 Source output deviation (channel to channel). -When Sout >=4.2V, Sout<=0.8V Max (S1, S2, S3, …. , S720) – Min (S1, S2, S3, …. , S720) <= 20mV -When 4.2V>Sout>0.8V Max (S1, S2, S3, …. , S720) – Min (S1, S2, S3, …. , S720) <= 6mV -Example When Sout level is 3.95V (Gray scale voltage) Max (S1, S2, S3, …. , S720) = 3.96V Min (S1, S2, S3, … , S720) = 3.944V Sout deviation =Max (S1, S2, S3, …. , S720) – Min (S1, S2, S3, …. , S720) = 10mV <- Out of Spec V1.7 28 2008.04.18 ST7787 7.6 Power consumption Operation mode Current consumption Typical Maximum IDDI IDD IDDI IDD (uA) (mA) (uA) (mA) Inversion mode Image One Line Note 1 1 2.6 1 3.0 One Line Note 2 1 2.5 1 2.8 One Line Note 3,4 1 0.65 1 0.8 N/A N/A 1 9uA 1 9uA -Normal mode -Partial + Idle mode (40 lines) -Sleep-in mode Notes: 1. All pixels black. 2. Grayscale from top to bottom. 3. Black & white checker board 8 by 8 4. Absolute worst case patterns: all pixels black. V1.7 Typical case: TA = 25 ℃ VDD = 2.78 V VDDI = 1.80 V Worst Case: TA = -30 to 70℃ VDD = 2.45 V to 3.3 V VDDI = 1.65 V to 3.3 V Includes process variance. 29 2008.04.18 ST7787 8. Timing chart 8.1 Parallel interface characteristics: 18, 16, 9 or 8-bits bus (8080-series MCU interface) Fig. 8.1.1 Parallel interface timing characteristics (8080-series MCU interface) Signal Symbol Parameter Min Max TAST Address setup time 10 D/CX TAHT Address hold time (Write/Read) 10 TCHW Chip select “H” pulse width 0 TCS Chip select setup time (Write) 15 TRCS Chip select setup time (Read ID) 45 CSX TRCSFM Chip select setup time (Read RAM) 355 TCSF Chip select wait time (Write/Read) 10 TCSH Chip select hold time 10 TWC Write cycle 66 WRX TWRH Control pulse “H” duration 20 TWRL Control pulse “L” duration 20 TRC Read cycle (ID) 160 RDX (ID) TRDH Control pulse “H” duration (ID) 90 TRDL Control pulse “L” duration (ID) 45 TRCFM Read cycle (FM) 450 RDX (FM) TRDHFM Control pulse “H” duration (RAM) 90 TRDLFM Control pulse “L” duration (RAM) 355 TDST Data setup time 20 TDHT Data hold time 20 D[17:0] TRAT Read access time (ID) 40 TRATFM Read access time (FM) 340 TODH Output disable time 20 80 Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 ℃ V1.7 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description - -(3-transfer for one pixel) -(15Mhz) When read ID data When read from frame memory For maximum CL=30pF For minimum CL=8pF 2008.04.18 ST7787 Fig. 8.1.2 Rising and falling timing for input and output signal Fig.8.1.3 Chip selection (CSX) timing Fig. 8.1.4 Write-to-read and read-to-write timing NOTE: The rising time and falling time (Tr, Tf) of input signal and fall time are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. V1.7 31 2008.04.18 ST7787 8.2 Parallel interface characteristics: 18, 16, 9 or 8-bits bus (6800-series MCU interface) TCHW CSX TCHW TCS VIH TCSH TRCS/TRCSFM VIL TCSF D/CX VIH VIL TAHT TAST /WX VIH VIL TWC TWRL VIH E TWRH VIL VIH D[17:0] write TDST TDHT TRDH/TRDHFM TRDL/TRDLFM VIL VIH RX VIL VIH E VIL TRC/TRCFM TRAT/TRATFM D[17:0] read TODH VIH VIL Fig. 8.2.1 Parallel interface timing characteristics (6800-series MCU interface) Signal Symbol Parameter Min Max Unit Description TAST Address setup time 10 ns D/CX TAHT Address hold time (Write/Read) 10 ns TCHW Chip select “H” pulse width 0 ns TCS Chip select setup time (Write) 15 ns TRCS Chip select setup time (Read ID) 45 ns CSX TRCSFM Chip select setup time (Read FM) 355 ns TCSF Chip select wait time (Write/Read) 10 ns TCSH Chip select hold time 10 ns TWC Write cycle 66 ns WRX -(15Mhz) TWRH Control pulse “H” duration 20 ns TWRL Control pulse “L” duration 20 ns TRC Read cycle (ID) 160 ns RDX (ID) When read ID data TRDH Control pulse “H” duration (ID) 90 ns TRDL Control pulse “L” duration (ID) 45 ns TRCFM Read cycle (FM) 450 ns When read from frame RDX (FM) TRDHFM Control pulse “H” duration (FM) 90 ns memory TRDLFM Control pulse “L” duration (FM) 355 ns TDST Data setup time 20 ns TDHT Data hold time 20 ns For maximum CL=30pF D[17:0] TRAT Read access time (ID) 40 ns For minimum CL=8pF TRATFM Read access time (FM) 340 ns Output disable time 20 80 ns TODH Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70℃ Note 2: The rising time and falling time (Tr, Tf) of input signal and fall time are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. V1.7 32 2008.04.18 ST7787 8.3 Serial interface characteristics (3-line serial) CSX VIH TCHW VIL TSCYCW/TSCYCR TCSH TCSS TSLW/TSLR SCL TSHW/TSHR TSDS SDA TSCC VIH VIL TSDH VIH VIL TOH TACC VIH VIL VIH SDA (DOUT) VIL Fig. 8.3.1 3-line serial interface timing Signal CSX SCL SDA (DIN) (DOUT) Symbol TCSS TCSH TSCC TCHW TSCYCW TSHW TSLW TSCYCR TSHR TSLR TSDS TSDH TACC TOH Parameter Min Max Chip select setup time 60 Chip select hold time 60 Chip select setup time 20 Chip select setup time 40 Serial clock cycle (Write) 66 SCL “H” pulse width (Write) 20 SCL “L” pulse width (Write) 20 Serial clock cycle (Read) 150 SCL “H” pulse width (Read) 60 SCL “L” pulse width (Read) 60 Data setup time 10 Data hold time 10 Access time 10 Output disable time 15 Table 8.3: 3-line Serial Interface Characteristics Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description For maximum CL=30pF For minimum CL=8pF Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70℃ Note 2: The rising time and falling time (Tr, Tf) of input signal and fall time are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. 8.4 Vertical synchronizing signal timing characteristic Fig. 8.4 Vertical synchronizing signal timing Signal Symbol Parameter Min Max Unit tVCYC VSYNC Cycle 1F+2H VSYNC tVLW VSYNC Pulse L Width 1H 1F-1H tVHW VSYNC Pulse H Width 3H -Standing up standing fall time of the input signal(tr,tf) is provided for by 15ns or less. -The signal level is provided for based on 30% and 70% of VDDI-DGND -This is provided for while external VSYNC is synchronizing. -F indicates the time of one frame in internal synchronizition. -H indicates the time in internal synchronizition for one line. V1.7 33 Description 2008.04.18 ST7787 9. Function description 9.1 Interface type selection The selection of given interfaces are done by setting P68, IM2, IM1, and IM0 pins as shown in following table. P68 0 0 0 0 1 1 1 1 IM2 0 1 1 1 1 0 1 1 1 1 IM1 0 0 1 1 0 0 1 1 IM0 0 1 0 1 0 1 0 1 Interface 3-line serial interface 8080 8-bit parallel 8080 16-bit parallel 8080 9-bit parallel 8080 18-bit parallel 3-line serial interface 6800 8-bit parallel 6800 16-bit parallel 6800 9-bit parallel 6800 18-bit parallel Read back selection Via the read instruction RDX strobe (8-bit read data and 8-bit read parameter) RDX strobe (16-bit read data and 8-bit read parameter) RDX strobe (9-bit read data and 8-bit read parameter) RDX strobe (18-bit read data and 8-bit read parameter) Via the read instruction E strobe (8-bit read data and 8-bit read parameter) E strobe (16-bit read data and 8-bit read parameter) E strobe (9-bit read data and 8-bit read parameter) E strobe (18-bit read data and 8-bit read parameter) P68 0 IM2 0 1 IM1 0 IM0 0 Interface 3-line serial interface 8080 8-bit parallel RDX Note1 RDX WRX Note1 WRX D/CX SCL D/CX 0 1 0 1 8080 16-bit parallel RDX WRX D/CX 0 0 1 1 1 1 1 1 0 0 1 0 8080 9-bit parallel 8080 18-bit parallel 6800 8-bit parallel RDX RDX E WRX WRX WRX D/CX D/CX RS 1 1 0 1 6800 16-bit parallel E WRX RS 1 1 1 0 6800 9-bit parallel E WRX 1 1 1 1 6800 18-bit parallel E WRX Note 1. Unused pins can be open, or connected to DGND or VDDI. RS RS Read back selection D[17:1]: unused, D0: SDA D[17:8]: unused, D7-D0: 8-bit data D[17:16]: unused, D15-D0: 16-bit data D[17:9]: unused, D8-D0: 9-bit data D17-D0: 18-bit data D[17:8]: unused, D7-D0: 8-bit data D[17:16]: unused, D15-D0: 16-bit data D[17:9]: unused, D8-D0: 9-bit data D17-D0: 18-bit data 9.2 8080-series MCU parallel interface (P68=’0’) The MCU can use on of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-lines with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low) enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write, RDX is the parallel data read and D[17:0] is parallel data. The graphics controller chip reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=’1’, D[17:0] bits are either display data or command parameters. When D/C=’0’, D[17:0] bits are commands. The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is in low state (DGND). Interface bus width can be selected with IM2, IM1 and IM0. The interface functions of 8080-series parallel interface are given in following table. P68 RDX WRX D/CX Read back selection 0 1 ↑ Write 8-bit command (D7 to D0) 8-bit 1 1 ↑ Write 8-bit display data or 8-bit parameter (D7 to D0) 0 1 0 0 parallel 1 ↑ 1 Read 8-bit display data (D7 to D0) 1 ↑ 1 Read 8-bit parameter or status (D7 to D0) 0 1 ↑ Write 8-bit command (D7 to D0) 16-bit 1 1 ↑ Write 16-bit display data or 8-bit parameter (D15 to D0) 0 1 0 1 parallel 1 ↑ 1 Read 16-bit display data (D15 to D0) 1 ↑ 1 Read 8-bit parameter or status (D7 to D0) 0 1 ↑ Write 8-bit command (D7 to D0) 9-bit 1 1 ↑ Write 9-bit display data or 8-bit parameter (D8 to D0) 0 1 1 0 parallel 1 ↑ 1 Read 9-bit display data (D8 to D0) 1 ↑ 1 Read 8-bit parameter or status (D7 to D0) 0 1 ↑ Write 8-bit command (D7 to D0) 18-bit 1 1 ↑ Write 18-bit display data or 8-bit parameter (D17 to D0) 0 1 1 1 parallel 1 ↑ 1 Read 18-bit display data (D17 to D0) 1 ↑ 1 Read 8-bit parameter or status (D7 to D0) Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh V1.7 IM2 IM1 IM0 Interface 34 2008.04.18 ST7787 9.2.1 Write cycle sequence Fig. 9.2.1 8080-series WRX protocol Note: WRX is an unsynchronized signal (It can be stopped). Fig. 9.2.2 8080-series parallel bus protocol, write to register or display RAM V1.7 35 2008.04.18 ST7787 9.2.2 Read cycle sequence The read cycle (RDX high-low-high sequence) means that the host reads information from display via interface. The driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX. Fig. 9.2.3 8080-series RDX protocol Note: RDX is an unsynchronized signal (It can be stopped). Read parameter D[17:0] Read display data S CMD DM PA CMD DM & data Data Data P D[17:0] S CMD DM PA CMD DM & data Data Data P Host D[17:0] Host to LCD S CMD Driver D[17:0] LCD to Host S RESX “1” CSX D/CX RDX WRX Hi-Z Hi-Z DM CMD PA1 Hi-Z Hi-Z P DM & data PAN-2 PAN-1 P Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored. CMD: write command code PA: parameter or display data Fig. 9.2.4 8080-series parallel bus protocol, read data from register or display RAM V1.7 36 2008.04.18 ST7787 9.3 6800-Series Parallel Interface (P68=’1’) The MCU uses a 11-lines 8-data parallel interface or 12-lines 9-data parallel interface or 19-lines 16-data parallel interface or 21-lines 18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. The R/WX is the Read/Write flag and D[17:0] is parallel data. The Graphics Controller Chip reads the data at the falling edge of E signal when R/WX= ‘1’ and Writes the data at the falling of the E signal when R/WX=’0’. The D/CX is the data/command flag. When D/CX=’1’, D[17:0] bits are display RAM data or command parameters. When D/C= ‘0’, D[17:0] bits are commands. The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM1 and IM0. The interface functions of 6800-series parallel interface are given in Table 9.3.1. Table 9.3.1 The function of 6800-series parallel interface P68 IM2 IM1 IM0 Interface D/CX R/WX E Function 0 0 ↓ Write 8-bit command (D7 to D0) 1 0 ↓ Write 8-bit display data or 8-bit parameter (D7 to D0) 1 1 0 0 8-bit Parallel 1 1 ↓ Read 8-bit Display data (D7 to D0) 1 1 ↓ Read 8-bit parameter or status (D7 to D0) 0 0 ↓ Write 8-bit command (D7 to D0) 1 0 ↓ Write 16-bit display data or 8-bit parameter (D15 to D0) 1 1 0 1 16-bit Parallel 1 1 ↓ Read 16-bit Display data (D15 to D0) 1 1 ↓ Read 8-bit parameter or status (D7 to D0) 0 0 ↓ Write 8-bit command (D7 to D0) 1 0 ↓ Write 9-bit display data or 8-bit parameter (D8 to D0) 1 1 1 0 9-bit Parallel 1 1 ↓ Read 9-bit Display data (D8 to D0) 1 1 ↓ Read 8-bit parameter or status (D7 to D0) 0 0 ↓ Write 8-bit command (D7 to D0) 1 0 ↓ Write 18-bit display data or 8-bit parameter (D17 to D0) 1 1 1 1 18-bit Parallel 1 1 ↓ Read 18-bit Display data (D17 to D0) 1 1 ↓ Read 8-bit parameter or status (D7 to D0) Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh. 9.3.1 Write cycle sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’). Fig. 9.3.1 6800-Series Write Protocol Note: E is an unsynchronized signal (It can be stopped) V1.7 37 2008.04.18 ST7787 Fig. 9.3.2 6800-series parallel bus protocol, write to register or display RAM 9.3.2 Read cycle sequence The write cycle means that the host reads information (command or/and data) to the display via the interface. Each read cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’). Fig. 9.3.3 6800-series read protocol Note: E is an unsynchronized signal (It can be stopped) V1.7 34 2008.04.18 ST7787 Read parameter D[17:0] Read display data S CMD DM PA CMD DM & data Data Data P D[17:0] S CMD DM PA CMD DM & data Data Data P Host D[17:0] Host to LCD S CMD Driver D[17:0] LCD to Host S RESX “1” CSX D/CX R/WX E Hi-Z Hi-Z DM CMD PA1 Hi-Z Hi-Z P DM & data PAN-2 PAN-1 P Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored. CMD: write command code PA: parameter or display data Fig. 9.3.4 6800-series parallel bus protocol, read data form register or display RAM V1.7 35 2008.04.18 ST7787 9.4 Serial interface The selection of this interface is done by IM2. See the Table 9.4.1. Table 9.4.1 Serial Interface Type Selection P68 IM2 IM1 IM0 Interface ‘-’ 0 ‘-’ ‘-’ 3-line Serial interface Read back selection Via the read instruction (8-bit, 24-bit and 32-bit read parameter) The serial interface is a 3-lines/ 9-bits bi-directional interface for communication between the micro controller and the LCD driver chip. The 3-lines serial use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output) Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary. 9.4.1 Command Write Mode The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-lines serial data packet contains a control bit D/CX and a transmission byte is transfrerred by the D/CX pin. If D/CX is “low”, the transmission byte is interpreted as a command byte. If D/CX is “high”, the transmission byte is stored in the display data RAM (Memory write command), or command register as parameter. Any instruction can be sent in any order to the DRIVER. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission. 3-Line Serial Data Stream Format Transmission byte (TB) may be a Command or a Data LSB MSB D/CXD7 D6 D5 D4 D3 D2 D1 D0 TB TB TB D/CXD7 D6 D5 D4 D3 D2 D1 D0 D/CXD7 D6 D5 D4 D3 D2 D1 D0 D/CXD7 D6 D5 D4 D3 D2 D1 D0 Fig. 9.4.1 Serial interface data Stream format When CSX is “high”, SCL clock is ignored. During the high time of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low (see Fig 6.1.1.2). SDA is sampled at the rising edge of CSX. D/CX indicates, whether the byte is command code (D/CX=’0’) or parameter/RAM data (D/CX=’1’). It is sampled when first rising edge of SCL (3-lines serial interface) . If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-lines serial interface) at the next rising edge of SCL. Fig. 9.4.2 3-line serial interface write protocol (write to register with control bit in transmission) V1.7 36 2008.04.18 ST7787 9.4.2 Read Functions The read mode of the interface means that the micro controller reads register value from the Driver. To do the micro controller first has to send a command (Read ID or register command) and then the following byte is transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below figure). The Driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro controller is supported to read at the rising edge of SCL. After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL of the last bit. 3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read): 3-line serial protocol (for RDDID command: 24-bit read) 3-line Serial Protocol (for RDDST command: 32-bit read) Fig. 9.4.4 3-line serial interface read protocol V1.7 37 2008.04.18 ST7787 9.5 Data Transfer Break and Recovery If there is a break in data transmission by RESX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been High state. See the following example Host (MCU to driver) Fig. 9.5.1 Serial bus protocol, write mode – interrupted by RESX If there is a break in data transmission by CSX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example Host (MCU to driver) Fig. 9.5.2 Serial bus protocol, write mode – interrupted by CSX If 1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below. Fig.9.5.3 Write interrupts recovery (serial interface) If a 2 or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value. V1.7 38 2008.04.18 ST7787 Fig. 9.5.4 Write interrupts recovery (both serial and parallel Interface ) V1.7 39 2008.04.18 ST7787 9.6 Data transfer pause It will be possible when transferring a Command, Frame Memory Data or Multiple Parameter Data to invoke a pause in the data transmission. If the Chip Select Line is released after a whole byte of a Frame Memory Data or Multiple Parameter Data has been completed, then DRIVER will wait and continue the Frame Memory Data or Parameter Data Transmission from the point where it was paused. If the Chip Select Line is released after a whole byte of a command has been completed, then the Display Module will receive either the command‘s parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter 9.6.1 Serial interface pause Fig. 9.6.1 Serial interface pause protocol (pause by CSX) 9.6.2 Parallel interface pause Fig. 9.6.2 Parallel bus pause protocol (paused by CSX) V1.7 40 2008.04.18 ST7787 9.7 Data Transfer Modes The Module has three kinds Color modes for transferring data to the display RAM. These are 12-bit Color per pixel, 16-bit Color per pixel and 18-bit Color per pixel. The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods. 9.7.1 Method 1 The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer is reset to the start point and the next Frame is written. 9.7.2 Method 2 Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a new Frame is downloaded. Note: 1) These apply to all data transfer Color modes on both serial and parallel interfaces. 2) The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the frame memory. V1.7 41 2008.04.18 ST7787 9.8 Data Color Coding 9.8.1 8-bit Parallel Interface (IM2, IM1, IM0=”100”) Different display data formats are available for three Colors depth supported by listed below. - 4k Colors, RGB 4,4,4-bit input, - 65k Colors, RGB 5,6,5-bit input,. - 262k Colors, RGB 6,6,6-bit input, 9.8.1.1 8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=”03h” There are 2 pixels (6 sub-pixels) per 3-bytes. Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 12-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 42 2008.04.18 ST7787 9.8.1.2 8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=”05h” There are 1 pixel (3 sub-pixels) per 2-bytes. RESX IM[2:0] “1” “100” CSX D/CX WRX RDX R/WX “1” 8080-series control pins “0” E 6800-series control pins D7 0 R1, Bit 4 G1, Bit 2 R2, Bit 4 G2, Bit 2 D6 0 R1, Bit 3 G1, Bit 1 R2, Bit 3 G2, Bit 1 D5 1 R1, Bit 2 G1, Bit 0 R2, Bit 2 G2, Bit 0 D4 0 R1, Bit 1 B1, Bit 4 R2, Bit 1 B2, Bit 4 D3 1 R1, Bit 0 B1, Bit 3 R2, Bit 0 B2, Bit 3 D2 1 G1, Bit 5 B1, Bit 2 G2, Bit 5 B2, Bit 2 D1 0 G1, Bit 4 B1, Bit 1 G2, Bit 4 B2, Bit 1 D0 0 G1, Bit 3 B1, Bit 0 G2, Bit 3 B2, Bit 0 Pixel n Pixel n+1 16 bits 16 bits Look-up table for 65k color data mapping (16 bits to 18 bits) 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 43 2008.04.18 ST7787 9.8.1.3 8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=”06h” There are 1 pixel (3 sub-pixels) per 3-bytes. RESX IM[2:0] “1” “100” CSX D/CX WRX RDX R/WX “1” 8080-series control pins “0” E 6800-series control pins D7 0 R1, Bit 5 G1, Bit 5 B1, Bit 5 R2, Bit 5 D6 0 R1, Bit 4 G1, Bit 4 B1, Bit 4 R2, Bit 4 D5 1 R1, Bit 3 G1, Bit 3 B1, Bit 3 R2, Bit 3 D4 0 R1, Bit 2 G1, Bit 2 B1, Bit 2 R2, Bit 2 D3 1 R1, Bit 1 G1, Bit 1 B1, Bit 1 R2, Bit 1 D2 1 R1, Bit 0 G1, Bit 0 B1, Bit 0 R2, Bit 0 D1 0 - - - - D0 0 - - - - Pixel n Pixel n+1 18 bits 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 44 2008.04.18 ST7787 9.8.2 16-Bit Parallel Interface (IM2,IM1, IM0=”101”) Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input V1.7 45 2008.04.18 ST7787 9.8.2.1 16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=”03h” There are 1 pixel (3 sub-pixels) per 1 bytes, 12-bit/pixel. Note1. The data order is ad follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 46 2008.04.18 ST7787 9.8.2.2 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=”05h” There are 1 pixel (3 sub-pixels) per 1 bytes, 16-bit/pixel. Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 47 2008.04.18 ST7787 9.8.2.3 16-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=”06h” There are 2 pixel (6 sub-pixels) per 3 bytes, 18-bit/pixel. Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 48 2008.04.18 ST7787 9.8.3 9-Bit Parallel Interface (IM2, IM1, IM0=”110”) Different display data formats are available for three colors depth supported by listed below. - 262k colors, RGB 6,6,6-bit input 9.8.3.1 Write 9-bit data for RGB 6-6-6-bit input (262k-color) There are 1 pixel (6 sub-pixels) per 3 bytes, 18-bit/pixel. RESX IM[2:0] “1” “110” CSX D/CX WRX RDX R/WX “1” 8080-series control pins “0” E 6800-series control pins D8 - R1, Bit 5 G1, Bit 2 R2, Bit 5 G2, Bit 2 D7 0 R1, Bit 4 G1, Bit 1 R2, Bit 4 G2, Bit 1 D6 0 R1, Bit 3 G1, Bit 0 R2, Bit 3 G2, Bit 0 D5 1 R1, Bit 2 B1, Bit 5 R2, Bit 2 B2, Bit 5 D4 0 R1, Bit 1 B1, Bit 4 R2, Bit 1 B2, Bit 4 D3 1 R1, Bit 0 B1, Bit 3 R2, Bit 0 B2, Bit 3 D2 1 G1, Bit 5 B1, Bit 2 G2, Bit 5 B2, Bit 2 D1 0 G1, Bit 4 B1, Bit 1 G2, Bit 4 B2, Bit 1 D0 0 G1, Bit 3 B1, Bit 0 G2, Bit 3 B2, Bit 0 Pixel n Pixel n+1 18 bits 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 49 2008.04.18 ST7787 9.8.4 18-Bit Parallel Interface (IM2, IM1, IM0=”111”) Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input. V1.7 50 2008.04.18 ST7787 9.8.4.1 18-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=”03h” There are 1 pixel (3 sub-pixels) per 1 byte, 12-bit/pixel. RESX IM[2:0] “1” “111” CSX D/CX WRX RDX R/WX “1” 8080-series control pins “0” E 6800-series control pins D17 - - - - - D16 - - - - - D15 - - - - - D14 - - - - - D13 - - - - - D12 - - - - - D11 - R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 D10 - R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 D9 - R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 D8 - R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 D7 0 G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 D6 0 G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 D5 1 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 D4 0 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 D3 1 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 D2 1 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 D1 0 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 D0 0 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 12 bits 12 bits Look-Up Table for 4096 Color data mapping (12 bits to 18 bits) 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 51 2008.04.18 ST7787 9.8.4.2 18-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=”05h” There are 1 pixel (3 sub-pixels) per 1 byte, 16-bit/pixel. RESX IM[2:0] “1” “111” CSX D/CX WRX RDX R/WX “1” 8080-series control pins “0” E 6800-series control pins D17 - - - - - D16 - - - - - D15 - R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4 D14 - R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 D13 - R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 D12 - R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 D11 - R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 D10 - G1, Bit 5 G2, Bit 5 G3, Bit 5 G4, Bit 5 D9 - G1, Bit 4 G2, Bit 4 G3, Bit 4 G4, Bit 4 D8 - G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 D7 0 G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 D6 0 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 D5 1 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 D4 0 B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4 D3 1 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 D2 1 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 D1 0 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 D0 0 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 16 bits 16 bits Look-up table for 65k color data mapping (16 bits to 18 bits) 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 52 2008.04.18 ST7787 9.8.4.3 18-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=”06h” There are 1 pixel (3 sub-pixels) per 1 bytes, 18-bit/pixel. RESX IM[2:0] “1” “111” CSX D/CX WRX RDX R/WX “1” 8080-series control pins “0” E 6800-series control pins D17 - R1, Bit 5 R2, Bit 5 R3, Bit 5 R4, Bit 5 D16 - R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4 D15 - R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 D14 - R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 D13 - R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 D12 - R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 D11 - G1, Bit 5 G2, Bit 5 G3, Bit 5 G4, Bit 5 D10 - G1, Bit 4 G2, Bit 4 G3, Bit 4 G4, Bit 4 D9 - G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 D8 - G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 D7 0 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 D6 0 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 D5 1 B1, Bit 5 B2, Bit 5 B3, Bit 5 B4, Bit 5 D4 0 B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4 D3 1 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 D2 1 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 D1 0 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 D0 0 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 18 bits 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data. Note 2.1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. ‘-‘ = Don't care - Can be set to '0' or '1' V1.7 53 2008.04.18 ST7787 9.8.5 3-line serial Interface Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB 4-4-4-bit input 65k colors, RGB 5-6-5-bit input 262k colors, RGB 6-6-6-bit input 9.8.5.1 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=”03h” Note 1. pixel data with the 12-bit color depth information Note 2. The most significant bits are: Rx3, Gx3 and Bx3 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 Note 4. X = Don't care - Can be set to '0' or '1' V1.7 54 2008.04.18 ST7787 9.8.5.2 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=”05h” Note 1. pixel data with the 16-bit color depth information Note 2. The most significant bits are: Rx4, Gx5 and Bx4 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 Note 4. X = Don't care - Can be set to '0' or '1' 9.8.5.3 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=”06h” Note 1. pixel data with the 18-bit color depth information Note 2. The most significant bits are: Rx5, Gx5 and Bx5 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 Note 4. X = Don't care - Can be set to '0' or '1' V1.7 55 2008.04.18 ST7787 9.9 RGB interface 9.9.1 General Description The module uses 6, 16 and 18-bit parallel RGB interface which includes: VS, HS, DE, PCLK, D[17:0]. The interface is activated after Power On sequence (See section Power On/Off Sequence) Pixel clock (PCLK) is running all the time without stopping and it is used to entering VS, HS, DE and D[17:0] states when there is a rising edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g. Sleep In –mode etc. Vertical synchronization (VS) is used to tell when there is received a new frame of the display. This is negative (‘0’, low) active and its state is read to the display module by a rising edge of he PCLK signal. Horizontal synchronization (HS) is used to tell when there is received a new line of the frame. This is negative (‘0’, low) active and its state is read to the display module by a rising edge of the PCLK signal. Data Enable (DE) is used to tell when there is received a RGB information that should be transferred on the display. This is a positive (‘1’, high) active and its state is read to the display module by a rising edge of the PCLK signal. D[17:0] (18-bit: R5-R0, G5-G0 and B5-B0; 16-bit: R4-R0, G5-G0 and B4-B0) are used to tell what is the information of the image that is transferred on the display (When DE=’1’ and there is a rising edge of PCLK). D[17:0] can be ‘0’ (low) or ‘1’ (high). These lines are read by a rising edge of the PCLK signal. The PCLK cycle is described in the following figure. PCLK VS, HS, DE D[17:0] The host changes D[17:0], VS,HS and DE lines when there is a falling edge of the PCLK The driver read the D[17:0], VS,HS and DE lines when there is a rising edge of the PCLK Fig. 9.9.1 PCLK cycle Note: PCLK is an unsynchronized signal (It can be stopped). V1.7 56 2008.04.18 ST7787 9.9.2 General Timing Diagram Fig. 9.9.2 RGB general timing diagram The image information must be correct on the display, when the timings are in range on the interface. However, the image information can be incorrect on the display, when timings are not out of range on the interface (Out of the range timings cannot on the host side). The correct image information must be displayed automatically (by the display module) on the next frame (vertical sync.) when there is returned from out of the range to in range interface timing. V1.7 57 2008.04.18 ST7787 9.9.3 Updating Order on Display Active Area (Normal Display Mode On + Sleep Out) There is defined different kind of updating orders for display. These updating orders are controlled by H/W (SMX, SMY) and S/W (MX, MY, MV) bits. Vertical active counter (0 ~ 319) Vertical active counter (0 ~ 319) Fig. 9.9.3 Updating order when MADCTL’s MX=”0” and MY=”0” Fig. 9.9.4 Updating order when MADCTL’s MX=”1” and MY=”0” Vertical active counter (0 ~ 319) Vertical active counter (0 ~ 319) Fig. 9.9.5 Updating order when MADCTL’s MX=”0” and MY=”1” V1.7 Fig. 9.9.6 Updating order when MADCTL’s MX=”1” and MY=”1” 58 2008.04.18 ST7787 Table 9.9.1 Rules for Updating Order Horizontal Counter Return to 0 Increment by 1 Return to 0 Return to 0 Condition An active VS signal is received Signal Pixel information of the active area is received An active HS signal between two active area lines The Horizontal counter is larger than 239 and the Vertical counter is larger than 319 Note 1. Pixel order is RGB on the display. Note 2. Data streaming direction from the host to the display is described in the following figure. Vertical Counter Return to 0 No change Increment by 1 Return to 0 Fig. 9.9.3 Data streaming order for RGB interface 9.9.4 RGB Interface Bus Width set All 4-kinds of bus width can be available during RGB interface mode (selected by COLMOD (3Ah) command for 6-bit, 16-bit and 18-bit data width) VIPF[3:0] D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0101 R4 R3 R2 R1 R0 x G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 x 0110 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 VIPF[3:0] D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x x x x x x x x x R5 R4 R3 R2 R1 x x x x x x x x x x G5 G4 G3 G2 G1 x x x x x x x x x x B5 B4 B3 B2 B1 Note 1: When VIPF[3:0]=”1110”, 6-bit data width of 3-times transfer is used to transmit 1 pixel data with depth information. Note 2: Only VIPF[3:0]= ”0101” , “0110” and “1110” are valid on RGB I/F, Others are invalid. Note 3. ‘x’ Don’t care, but need to set VDDI or DGND level. 1110 9.9.5 RGB Interface Mode Set Table 9.9.5.1 RGB Interface Mode Set RGB I/F PCLK DE VS Mode RGB Mode 1 Used Used Used RGB Mode 2 Used Used Used HS Used Used Video Data bus D[17:0] Used Used Register for Blanking Porch setting Not Used Used R0 x x 6-bit G0 x x data B0 x x the 18-bit color Reference clock for Display Internal Oscillator Internal Oscillator There are 2-kinds of RGB mode which is selected by RCM1 & RCM0 hardware pins. In RGB Mode 1 (RCM1, RCM0 = “10”), writing data to frame memory is done by PCLK and Video Data Bus (D[17:0]), when DE is high state. The external synchronization signals (PCLK, VS and HS) are used for internal display signals. So, controller (host) must always transfer PCLK, VS, HS and DE signals to IC. In RGB Mode 2 (RCM1, RCM0 = “11”), blanking porch setting of VS and HS signals are defined by RGBBPCTR (B5h) command. DE pin is used for data making. When DE pin is high, valid data is directly stored to frame memory. In the contrast, if DE pin is low the data of frame memory will keep same status. V1.7 63 Bus width 16-bit data 18-bit data Bus width 2008.04.18 ST7787 Table 9.9.5.2 MCU & RGB Interface Comparisons table Function Mode selection 1 Mode selection 2 Motion /Still selection RCM1, RCM0 "0x" 8080/ 6800 IF + SPI I/F MCU Mode IMx= IMx="00" 8080/ 6800 IF SPI I/F Motion or Still Still picture picture RCM1, RCM0 "10" "11" RGB I/F + SPI I/Mode selection 1/F RGB Mode 1 RGB Mode 2 ICM='0' ICM='1' RGB-1 I/F + SPI I/F Motion or Still picture Still picture CSX VS, HS, DE CSX Refer PCLK Refer SCL Refer PCLK Refer SCL Refer PCLK Refer Internal Oscillator Refer PCLK Refer Internal Oscillator D0 D[17:0] D/CX = SCL PCLK Input signal CSX WRX (R/WX), RDX (E) SDA H/W pin enable D/CX = SCL CSX VS, HS, DE Refer SCL Refer Internal Oscillator GRAM Read Cycle Command setting SMX, SMY, SRGB TE Function Normal / Partial mode -By command setting -By command setting -By command setting -By command setting -By command setting -By Command setting -By command setting -Don’t care in this mode, but should be set to VDDI or DGND Data inverter setting (REV H/W pin) DE H/W pin RL H/W pin TB H/W pin Blanking porch Colors format D[17:0] D[7:0] D0 SDA SDA SDA SDA -If those register not change, those H/W pins are always valid. If those registers be changed, should be follow registers setting. -When Power On or H/W reset, those function follow H/W pins setting first. Idle Mode (IDM H/W pin) Display On/ Off (SHUT H/W pin) Still picture PCLK D[17:0] Refer the WRX cycle Refer Internal Oscillator Motion or Still picture SDA H/W pin enable D/CX = SCL Input data GRAM Write cycle ICM='0' ICM='1' RGB-2 I/F + SPI I/F -Don’t care in this mode, but should be set to VDDI or DGND -Don’t care in this mode -Control by IFPF[2:0] of COLMOD(3A) -The data latched by rising edge of PCLK when DE=’1’ -When display data coming the DE signal should be VDDI level -Don’t care in this mode, but should be set to VDDI or DGND -Control by DE signal -Control by VIPF[3:0] of COLMOD(3A) -By IDM H/W pin -IDM On/OFF (39h/28h) are disable -By SHUT H/W pin -SLPIN(10h), SLPOUT(11h), Display On/OFF (29h/28h) are disable -By REV H/W pin -INVON/OFF (21h/20h) are disable -When DE='0' area, the data of GRAM will keep the same status. -By H/W pin -No commands conflict -Control by RGBBPCTR (B5h) Note 1: RCM1 and RCM0 are H/W setting pins. Note 2: In RGB + SPI I/F (RCM="1x"), VS, HS, DE, PCLK and D[17:0] are Hi-Z by Driver and can be stop for Host, when ICM='1'. Note 3: In RGB + SPI I/F (RCM="1x"), the data deliver via GRAM Note 4: When Power on Driver IC should be detect SMX, SMY, SRGB H/W setting Note 5: When Power on Driver IC should be detect RCM1, RCM0 H/W setting and get into the I/F mode. Note 6: When Power on Driver IC should be detect LCM1, LCM0 H/W setting and get into the setting mode. V1.7 64 2008.04.18 ST7787 9.9.6 RGB Interface Timing Diagram 9.9.6.1 General Timings for RGB I/F Fig. 9.9.6 General timing of RGB interface Table 9.9.6.1 General Timing for RGB I/F Item Symbol Condition Min Specification Type. Max Pixel low pulse width TPCLKLT 12 Pixel high pulse width TPCLKHT 12 Vertical Sync. set-up time TVSST 15 Vertical Sync. hold time TVSSHT 15 Horizontal Sync. set-up time THSST 15 Horizontal Sync. hold time TVSSHT 15 Data Enable set-up time TDEST 15 Data Enable hold time TDEHT 15 Data set-up time TDST 15 Data hold time TDHT 15 Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 ℃ (to +85℃ no damage) Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Note 3. Data lines can be set to “High” or “Low” during blanking time – Don’t care. Note 4. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. Note 5. HP is multiples of eight PCLK. V1.7 65 Unit ns ns ns ns ns ns ns ns ns ns 2008.04.18 ST7787 VS n frame n+1 frame n+2 frame HS PCLK DE * DE ** don't care Data Frame data frame data DE * = RGB mode 1 DE ** = RGB mode 2 data transfer (ICM="1") frame data RAM write command (2Ch) address set command (2Ah, 2Bh) data transfer (ICM="1") Fig. 9.9.7 RAM access via SPI interface in RGB mode Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command. V1.7 66 2008.04.18 ST7787 9.9.6.2 RGB Interface Mode 1 Timing Diagram Fig. 9.9.8 RGB mode 1 timing diagram Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command. V1.7 67 2008.04.18 ST7787 Fig. 9.9.9 Vertical and horizontal timing of RGB interface V1.7 68 2008.04.18 ST7787 Table 9.9.6.2 Vertical and Horizontal Timing for RGB I/F Item Vertical Timing Vertical cycle period Vertical low pulse width Vertical front porch Vertical back porch Vertical data start line Vertical blanking period Vertical active area Vertical refresh rate Horizontal Timing Horizontal cycle period Horizontal low pulse width Horizontal front porch Horizontal back porch Horizontal data start point Symbol Min Specification Typ. Max TVS + TVBP TVS + TVBP + TVFP 326 2 2 2 4 6 330 4 4 4 8 10 Frame rate 61.75 Condition TVP TVS TVFP TVBP TVBL TVDISP TVRR THP THS THFP THBP THS + THBP ff HS + fHBP Horizontal blanking period Horizontal active area 272 2 2 2 30 1.0 32 320 65 68.25 512 256 256 256 256 THBL 256 THDISP 240 TPCLKCYC 33.3 174 Pixel clock cycle TVRR=65Hz fPCLKCYC 5.8 30.0 Note 1. VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage) Note 2. Data lines can be set to “High” or “Low” during blanking time – Don’t care. Note 3. HP is multiples of eight PCLK. V1.7 69 Unit HS HS HS HS HS HS HS Hz PCLK PCLK PCLK PCLK PCLK us PCLK PCLK ns MHz 2008.04.18 ST7787 9.9.6.3 RGB Interface Mode 2 Timing Diagram V back porch (TVS+TVBP) VS 1 frame (TVP) V front porch (TVFP) HS DE “1" HS 1 line (THP) H back porch (THS+THBP) Valid data (THDISP) H front porch (THFP) PCLK DE “1" Data bus Invalid Latch data Invalid D1 D2 D3 Invalid Dn D1 D2 D3 Dn Fig. 9.9.10 RGB mode 2 timing diagram Fig. 9.9.11 RGB mode 2 vertical timing diagram Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command. Horizontal timing for RGB I/F HS THS+THBP=10 PCLK D[17:0] THDISP=240 PCLK Invalid THFP=10 PCLK Invalid THP= 260 PCLK PCLK Fig. 9.9.12 RGB mode 2 V1.7 70 2008.04.18 ST7787 Fig. 9.9.13 RGB mode 2 idle mode timing diadram Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command. Fig. 9.9.14 Vertical and Horizontal in RGB interface V1.7 71 2008.04.18 ST7787 Table 9.9.6.3 Vertical and Horizontal Timing for RGB I/F Item Vertical Timing Vertical cycle period Vertical low pulse width Vertical front porch Vertical back porch Vertical data start line Vertical blanking period Vertical active area Vertical refresh rate Horizontal Timing Horizontal cycle period Horizontal low pulse width Horizontal front porch Horizontal back porch Symbol TVP TVS TVFP TVBP TVBL TVDISP TVRR Pixel clock cycle TVS + TVBP TVS + TVBP + TVFP Frame rate 61.75 THS + THBP ff HS + fHBP THBL THDISP TPCLKCYC fPCLKCYC Min 323 1 1 1 2 3 THP THS THFP THBP Horizontal data start point Horizontal blanking period Horizontal active area Condition TVRR=65Hz 243 1 1 1 1 0.196 3 33.3 5.1 Specification Type. Max 324 1 3 4 320 65 260 10 20 240 182 5.48 4 1023 1023 1023 1023 68.25 511 63 63 63 63 256 196 30 Unit HS HS HS HS HS HS HS Hz PCLK PCLK PCLK PCLK PCLK us PCLK PCLK ns MHz Note 1. VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage) Note 2. Data lines can be set to “High” or “Low” during blanking time – Don’t care. Note 3. HP is multiples of eight PCLK. V1.7 72 2008.04.18 ST7787 9.9.6.4 Power On Sequence on RGB Mode 2 The Driver operates power up and display ON by VDD, VDDI, SHUT, VS, HS, DE, PCLK on RGB mode 2 as show as following figure. VDD TVDD-VDDI VDDI VDD RESX SHUT PCLK TRS-SH TVDD-SH TPCLK-SH HS DE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VS Display high voltage TSH-LCD Display on TSH-ON Display Normal display Blanking display(over 1 frame) Source output Normal display Vcom output Normal display Gate output Internal counter Internal oscillator Fig. 9.9.15 Power-ON sequence in RGB mode 2 Table 9.9.6.4 Power ON AC Characteristics Characteristics Symbol Min VDD On to VDDI On TVDD-VDDI 0 VDDI/VDD on to falling edge of SHUT TVDD-SH 1 RESX to falling of SHUT TRS-SH 10 Signals input to falling edge of SHUT * TCLK-SH 1 Falling edge of SHUT to LCD power ON TSH-LCD Falling edge of SHUT to Display start TSH-ON Note 1: Signals mean VS, HS, DE and PCLK signal. Note 2: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command. V1.7 73 Typ Max 120 10 Unit ns ms us PCLK ms VS Remark Note1 2008.04.18 ST7787 9.9.6.5 Power OFF Sequence on RGB Mode 2 The Driver operates power off and display OFF by VDD, VDDI, SHUT, VS, HS and DE on RGB mode 2 as show as following figure. TVDD-VDDI RESX SHUT TOFF-VDD PCLK TSH-OFF HS DE VS Display high voltage Display on Display off Display Normal display Source output Normal display 0V Vcom output Normal display 0V Blanking display(over 1 frame) Gate output Internal counter Internal oscillator Fig. 9.9.16 Power-OFF seqnence in RGB mode 2 Table 9.9.6.5 Power OFF AC Characteristics Characteristics Symbol Min VDDI On to VDD On TVDD-VDDI 0 Signals input to VDDI/VDD off TSH-OFF 1 Rising edge of SHUT to Display off TSH-OFF 2 Note 1: Signals mean VS, HS, DE and PCLK signal. Note 2: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command. V1.7 74 Typ Max Unit ns us VS Remark Note1 2008.04.18 ST7787 9.9.7 RGB Data Color Coding 9.9.7.1 16-bit/pixel Color Order on the RGB Interface PCLK Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Green data and MSB=Bit4, LSB=Bit0 for Red and Blue data. Note 2. ‘-’ Don’t care, but need set to VDDI or DGND level. V1.7 75 2008.04.18 ST7787 9.9.7.2 18-bit/pixel Color Order on the RGB Interface PCLK Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data. Note 2. ‘-’ Don’t care, but need set to VDDI or DGND level. V1.7 76 2008.04.18 ST7787 9.9.7.3 6-bit/pixel Color Order on the RGB Interface RESX “1” “10”or “11” RCM[1:0] VS HS DE “1” “1” “1” WRX PCLK D17 - - - - - D16 - - - - - D9 - - - - - D8 - - - - - D7 R1, Bit 5 G1, Bit 5 B1, Bit 5 R2, Bit 5 G2, Bit 5 D6 R1, Bit 4 G1, Bit 4 B1, Bit 4 R2, Bit 4 G2, Bit 4 D5 R1, Bit 3 G1, Bit 3 B1, Bit 3 R2, Bit 3 G2, Bit 3 D4 R1, Bit 2 G1, Bit 2 B1, Bit 2 R2, Bit 2 G2, Bit 2 D3 R1, Bit 1 G1, Bit 1 B1, Bit 1 R2, Bit 1 G2, Bit 1 D2 R1, Bit 0 G1, Bit 0 B1, Bit 0 R2, Bit 0 G2, Bit 0 D1 - - - - - D0 - - - - Pixel n Pixel n+1 18 bits 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data. Note 2. ‘-’ Don’t care, but need set to VDDI or DGND level. V1.7 77 2008.04.18 ST7787 9.10 Display Data RAM 9.10.1 Configuration The display module has an integrated 240x320x18-bit graphic type static RAM. This 1382,400-bit memory allows to store on-chip a 240xRGBx320 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory. Fig. 9.10.1 Display data RAM organization V1.7 78 2008.04.18 ST7787 9.10.2 Memory to Display Address Mapping 9.10.2.1 When using 240RGB x 320 resolution (SMX=SMY=SRGB=’0’) 1 2 3 4 5 6 7 8 | | | | | 313 314 315 316 317 318 319 320 G0 B0 R1 G1 | | | | | | | | | | | | | | | | | | | | 0 239 S6 -------- S715 S716 S717 S718 S719 S720 1 238 RGB Order RGB=1 S5 RGB=0 S4 Pixel 240 RGB=1 RA MY=' 0 ' MY=' 1 ' 0 319 R0 1 318 2 317 3 316 4 315 5 314 6 313 7 312 | | | | | | | | | | | | | | | 312 7 313 6 314 5 315 4 316 3 317 2 318 1 319 0 MX=' 0 ' CA MX=' 1 ' S3 Pixel 239 -------- RGB=0 S2 RGB=0 S1 RGB=1 Source Out RGB=0 Gate Out Pixel 2 RGB=1 Pixel 1 SA ML=' 0 ' ML=' 1 ' B1 -------- R238 G238 B238 R239 G239 B239 0 319 -------1 318 -------2 317 -------3 316 -------4 315 -------5 314 -------6 313 -------7 312 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -------312 7 -------313 6 -------314 5 -------315 4 -------316 3 -------317 2 -------318 1 -------319 0 238 239 -------1 0 -------- Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command MV =Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command V1.7 79 2008.04.18 ST7787 9.10.3 Normal Display On or Partial Mode On, Vertical Scroll Off 9.10.3.4 When using 240RGB x 320 resolution In this mode, contents of the frame memory within an area where column pointer is 00h to EFh and page pointer is 00h to 13Fh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). 1). Example for Normal Display On (MX=MY=ML=’0’ ,SMX=SMY=’0’) 240 Columns Scan 240 Columns Order 00h 00 10 20 30 40 50 60 S0 U0 V0 W0 X0 Y0 Z0 01h 01 11 21 31 41 51 U1 V1 W1 X1 Y1 Z1 ---- ---- ---- ---- ---- EEh EFh 02 03 0W 0X 0Y 0Z 1 12 13 1W 1X 1Y 1Z 2 22 2X 2Y 2Z 3 32 3X 3Y 3Z | 42 4X 4Y 4Z | 5Y 5Z | 6Z | | | 240 x 320 x18 bit Fram e RAM | | SZ | UY UZ | V2 VX VY VZ | W2 WX WY WZ | X2 XX XY XZ 318 Y2 Y3 YW YX YY YZ 319 Z2 Z3 ZW ZX ZY ZZ 320 00 10 20 30 40 50 60 01 11 21 31 41 51 02 03 12 13 22 32 42 0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y 0Z 1Z 2Z 3Z 4Z 5Z 6Z 240 R G B x 320 LCD Panel S0 U0 V0 W0 X0 Y0 Z0 U1 V1 W1 X1 Y1 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 VX WX XX YW YX ZW ZX UY VY WY XY YY ZY SZ UZ VZ WZ XZ YZ ZZ G1 G2 G3 | | | | | | | | | | | | G318 G319 G320 Display area =320 lines 320 Lines 00h 01h 02h | | | | | | | | | | | | 13Dh 13Eh 13Fh 2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=13Bh, MX=MV=ML=’0’ ,SMX=SMY=’0’) 240 Columns Scan 240 Columns Order 320 Lines V1.7 00h 01h 02h | | | | | | | | | | | | 13Dh 13Eh 13Fh 00h 00 10 20 30 40 50 60 S0 U0 V0 W0 X0 Y0 Z0 01h 01 11 21 31 41 51 U1 V1 W1 X1 Y1 Z1 ---- ---- ---- ---- ---- EEh EFh 02 03 0W 0X 0Y 0Z 1 12 13 1W 1X 1Y 1Z 2 22 2X 2Y 2Z 3 32 3X 3Y 3Z | 42 4X 4Y 4Z | 5Y 5Z | 6Z | | | 240 x 320 x18 bit Fram e RAM | | SZ | UY UZ | V2 VX VY VZ | W2 WX WY WZ | X2 XX XY XZ 318 Y2 Y3 YW YX YY YZ 319 Z2 Z3 ZW ZX ZY ZZ 320 00 10 20 30 40 50 60 01 11 21 31 41 51 02 12 22 32 42 03 13 0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y 0Z 1Z 2Z 3Z 4Z 5Z 6Z 240 RGB x 320 LCD Panel S0 U0 V0 W0 X0 Y0 Z0 80 U1 V1 W1 X1 Y1 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 VX WX XX YW YX ZW ZX UY VY WY XY YY ZY SZ UZ VZ WZ XZ YZ ZZ G1 G2 G3 | | | | | | | | | | | | G318 G319 G320 Non-Display area =4 lines Display area =312 lines Non-Display area =4lines 2008.04.18 ST7787 9.10.4 Vertical Scroll Mode There is vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and Vertical Scrolling Start Address” (37h). Fig. 9.10.2 Difference between Scrolling and original V1.7 81 2008.04.18 ST7787 9.10.4.1 When using 240RGB x 320 resolution When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=320. In this case, scrolling is applied as shown below. 1). Example for TFA =3, VSA=315, BFA=2, SSA=4, ML=0: Scrolling Scan 240 Columns 240 Columns Order 320 Lines 00h 01h 02h | | | | | | | | | | | | 13Dh 13Eh 13Fh 00h 00 10 20 30 40 50 60 01h 01 11 21 31 41 51 ---- ---- ---- ---- ---- EEh EFh 02 03 0W 0X 0Y 0Z 12 13 1W 1X 1Y 1Z 22 2X 2Y 2Z 32 3X 3Y 3Z 42 4X 4Y 4Z 5Y 5Z 6Z 240 x 320 x18 bit Fram e RAM S0 U0 V0 W0 X0 Y0 Z0 U1 V1 W1 X1 Y1 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 VX WX XX YW YX ZW ZX UY VY WY XY YY ZY SZ UZ VZ WZ XZ YZ ZZ 1 2 3 | | | | | | | | | | | | 318 319 320 SSA 00 10 20 40 50 60 01 11 21 41 51 02 03 12 13 22 42 0W 0X 0Y 1W 1X 1Y 2X 2Y 4X 4Y 5Y 0Z 1Z 2Z 4Z 5Z 6Z 240 R G B x 320 LCD Panel S0 U0 V0 W0 X0 30 Y0 Z0 U1 V1 W1 X1 31 Y1 Z1 V2 W2 X2 32 Y 2 Y3 Z 2 Z3 VX WX XX 3X YW Y X ZW Z X UY VY WY XY 3Y YY ZY SZ UZ VZ WZ XZ 3Z YZ ZZ G1 G2 G3 | | | | | | | | | | | | G318 G319 G320 TFA VSA BFA 2). Example for TFA =3, VSA=315, BFA=2, SSA=4, ML=1: Scrolling: TFA and BFT are exchanged Scan 240 Columns 240 Columns Order 320 Lines V1.7 00h 01h 02h | | | | | | | | | | | | 13Dh 13Eh 13Fh 00h 00 10 20 30 40 50 60 S0 U0 V0 W0 X0 Y0 Z0 01h 01 11 21 31 41 51 U1 V1 W1 X1 Y1 Z1 ---- ---- ---- ---- ---- EEh EFh 02 03 0W 0X 0Y 0Z 320 12 13 1W 1X 1Y 1Z 319 22 2X 2Y 2Z 318 32 3X 3Y 3Z | 42 4X 4Y 4Z | 5Y 5Z | 6Z | | | 240 x 320 x18 bit Fram e RAM | | SZ | UY UZ | V2 VX VY VZ | W2 WX WY WZ | X2 XX XY XZ 3 Y2 Y3 YW YX YY YZ 2 Z2 Z3 ZW ZX ZY ZZ 1 00 10 W0 20 30 40 50 60 01 11 W1 21 31 41 51 02 03 12 13 W2 22 32 42 0W 0X 0Y 1W 1X 1Y WX WY 2X 2Y 3X 3Y 4X 4Y 5Y 240 R G B x 320 LCD Panel SSA 82 S0 U0 V0 X0 Y0 Z0 U1 V1 X1 Y1 Z1 V2 X2 Y2 Y3 Z2 Z3 VX XX YW YX ZW ZX UY VY XY YY ZY 0Z G1 1Z G2 W Z G3 2Z | 3Z | 4Z | 5Z | 6Z | | | | | SZ | UZ | VZ | XZ G318 YZ G319 ZZ G320 BFA VSA TFA 2008.04.18 ST7787 9.10.5 Vertical Scroll Example Case 1: TFA + VSA + BFA≠ ≠320 N/A. Do not set TFA + VSA + BFA≠320. In that case, unexpected picture will be shown. Case 2: TFA + VSA + BFA=320 (Scrolling) Example1) When MADCTL parameter ML=”0”, TFA=0, VSA=320, BFA=0 and VSCSAD=80. Example2) When MADCTL parameter ML=”1”, TFA=30, VSA=290, BFA=0 and VSCSAD=80. V1.7 83 2008.04.18 ST7787 9.11 Address Counter The address counter sets the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=239 (EFh) and Y=0 to Y=319 (13Fh). Addresses outside these ranges are not allowed. Before writing to the RAM a window must be defined into which will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=239 (EFh), YE=319 (13Fh). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET” and ”MADCTL” (see section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Section 9.12 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as section. 9.12 below: Condition When RAMWR/RAMRD command is accepted Complete Pixel Read / Write action The Column counter value is larger than “End Column (XE)” The Column counter value is larger than “End Column (XE)” and the Row counter value is larger than “End Row (YE)” Column Counter Row Counter Return to “Start Column (XS)” Increment by 1 Return to “Start Column (XS)” Return to “Start Column (XS)” Return to “Start Row (YS)” No change Increment by 1 Return to “Start Row (YS)” 9.12. Memory Data Write/ Read Direction The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below. Fig. 9.12.1 Data streaming order V1.7 84 2008.04.18 ST7787 9.12.1 When 240RGBx320 MADCTL (36h) Physical row point MV 0 0 0 0 1 1 1 1 MX 0 0 1 1 0 0 1 1 MY 0 1 0 1 0 1 0 1 CASET Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (239-Physical Column Pointer) Direct to (239-Physical Column Pointer) Direct to Physical Row Pointer Direct to (319-Physical Row Pointer) Direct to Physical Row Pointer Direct to (319-Physical Row Pointer) RASET Direct to Physical Row Pointer Direct to (319-Physical Row Pointer) Direct to Physical Row Pointer Direct to (319-Physical Row Pointer) Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (239-Physical Column Pointer) Direct to (239-Physical Column Pointer) Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7 (MY), B6 (MX), B5 (MV). The write order for each pixel unit is One pixel unit represents 1 column and 1page counter value on the Frame Memory. V1.7 85 2008.04.18 ST7787 9.12.2 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY) MADCTL Image in the Parameter Host Display Data Image in the Driver Direction Normal (DDRAM) MV MX MY 0 0 0 (MPU) B H/W position (0,0) B X-Y address (0,0) X: CASET F Y-Mirror 0 0 1 B Y: RASET F F H/W position (0,0) X-Y address (0,0) X: CASET F X-Mirror 0 1 0 B Y: RASET B B H/W position (0,0) X-Y address (0,0) X: CASET Y: RASET F X-Mirror 0 1 1 B F H/W position (0,0) F Y-Mirror X-Y address (0,0) X: CASET B F X-Y Exchange 1 0 0 B H/W position (0,0) Y: RASET B X-Y address (0,0) X: RASET F X-Y Exchange 1 0 1 B Y: CASET F F H/W position (0,0) Y-Mirror X-Y address (0,0) X: RASET F X-Y Exchange 1 1 0 B Y: CASET B B H/W position (0,0) X-Y address (0,0) X: RASET X-Mirror Y: CASET F X-Y Exchange 1 1 1 B H/W position (0,0) F B X-Mirror X-Y address (0,0) Y-Mirror X: RASET F V1.7 F 86 Y: CASET 2008.04.18 ST7787 9.13 Tearing Effect Output Line The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. 9.13.1 Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only: tvdh= The LCD display is not updated from the Frame Memory tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see below) Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 320 H-sync pulses per field. thdh= The LCD display is not updated from the Frame Memory thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above) Note: During Sleep In Mode, the Tearing Output Pin is active Low. V1.7 87 2008.04.18 ST7787 9.13.2 Tearing Effect Line Timings The Tearing Effect signal is described below: Table 9.13.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 58.9 Hz) Symbol Parameter min max unit tvdl Vertical Timing Low Duration 13 tvdh Vertical Timing High Duration 1000 thdl Horizontal Timing Low Duration 33 thdh Horizontal Timing Low Duration 25 NOTE: The timings in Table 9.3.1 apply when MADCTL ML=0 and ML=1 500 description ms µs µs µs The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect: V1.7 88 2008.04.18 ST7787 9.13.3 Example 1: MPU Write is faster than panel read. MCU to memory 1st 320nd time TE output signal time Memory to LCD 1st 320nd time Image on LCD Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image: B V1.7 89 2008.04.18 ST7787 9.13.4 Example 2: MPU write is slower than panel read. The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position. B V1.7 90 2008.04.18 ST7787 9.14 Preset Values ST7787 will set preset values on our production line for each display module. Any of these preset values do not need customer’s SW support. 9.15 Power ON/OFF Sequence The power on/off sequence is illustrated below: 9.15.1 Uncontrolled Power Off The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. 2. At an uncontrolled power off the display will go blank and there will not be any visible effects within (TBD) second on the display (blank display) and remains blank until “Power On Sequence” powers it up. V1.7 91 2008.04.18 ST7787 9.16 Power Level Definition 9.16.1 Power Level 6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 262,144 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out. In this mode part of the display is used with maximum 262,144 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out. In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode In this mode, the DC: DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe. 6. Power Off Mode In this mode, both VDD and VDDI are removed. Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed. V1.7 92 2008.04.18 ST7787 9.16.2 Power Flow Chart Normal display mode on = NOR ON Partial display mode on = PTL ON Idle mode off = IDM OFF Idle mode on = IDM ON Sleep out = SLP OUT Sleep in = SLP IN NOR ON PTL ON Sleep out Normal display mode on Idle mode off IDM ON Power on sequence HW reset SW reset SLP IN SLP OUT Sleep in Normal display mode on Idle mode off Sleep out Normal display mode on Idle mode on Sleep out Partial display mode on Idle mode off PTL ON NOR ON PTL ON IDM OFF IDM ON IDM ON NOR ON SLP IN SLP OUT SLP IN SLP OUT IDM OFF Sleep out Partial display mode on Idle mode on Sleep in Normal display mode on Idle mode on Sleep in Partial display mode on Idle mode off IDM ON SLP IN SLP OUT IDM OFF IDM OFF Sleep in Partial display mode on Idle mode on PTL ON NOR ON Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode. Note 2: There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power mode. V1.7 93 2008.04.18 ST7787 9.17 Reset 9.17.1 Reset Table (240RGB x320) Item After Power On After Hardware Reset After Software Reset Random In Off Normal Off On Off Off 0000h No Change In Off Normal Off On Off Off 0000h Column: End Address (XE) 00Efh 00EFh Row: Start Address (YS) 0000h 0000h Row: End Address (YE) 013Fh 013Fh GC0 See Section 9.19 0000h 013Fh Off 0000h 0140h 0000h 0000h Off 0 (Mode1) GC0 See Section 9.19 0000h 013Fh Off 0000h 0140h 0000h 0000h Off 0 (Mode1) No Change In Off Normal Off On Off Off 0000h 00EFh (239d) (when MV=0) 013Fh (319d) (when MV=1) 0000h 013Fh (319d) (when MV=0) 00EFh (239d) (when MV=1) GC0 No Change 0000h 013Fh Off 0000h 0140h 0000h 0000h Off 0 (Mode1) Memory Data Access Control (MY/MX/MV/ML/RGB) 0/0/0/0/0 0/0/0/0/0 No Change Interface Pixel Color Format RDDPM RDDMADCTL RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h NV value NV value 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h NV value NV value No Change 08h No Change No Change 00h 00h 00h 38h NV value NV value Frame memory Sleep In/Out Display On/Off Display mode (normal/partial) Display Inversion On/Off VSYNCIN VSYNCOUT Display Idle Mode On/Off Column: Start Address (XS) Gamma setting RGB for 4k and 65k Color Mode Partial: Start Address (PSL) Partial: End Address (PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area (TFA) Scroll: Scroll Area (VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address (SSA) Tearing: On/Off Tearing Effect Mode *3) Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied. Notes:2. Powered-On Reset finishes within 10µs after both VDD & VDDI are applied. Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. V1.7 94 2008.04.18 ST7787 9.17.2 Module Input/Output Pins 9.17.2.1 Output or Bi-directional (I/O) Pins Output or Bi-directional pins TE D7 to D0 (Output driver) After Power On Low High-Z (Inactive) After Hardware Reset Low High-Z (Inactive) After Software Reset Low High-Z (Inactive) Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset. 9.17.2.2 Input Pins Input pins RESX CSX D/CX WRX RDX D7 to D0 P/SX V1.7 During Power On Process See 9.15 Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid After Power On Input valid Input valid Input valid Input valid Input valid Input valid Input valid After Hardware Reset Input valid Input valid Input valid Input valid Input valid Input valid Input valid 95 After Software Reset Input valid Input valid Input valid Input valid Input valid Input valid Input valid During Power Off Process See 9.15 Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid 2008.04.18 ST7787 9.17.3 Reset Timing Table 9.18.3.1 Reset input timing VSS=0V, VDDI=1.65V to 1.95V, VDD=2.45V to 2.9V,Ta = -30 to 70℃) Symbol Parameter Related Pins MIN TYP tRESW *1) Reset low pulse width RESX 30 tREST *2) Reset complete time - 120 - MAX - Note - Unit us - ms Note 1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below. Note 2. During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode) and then return to Default condition for H/W reset. Note 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 120ms after a rising edge of RESX. Note 4. Spike Rejection also applies during a valid reset pulse as shown below: V1.7 96 2008.04.18 ST7787 9.18 Color Depth Conversion Look Up Tables 9.18.1 4096 and 65536 Color to 262,144 Color Look Up Table Outputs Color Frame Memory Data (6-bit) RED V1.7 R005 R004 R003 R002 R001 R000 R015 R014 R013 R012 R011 R010 R025 R024 R023 R022 R021 R020 R035 R034 R033 R032 R031 R030 R045 R044 R043 R042 R041 R040 R055 R054 R053 R052 R051 R050 R065 R064 R063 R062 R061 R060 R075 R074 R073 R072 R071 R070 R085 R084 R083 R082 R081 R080 R095 R094 R093 R092 R091 R090 R105 R104 R103 R102 R101 R100 R115 R114 R113 R112 R111 R110 R125 R124 R123 R122 R121 R120 R135 R134 R133 R132 R131 R130 R145 R144 R143 R142 R141 R140 R155 R154 R153 R152 R151 R150 R165 R164 R163 R162 R161 R160 R175 R174 R173 R172 R171 R170 R185 R184 R183 R182 R181 R180 R195 R194 R193 R192 R191 R190 R205 R204 R203 R202 R201 R200 R215 R214 R213 R212 R211 R210 R225 R224 R223 R222 R221 R220 R235 R234 R233 R232 R231 R230 R245 R244 R243 R242 R241 R240 R255 R254 R253 R252 R251 R250 R265 R264 R263 R262 R261 R260 R275 R274 R273 R272 R271 R270 R285 R284 R283 R282 R281 R280 R295 R294 R293 R292 R291 R290 R305 R304 R303 R302 R301 R300 R315 R314 R313 R312 R311 R310 Default value after H/W Reset RGBSET Parameter 000000 000011 000101 000111 001001 001011 001101 001111 010001 010011 010101 010111 011001 011011 011101 011111 100001 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 97 Look Up Table Input Data 4k Color 65k Color 0000 00000 0001 00001 0010 00010 0011 00011 0100 00100 0101 00101 0110 00110 0111 00111 1000 01000 1001 01001 1010 01010 1011 01011 1100 01100 1101 01101 1110 01110 1111 01111 10000 10001 10010 10011 10100 10101 10110 10111 Not Used 11000 11001 11010 11011 11100 11101 11110 11111 2008.04.18 ST7787 Color Look Up Table Outputs Frame Memory Data (6-bit) Default value after H/W Reset RGBSET Parameter GREEN G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 G165 G164 G163 G162 G161 G160 G175 G174 G173 G172 G171 G170 G185 G184 G183 G182 G181 G180 G195 G194 G193 G192 G191 G190 G205 G204 G203 G202 G201 G200 G215 G214 G213 G212 G211 G210 G225 G224 G223 G222 G221 G220 G235 G234 G233 G232 G231 G230 G245 G244 G243 G242 G241 G240 G255 G254 G253 G252 G251 G250 G265 G264 G263 G262 G261 G260 G275 G 274 G273 G272 G271 G270 G285 G 284 G283 G282 G281 G280 G295 G 294 G293 G292 G291 G290 G305 G 304 G303 G302 G301 G300 G315 G 314 G313 G312 G311 G310 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 V1.7 98 Look Up Table Input Data 4k Color 65k Color 0000 000000 0001 000001 0010 000010 0011 000011 0100 000100 0101 000101 0110 000110 0111 000111 1000 001000 1001 001001 1010 001010 1011 001011 1100 001100 1101 001101 1110 001110 1111 001111 010000 010001 010010 010011 010100 010101 010110 010111 Not Used 011000 011001 011010 011011 011100 011101 011110 011111 2008.04.18 ST7787 Color Look Up Table Outputs Frame Memory Data (6-bit) Default value after H/W Reset RGBSET parameter GREEN G325 G324 G323 G322 G321 G320 G335 G334 G333 G332 G331 G330 G345 G344 G343 G342 G341 G340 G355 G354 G353 G352 G351 G350 G365 G364 G363 G362 G361 G360 G375 G374 G373 G372 G371 G370 G385 G384 G383 G382 G381 G380 G395 G394 G393 G392 G391 G390 G405 G404 G403 G402 G401 G400 G415 G414 G413 G412 G411 G410 G425 G424 G423 G422 G421 G420 G435 G434 G433 G432 G431 G430 G445 G444 G443 G442 G441 G440 G455 G454 G453 G452 G451 G450 G465 G464 G463 G462 G461 G460 G475 G474 G473 G472 G471 G470 G485 G484 G483 G482 G481 G480 G495 G494 G493 G492 G491 G490 G505 G504 G503 G502 G501 G500 G515 G514 G513 G512 G511 G510 G525 G524 G523 G522 G521 G520 G535 G534 G533 G532 G531 G530 G545 G544 G543 G542 G541 G540 G555 G554 G553 G552 G551 G550 G565 G564 G563 G562 G561 G560 G575 G574 G573 G572 G571 G570 G585 G584 G583 G582 G581 G580 G595 G594 G593 G592 G591 G590 G605 G604 G603 G602 G601 G600 G615 G614 G613 G612 G611 G610 G625 G624 G623 G622 G621 G620 G635 G634 G633 G632 G631 G630 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 V1.7 99 Look Up Table Input Data 4k Color 65k Color 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Not Used 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 2008.04.18 ST7787 Color BLUE V1.7 Look Up Table Outputs Frame Memory Data (6-bit) Default value after H/W Reset RGBSET parameter B005 B004 B003 B002 B001 B000 B015 B014 B013 B012 B011 B010 B025 B024 B023 B022 B021 B020 B035 B034 B033 B032 B031 B030 B045 B044 B043 B042 B041 B040 B055 B054 B053 B052 B051 B050 B065 B064 B063 B062 B061 B060 B075 B074 B073 B072 B071 B070 B085 B084 B083 B082 B081 B080 B095 B094 B093 B092 B091 B090 B105 B104 B103 B102 B101 B100 B115 B114 B113 B112 B111 B110 B125 B124 B123 B122 B121 B120 B135 B134 B133 B132 B131 B130 B145 B144 B143 B142 B141 B140 B155 B154 B153 B152 B151 B150 B165 B164 B163 B162 B161 B160 B175 B174 B173 B172 B171 B170 B185 B184 B183 B182 B181 B180 B195 B194 B193 B192 B191 B190 B205 B204 B203 B202 B201 B200 B215 B214 B213 B212 B211 B210 B225 B224 B223 B222 B221 B220 B235 B234 B233 B232 B231 B230 B245 B244 B243 B242 B241 B240 B255 B254 B253 B252 B251 B250 B265 B264 B263 B262 B261 B260 B275 B274 B273 B272 B271 B270 B285 B284 B283 B282 B281 B280 B295 B294 B293 B292 B291 B290 B305 B304 B303 B302 B301 B300 B315 B314 B313 B312 B311 B310 000000 000011 000101 000111 001001 001011 001101 001111 010001 010011 010101 010111 011001 011011 011101 011111 100001 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 100 Look Up Table Input Data 4k Color 65k Color 0000 00000 0001 00001 0010 00010 0011 00011 0100 00100 0101 00101 0110 00110 0111 00111 1000 01000 1001 01001 1010 01010 1011 01011 1100 01100 1101 01101 1110 01110 1111 01111 10000 10001 10010 10011 10100 10101 10110 10111 Not Used 11000 11001 11010 11011 11100 11101 11110 11111 2008.04.18 ST7787 9.19 Sleep Out-Command and Self-Diagnostic Functions of the Display Module 9.19.1 Register Loading Detection Sleep Out-command (See section 10.1.12 “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from E-memory (similar device) to registers of the display controller is working properly. There are compared factory values of the E-memory and register values of the display controller by the display controller. If those both values (E-memory and register values) are same, there is inverted (=increased by 1) a bit, which is defined in command 10.1.10 “Read Display Self-Diagnostic Result (0Fh) ” (=RDDSDR) (The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= increased by 1). The flow chart for this internal function is following: Power on sequence HW reset SW reset Sleep In (10h) Sleep Out Mode Sleep In Mode RDDSDR’s D7=0 Sleep Out (11h) Loads values from E-memory to registers No Compares E-memory and register values Are E-memory and register values same ? Yes D7 inverted Note: There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh), by the display module. V1.7 101 2008.04.18 ST7787 9.20 External Light Source The operation of the module can meet customer’s Environmental reliability requirements. 9.21 Oscillator The chip has on-chip oscillator that does not require external components. This oscillator output signal is used for system clock generation for internal display operation. 9.22 System Clock Generator The timing generator produces the various signals to driver the internal circuitty. Internal chip operation is not affected by operations on the data bus. 9.23 Instruction Decoder and Register The instruction decoder indentifies command words arriving at the interface and routes the following data bytes to their destination. The command set can be found in “ Command” section. 9.24 Source Driver The source driver block includes 240x3 source outputs (S1 to S720), which should be connected directly to the TFT-LCD. The source output signals are generated in the data processing block after the data is read out of the RAM and latched, which represent the simulatance selected rows. 9.25 Gate Driver The gate driver block include 320 chanel gate output (G1 to G320) which should be connected directly to the TFT-LCD. 9.25.1 Gate Driver 9.25.1.1 Normal mode S1-S396 1 2 3 4 5 6 7 8 9 10 11 12 G1 G2 G3 G4 G5 G6 G7 VGH G8 VGL G9 G10 G11 G12 Fig. 9.25.1 Gate Driver Output Option 1 V1.7 102 2008.04.18 ST7787 10. Command 10.1 System function Command List and Description Table 10.1.1 System Function command List (1) Instruction Refer D/CX WRXRDX D17-8 NOP 10.1.1 SWRESET 10.1.2 RDDID RDDST RDDPM 10.1.3 10.1.4 10.1.5 RDD 10.1.6 MADCTL RDD 10.1.7 COLMOD RDDIM 10.1.8 RDDSM 10.1.9 RDDSDR 10.1.10 0 0 0 1 1 1 1 0 1 1 1 -↑ ↑ ↑ 1 1 1 1 0 1 1 0 1 1 D6 D5 D3 0 0 0 --ID14 ID24 ID34 0 --MV IFPF0 0 0 0 --ID13 ID23 ID33 1 --ML IDMON 0 0 0 --ID17 ID27 ID37 0 --BSTON ST23 ↑ - VSSON ST14 INVON ST12 GCS1 GCS0 TELOM HSON ↑ 1 - 1 1 -↑ 1 1 ↑ ↑ 1 ↑ ↑ - 0 -↑ 1 - 1 1 1 1 ↑ ↑ - 0 -↑ 1 - 1 1 1 1 ↑ ↑ - 0 -↑ 1 - 1 1 1 1 ↑ ↑ - 0 -↑ 1 - 1 1 ↑ - 1 1 ↑ - 1 ↑ ↑ ↑ ↑ 0 0 0 0 0 0 ----ID16 ID15 ID26 ID25 ID36 ID35 0 0 ----MY MX IFPF2 IFPF1 D4 - 1 1 1 1 -↑ 1 1 1 1 1 1 ↑ ↑ ↑ ↑ D7 D2 D1 D0 (Hex) Function 0 0 0 (00h) No Operation 0 0 1 (01h) Software reset (04h) Read Display ID 1 0 0 ------Dummy read ID12 ID11 ID10 ID1 read ID22 ID21 ID20 ID2 read ID32 ID31 ID30 ID3 read 0 0 1 (09h) Read Display Status ------Dummy read RGB MH ST24 PTLON SLOUTNORON - Read Display Power 0 0 0 0 1 0 1 0 (0Ah) Mode ----------------Dummy read BSTON IDMON PTLON SLPOUT NORON DISON D1 D0 0 0 0 0 1 0 1 1 (0Bh Read Display MADCTL ----------------Dummy read MX MY MV ML RGB MH D1 D0 00h Read Display Pixel 0 0 0 0 1 1 0 0 (0Ch) Format ----------------Dummy read VIPF3 VIPF2 VIPF1 VIPF0 D3 IFPF2 IFPF1 IFPF0 Read Display Image 0 0 0 0 1 1 0 1 (0Dh) Mode ----------------Dummy read VSSON D6 INVON D4 D3 GCS2 GCS1 GCS0 Read Display Signal 0 0 0 0 1 1 1 0 (0Eh) Mode ----------------Dummy read TEON TELOM HSON VSON PCKON DEON D1 D0 00h Read Display 0 0 0 0 1 1 1 1 (0Fh) Self-diagnostic result --- --- --- RELD FUND ATTD ST11 DISON TEON GCS2 VSON PCKON DEON ST0 --- --- --- --- --- Dummy read BRD D3 D2 D1 D0 - “-“: Don’t care Ver. 1.7 103 2008.04.18 ST7787 Table 10.1.2 System Function command List (2) Instruction Refer D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 (Hex) Function 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 (10h) (11h) (12h) (13h) Sleep in & booster off Sleep out & booster on Partial mode on Partial mode off Normal mode 0 0 0 GC4 0 0 0 --XS4 --XE4 0 --YS4 --YE4 0 0 0 0 GC3 1 1 1 --XS3 --XE3 1 --YS3 --YE3 1 SLPIN SLPOUT PTLON NORON 10.1.11 10.1.12 10.1.13 10.1.14 0 0 0 0 ↑ ↑ ↑ ↑ 1 1 1 1 - 0 0 0 0 INVOFF INVON 10.1.15 10.1.16 GAMSET 10.1.17 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ -↑ ↑ ↑ -↑ ↑ -↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -↑ -↑ - 0 0 0 GC7 0 0 0 --XS7 --XE7 0 --YS7 --YE7 0 DISPOFF 10.1.18 DISPON 10.1.19 CASET 10.1.20 RASET 10.1.21 RAMWR 10.1.22 RAMRD 10.1.23 0 1 0 1 0 1 GC6 GC5 0 1 0 1 0 1 ----XS6 XS5 ----XE6 XE5 0 1 ----YS6 YS5 ----YE6 YE5 0 1 0 0 0 (20h) Display inversion off Normal 0 0 1 (21h) Display inversion on 1 1 0 (26h) Gamma curve select GC2 GC1 GC0 0 0 0 (28h) Display off 0 0 1 (29h) Display on 0 1 0 (2Ah) Column address set ----XS8 Xaddress start: 0≦XS≦EF XS2 XS1 XS0 00h MV=0 ----XE8 Xaddress end: XS≦XE≦EF XE2 XE1 XE0 AFh MV=0 0 1 1 (2Bh) Row address set ----YS8 Xaddress start: 0≦YS≦13F YS2 YS1 YS0 00h MV=0 ----YE8 Xaddress end: YS≦YE≦13F YE2 YE1 YE0 DBh MV=0 1 0 0 (2Ch) Memory write Write data * Bit asignment varies with the selected interface Write data 0 0 1 0 1 1 1 0 (2Eh) Memory read ----------------Dummy read Read data * Bit asignment varies with the selected interface Read data “-“: Don’t care Ver. 1.7 104 2008.04.18 ST7787 Table 10.1.3 System Function command List (3) Instruction Refer D/CXWRXRDX D17-8 D7 D6 D5 D4 D3 D2 1 1 - 1 1 1 0 1 1 1 1 1 1 0 0 1 0 1 0 1 1 0 0 0 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 0 --PSL7 --PEL7 0 --TFA7 --VSA7 --BFA7 0 0 --0 MY 0 --SSA7 0 0 0 0 --PSL6 --PEL6 0 --TFA6 --VSA6 --BFA6 0 0 --0 MX 0 --SSA6 0 0 0 1 --PSL5 --PEL5 1 --TFA5 --VSA5 --BFA5 1 1 --1 MV 1 --SSA5 1 1 1 1 --PSL4 --PEL4 1 --TFA4 --VSA4 --BFA4 1 1 --1 ML 1 --SSA4 1 1 1 0 --PSL3 --PEL3 0 --TFA3 --VSA3 --BFA3 0 0 --0 RGB 0 --SSA3 1 1 1 0 --PSL2 --PEL2 0 --TFA2 --VSA2 --BFA2 1 1 --1 MH 1 --SSA2 0 0 0 1 ↑ 1 - VIPF3 VIPF2 VIPF1 VIPF0 0 ↑ 1 - 0 0 1 1 1 1 1 1 (3Fh) 1 ↑ 1 - 1 1 0 0 1 0 1 0 CAh 1 ↑ 1 - 0 0 0 0 0 0 INI 0 0 ↑ 1 - 1 1 0 1 1 0 1 0 10.1.35 1 1 ↑ - --- --- --- --- --- --- --- --- RDID2 10.1.36 1 0 1 1 0 1 ↑ 1 1 ↑ ↑ 1 ↑ ↑ 1 - ID17 1 --ID27 1 ID16 1 --ID26 1 ID15 0 --ID25 0 ID14 1 --ID24 1 ID13 1 --ID23 1 RDID3 10.1.37 1 1 ↑ - --- --- --- --- --- 1 1 ↑ - ID37 ID36 ID35 ID34 ID33 0 1 PTLAR SCRLAR 10.1.25 10.1.26 TEOFF 10.1.27 TEON 10.1.28 MADCTL 10.1.29 VSCSAD 10.1.30 IDMOFF IDMON 10.1.31 10.1.32 COLMOD 10.1.33 OTP_process 10.1.34 RDID1 --- D1 D0 0 0 --- PSL8 PSL1 PSL0 --- PEL8 PEL1 PEL0 1 1 --- TFA8 TFA1 TFA0 --- VSA8 VSA1 VSA0 --- BFA8 BFA1 BFA0 0 0 0 1 --M 1 0 ----1 1 --- SSA8 SSA1 SSA0 0 0 0 1 1 0 (Hex) Function (30h) Partial start/end address set 00h Partial start address 0,1,2,….,219 00h 00h Partial end address 0,1,2,….,219 F0h (33h) Scroll area set Top fixed area 0,1,2,….,219 Vertical scroll area 0,1,2,….,219 Bottom fixed area 0,1,2,….,219 (34h) Tearing effect line off (35h) Tearing effect mode set & on M="0": Mode 1, M="1": Mode 2 (36h) Memory data access control soft rst (37h) Scroll start address of RAM SSA=0,1,2,….,319 00h (38h) Idle mode off (39h) Idle mode on (3Ah) Interface pixel format IFPF2 IFPF1IFPF0 soft rst OTP-Process (DAh) Read ID1 Dummy read ID12 ID11 ID10 Read parameter 0 1 1 (DBh) Read ID2 ------Dummy read ID22 ID21 ID20 Read parameter 1 0 0 (DCh) Read ID3 --- --- --- Dummy read Read parameter “-“: Don’t care Note 1. After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer “RESET TABLE” section) Note 2. Undefined commands are treated as NOP (00 h) command. Note 3. B0 to D9 and DE to FF are for factory use of driver supplier. Note 4. Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh and Read Display Self Diagnostic Result (0Fh) of these commands are updated immediately both in Sleep In mode and Sleep Out mode. Ver. 1.7 105 ID32 ID31 ID30 2008.04.18 ST7787 10.2 Panel Function Command List and Description Table 10.2.1 Panel Function Command List (2) Instruction Refer D/CX WRX RDX D23-8 D7 RGBCTR D6 D5 D4 D3 D2 D1 D0 0 ↑ 1 - 1 0 1 1 0 0 0 0 1 ↑ 1 - --0 --0 --0 ICM 0 DP 0 EP 0 HSP 0 VSP 0 0 ↑ 1 - 1 0 1 1 0 0 0 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 0 ↑ 1 1 ↑ 1 - --- RTNA[6] RTNA[5] 0 0 1 ------0 0 0 ------0 0 0 1 0 1 --- RTNB[6] RTNB[5] 10.2.1 FRMCTR1 10.2.2 FRMCTR2 10.2.3 0 0 1 - --0 --0 --0 --0 --0 --0 1 0 1 0 0 - 1 0 1 - --- RTNC[6] RTNC[5] RTNC[4] RTNC[3] RTNC[2] RTNC[1] RTNC[0] 0 0 1 1 0 1 1 0 Blanking porch setting ------FPC[4] FPC[3] FPC[2] FPC[1] FPC[0] line inversion 0 0 0 1 0 0 0 0 ------BPC[4] BPC[3] BPC[2] BPC[1] BPC[0] 0 0 0 1 0 0 0 0 --- RTND[6] RTND[5] RTND[4] RTND[3] RTND[2] RTND[1] RTND[0] 0 0 1 1 1 0 0 0 ------FPD[4] FPD[3] FPD[2] FPD[1] FPD[0] Blanking porch setting frame inversion 0 0 0 1 0 0 0 0 ------BPD[4] BPD[3] BPD[2] BPD[1] BPD[0] 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 0 (B4h) Display inversion ----------NLA NLB NLC control 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 (B5h) --------VFP[3] VFP[2] VFP[1] VFP[0] 0 0 0 0 0 0 0 0 --------VBP[3] VBP[2] VBP[1] VBP[0] RGB I/F Blanking porch 0 0 0 0 0 0 1 0 setting --------HFP[3] HFP[2] HFP[1] HFP[0] 0 0 0 0 1 0 0 1 --------HBP[3] HBP[2] HBP[1] HBP[0] 0 0 0 0 1 0 0 1 Display function 1 0 1 1 0 1 1 0 (B6h) setting 1 0 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 0 ↑ 1 1 ↑ 1 0 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 0 ↑ 1 - 1 ↑ 1 - 1 ↑ 1 --0 --0 --0 --0 NO1 0 --0 NO0 0 --0 SDT1 0 PTG1 0 SDT0 0 PTG0 0 EQ1 1 PT1 1 EQ0 0 PT0 0 VSYNCOUT 10.2.8 0 ↑ 1 - 1 0 1 1 1 1 0 0 VSYNCOIN 10.2.9 0 ↑ 1 - 1 0 1 1 1 1 0 1 DISSET5 Ver. 1.7 10.2.7 - 106 Blanking porch setting FPB[4] FPB[3] FPB[2] FPB[1] FPB[0] 1 0 0 0 0 BPB[4] BPB[3] BPB[2] BPB[1] BPB[0] 1 0 0 0 0 ↑ 10.2.6 In normal mode full colors - 1 RGB PRCTR (B1h) RTNB[4] RTNB[3] RTNB[2] RTNB[1] RTNB[0] 1 10.2.5 Polarity set 1 0 1 1 0 Blanking porch setting FPA[4] FPA[3] FPA[2] FPA[1] FPA[0] 0 0 0 1 0 BPA[4] BPA[3] BPA[2] BPA[1] BPA[0] 0 0 0 1 0 1 0 0 1 0 (B2h) In idle mode 8-colors ↑ INVCTR (B0h) Set Display I/F mode RTNA[4] RTNA[3] RTNA[2] RTNA[1] RTNA[0] 1 FRMCTR3 10.2.4 (Hex) Function 1 0 0 1 1 (B3h) In partial mode + full colors External VSYNC disable External VSYNC (BDh) enable (BCh) 2008.04.18 ST7787 Table 10.2.2 Panel Function Command List (2) Instruction Refer D/CXWRXRDX D17-8 D7 0 ↑ 1 -1 PWCTR1 10.2.10 --1 ↑ 1 -0 0 ↑ 1 -1 -VGH3 1 ↑ 1 PWCTR2 10.2.11 -1 --1 ↑ 1 -0 0 ↑ 1 -1 --1 ↑ 1 -0 1 PWCTR3 10.2.12 1 1 PWCTR4 10.2.13 ↑ ↑ ↑ 1 1 1 1 ↑ 1 0 ↑ 1 1 ↑ 1 1 ↑ 1 1 1 ↑ ↑ 1 ↑ 1 0 ↑ 1 1 ↑ 1 PWCTR5 10.2.14 ↑ 1 1 VMCTR1 10.2.15 VMCTR2 10.2.16 ↑ ↑ 1 1 1 ↑ 1 0 ↑ 1 1 ↑ 1 1 ↑ 1 0 ↑ 1 1 ↑ 1 1 ↑ 1 D5 0 -0 0 VGH1 1 -0 0 -0 D4 0 VRH4 1 0 VGH0 1 -0 0 -0 D3 0 VRH3 0 0 VGL3 1 -0 0 -0 D2 0 VRH2 0 0 VGL2 0 GOT2 0 0 APA2 0` D1 0 VRH1 0 0 VGL1 0 GOT1 0 1 APA1 0 D0 0 VRH0 0 1 VGL0 0 GOT0 0 0 APA0 1 STEP1A _SEL2 STEP1A _SEL1 STEP1A _SEL0 --- STEP2A _SEL2 STEP2A _SEL1 STEP2A _SEL0 -- 1 0 1 1 0 0 0 1 -- 1 LDO5 _SEL2 LDO5 _SEL1 LDO5 _SEL0 --- STEP4A _SEL2 STEP4A _SEL1 STEP4A _SEL0 -- 0 0 0 1 0 0 1 1 -- -- STEP1AP _SEL2 STEP1AP _SEL1 STEP1AP_ SEL0 --- STEP2AP _SEL2 STEP2AP _SEL1 STEP2AP _SEL0 -- 0 0 0 0 0 0 0 0 -- -- -- -- -- -- STEP4AP _SEL2 STEP4AP _SEL1 STEP4AP _SEL0 ---- -1 -0 -1 -0 -0 -0 -0 -0 -0 -0 0 0 APB2 0 0 1 APB1 0 0 1 APB0 1 -- STEP1B _SEL3 STEP1B _SEL2 STEP1B _SEL1 STEP1B _SEL0 --- STEP2A _SEL2 STEP2A _SEL1 STEP2B _SEL0 -- 0 0 0 0 0 0 0 0 -- -- -- -- -- -- STEP4B _SEL2 STEP4B _SEL1 STEP4B _SEL0 -- -- -- -- -- -- 0 0 0 STEP1BP _SEL2 STEP1BP _SEL1 STEP1AP _SEL0 -- STEP2BP _SEL2 STEP2BP _SEL1 STEP2BP _SEL0 -- -- 0 0 0 -- 0 0 0 -- -- -- -- -- -- STEP4BP _SEL2 STEP4BP _SEL1 STEP4BP _SEL0 ---- -1 -0 -1 -0 -0 -0 -0 -0 -0 -0 0 1 APC2 0 0 0 APC1 0 0 0 APC0 1 STEP1C _SEL3 STEP1C _SEL2 STEP1C _SEL1 STEP1C _SEL0 --- STEP2C _SEL2 STEP2C _SEL1 STEP2C _SEL0 1 0 1 1 0 0 1 1 -- STEP4C _SEL2 STEP4C _SEL1 STEP4C _SEL0 -- 1 STEP1A_ SEL3 1 1 1 - D6 1 -0 1 VGH2 0 -0 1 -0 -- -- -- -- -- -- -- -- -- -- -- 0 1 1 -- -- STEP1CP _SEL2 STEP1CP _SEL1 STEP1CP _SEL0 --- STEP2CP _SEL2 STEP2CP _SEL1 STEP2CP _SEL0 -- -- 0 0 0 -- 0 0 0 -- -- -- -- -- -- STEP4CP _SEL2 STEP4CP _SEL1 STEP4CP _SEL0 ---- -1 -0 VMH6 0 -1 VMH 5 1 -1 VMH4 0 -0 VMH3 1 0 1 VMH2 0 0 0 VMH1 0 0 1 VMH0 0 -- -- ------- ---1 0 0 -- -- -- -- (Hex) Function (C0h) Power control setting (C1h) Power control BBh setting (C2h) In normal mode full color (C3h) In Idle mode (8-colors) (C4h) In partial mode + Full colors (C5h) VCOM control 1 VMH_ VMH_ VMH_ VMH_ VMH_ VMH_ VMH_ COLOR8M6 COLOR8M5 COLOR8M4 COLOR8M3 COLOR8M2 COLOR8M1 COLOR8M0 0 1 0 1 0 0 0 nVM0 --- --- -- --- --- --- 0 0 0 0 -1 VMA5 0 -1 VMA4 1 -0 VMA3 0 -1 VMA2 1 -1 VMA1 1 -0 VMA0 0 VMA _IDMON01 VMA _IDMON00 0 0 -- VMA VMA _IDMON05 _IDMON04 ---“-“: Don’t care Note 1: C0h to CFh are fixed for about power controller. Note 2: The C9h to CFh are reserved for further using. 0 Ver. 1.7 107 0 VMA VMA _IDMON03 _IDMON02 0 0 (C6h) VCOM control 2 2008.04.18 ST7787 Table 10.2.3 Panel Function Command List (3) Instruction Refer D/CXWRXRDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 ↑ 0 1 1 1 0 1 0 0 0 0 WRID1 10.2.17 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ↑ 1 1 0 0 0 0 0 0 0 0 ↑ 0 1 1 1 0 1 0 0 0 1 WRID2 10.2.18 0 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ↑ 1 1 0 1 0 1 1 1 0 0 ↑ 0 1 1 1 0 1 0 0 1 0 WRID3 10.2.19 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 ↑ 1 1 0 0 0 0 0 0 0 0 ↑ 0 1 1 1 0 1 1 1 1 0 OTP-Load 10.2.20 ↑ 1 1 0 1 1 1 0 1 0 1 0 ↑ 1 1 1 0 1 1 1 1 0 ↑ 1 1 1 1 0 0 1 0 1 0 ↑ 1 1 0 0 0 0 0 0 0 0 OTP-Prog 10.2.21 ↑ 1 1 1 0 1 0 1 0 1 0 ↑ 1 1 1 0 1 0 0 1 0 1 ↑ 1 1 0 1 0 1 1 0 1 0 “-“: Don’t care Note 1: The D1h to D8h registers are fixed for about ID code setting. Note 2: The D9h, DEh and DFh registers are used for NV Memory function controller. (Ex: write, clear, etc.) Ver. 1.7 108 (Hex) Function (D0h) Reserved for future using (D1h) LCM version code OTP ID2 set the LCM version code. (D2h) Customer Project code OTP ID3 set the project code. DEh OTP-Read command 75h DFh CAh OTP prog. Command 00h Protection sequence:CA AAh 00AA A5 A5 5A A5h 5Ah 2008.04.18 ST7787 Table 10.2.4 Panel Function Command List (4) Instruction GAMCTRP1 GAMCTRN1 Refer D/CXWRXRDX D17-8 0 ↑ 1 - 1 ↑ 1 - 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 10.2.22 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 0 ↑ 1 D6 D5 D4 1 1 1 0 MVA_EN --- --- --- 0 0 0 0 --- --- --- --- 0 0 0 --- --- --- 0 --0 0 --0 0 --0 --- --- --- 0 0 0 --- --- --- 0 0 0 --- --- --- 0 0 0 --- --- --- 0 0 0 --- --- --- 0 D3 D2 D1 D0 (Hex) Function 0 0 0 0 (E0h) Set Gamma correction RFP0[3] RFP0[2] RFP0[1] RFP0[0] 0 0 0 1 PKP0[3] PKP0[2] PKP0[1] PKP0[0] 1 1 0 0 PKP1[4] PKP1[3] PKP1[2] PKP1[1] PKP1[0] 1 1 0 0 1 PKP2[4] PKP2[3] PKP2[2] PKP2[1] PKP2[0] 1 1 1 0 0 PKP3[4] PKP3[3] PKP3[2] PKP3[1] PKP3[0] 1 1 0 1 1 PKP4[4] PKP4[3] PKP4[2] PKP4[1] PKP4[0] 1 1 0 0 1 1 0 0 0 PKP6[4] PKP6[3] PKP6[2] PKP6[1] PKP6[0] 1 1 0 1 0 PKP7[4] PKP7[3] PKP7[2] PKP7[1] PKP7[0] 0 0 0 0 --- --- --- --- 0 0 0 0 --- --- --- --- 1 1 0 1 PKP8[3] PKP8[2] PKP8[1] PKP8[0] 0 0 0 1 RFP1[3] RFP1[2] RFP1[1] RFP1[0] 0 0 0 0 0 --- --- --- 0 - 0 0 0 0 0 0 1 1 1 - 1 1 1 0 0 0 0 1 ↑ 1 - --- --- --- --- 0 0 0 0 1 ↑ 1 --- --- --- --- 1 ↑ 1 1 ↑ 1 ↑ 1 10.2.23 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 0 ↑ 1 1 ↑ 1 0 0 0 --- --- --- 0 0 0 --- --- --- 0 0 0 --- --- --- 0 0 0 --- --- --- 0 0 0 --- --- --- 0 0 0 --- --- --- 0 0 0 --- --- --- 0 0 1 0 OSP1[2] OSP1[1] OSP1[0] 1 RFN0[3] RFN0[2] RFN0[1] RFN0[0] 0 0 0 1 PKN0[3] PKN0[2] PKN0[1] PKN0[0] 1 1 0 0 1 0 0 1 1 1 1 0 0 PKN3[4] PKN3[3] PKN3[2] PKN3[1] PKN3[0] 1 1 0 1 1 PKN4[4] PKN4[3] PKN4[2] PKN4[1] PKN4[0] 1 1 0 0 1 PKN5[4] PKN5[3] PKN5[2] PKN5[1] PKN5[0] 1 1 0 0 Negative Polarity 0 PKN6[4] PKN6[3] PKN6[2] PKN6[1] PKN6[0] 1 1 0 1 0 PKN7[4] PKN7[3] PKN7[2] PKN7[1] PKN7[0] 0 0 0 --- --- --- 0 0 0 0 --- --- --- --- 1 1 0 1 PKN8[3] PKN8[2] PKN8[1] PKN8[0] 0 0 0 1 RFN1[3] RFN1[2] RFN1[1] RFN1[0] 0 0 0 0 0 --- --- --- --- --- - 0 0 0 0 0 0 1 1 - 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 - Set Gamma correction PKN2[4] PKN2[3] PKN2[2] PKN2[1] PKN2[0] 0 -- (E1h) PKN1[4] PKN1[3] PKN1[2] PKN1[1] PKN1[0] --- 1 Vcom 1 _Mu_mode 1 1 Postiive Polarity 1 PKP5[4] PKP5[3] PKP5[2] PKP5[1] PKP5[0] --- 1 Vcom_multi_mode10.2.24 D7 0 1 0 OSN1[2] OSN1[1] OSN1[0] (FBh) Vcom multi mode “-“: Don’t care Note 1: E0-E7 registers are fixed for about Gamma adjusting. Ver. 1.7 109 2008.04.18 ST7787 10.1.1 NOP (00h) 00H Inst / Para NOP Parameter D/CX WRX RDX 0 1 ↑ D17-8 - D7 0 NOP (No Operation) D6 D5 D4 D3 0 0 0 0 No Parameter D2 0 D1 0 D0 0 (Code) (00h) - NOTE: “-“ Don’t care -This command is empty command. It does not have effect on the display module. Description -However it can be used to terminate RAM data write or read as described in RAMWR (Memory Write), RAMRD (Memory Read) and parameter write commands. Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence N/A S/W Reset N/A H/W Reset N/A Flow Chart Ver. 1.7 - 110 2008.04.18 ST7787 10.1.2 SWRESET (01h): Software Reset 01H Inst / Para SWRESET Parameter D/CX WRX RDX 0 1 ↑ D17-8 - D7 0 SWRESET (Software Reset) D6 D5 D4 D3 0 0 0 0 No Parameter D2 0 D1 0 D0 1 (Code) (01h) - NOTE: “-“ Don’t care Description -When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values and all source & gate outputs are set to VSS (display off). (See default tables in each command description) Note: The Frame Memory contents are not affected by this command. -It will be necessary to wait 120msec before sending new command following software reset. -The display module loads all display supplier ’s factory default values to the registers during 120msec. Restriction -If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out command. -Software Reset command cannot be sent during Sleep Out sequence. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Default Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence N/A S/W Reset N/A H/W Reset N/A Legend SWRESET (01h) Command Parameter Display whole blank screen Display Flow Chart Action Set Commands to S/W Default Value Mode Sequential Sleep In Mode Ver. 1.7 111 2008.04.18 ST7787 10.1.3 RDDID (04h): Read Display ID RDDID (Read Display ID) 04H Inst / Para RDDID 1st Parameter 2nd Parameter 3rt Parameter 4th Parameter D/CX WRX RDX 0 ↑ 1 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ D17-8 - D7 0 ID17 ID27 ID37 D6 0 ID16 ID26 ID36 D5 0 ID15 ID25 ID35 D4 0 ID14 ID24 ID34 D3 0 ID13 ID23 ID33 D2 1 ID12 ID22 ID32 D1 0 ID11 ID21 ID31 D0 0 ID10 ID20 ID30 (Code) (04h) Dummy NOTE: “-“ Don’t care -This read byte returns 24-bit display identification information. -The 1st parameter is dummy data -The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID. Description -The 3rd parameter (ID27 to ID20): LCD module/driver version ID -The 4th parameter (ID37 to UD30): LCD module/driver ID. NOTE: Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively. Restriction Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status Default Flow Chart ID1 ID2 ID3 Power On Sequence N/A N/A N/A S/W Reset N/A N/A N/A H/W Reset N/A N/A N/A Serial I/F Mode Parallel I/F Mode RDDID (04h) RDDID (04h) Dummy Clock Dummy Read Send ID1[7:0] Send ID1[7:0] Legend Host Driver Command Parameter Display Action Mode Ver. 1.7 Send ID2[7:0] Send ID2[7:0] Send ID3[7:0] Send ID3[7:0] 112 Sequential transfer 2008.04.18 ST7787 10.1.4 RDDST (09h): Read Display Status 09H Inst / Para RDDST D/CX WRX RDX 0 ↑ 1 1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 5th Parameter 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ D17-8 - D7 0 - RDDST (Read Display Status) D6 D5 D4 D3 0 0 0 1 - - - - BSTON ST23 VSSON GCS1 MY IFPF2 ST14 GCS0 MX IFPF1 INVON TELOM MV IFPF0 ST12 HSON - D2 0 D1 0 D0 1 (Code) (09h) - - - - ML RGB MH ST24 IDMON PTLON SLOUT NORON ST11 DISON TEON GCS2 VSON PCKON DEON ST0 NOTE: “-“ Don’t care This command indicates the current status of the display as described in the table below: Description Bit BSTON Description Booster Voltage Status MY Row Address Order (MY) MX Column Address Order (MX) MV Row/Column Exchange (MV) ML Scan Address Order (ML) RGB RGB/ BGR Order (RGB) MH Horizontal Order ST24 ST23 IFPF2 IFPF1 IFCPF0 IDMON PTLON SLPOUT NORON For Future Use For Future Use Interface Color Pixel Format Definition Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off VSSON ST14 INVON ST12 ST11 DISON TEON TELOM HSON Vertical Scrolling Status Horizontal Scroll Status Inversion Status All Pixels On (Not Used) All Pixels Off (Not Used) Display On/Off Tearing effect line on/off Tearing effect line mode Horizontal Sync. (HS, RGB I/F) Vertical Sync, (VS, RGB I/F) Pixel Clock (PCLK, RGB I/F) Data Enable (DE, RGB I/F) For Future Use VSON PCLKON DEON ST0 GS 0 1 Ver. 1.7 Value 1’ =Booster on, 0’ =Booster off ‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’) ‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7=’0’) ‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’) ‘0’ =Increment, (Left to Right, when MADCTL (36h) D6=’1’) ‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’) ‘0’ = Normal, (when MADCTL (36h) D5=’0’) ‘1’ =Decrement, (LCD refresh Top to Bottom, when MADCTL (36h) D4=’1’) “0”=Increment, (LCD refresh Bottom to Top, when MADCTL (36h) D4=’0’) ‘1’ =BGR, (When MADCTL (36h) D3=’1’) ‘0’ =RGB, (When MADCTL (36h) D3=’0’) ‘1’ =Decrement, (LCD refresh Left to Right, when MADCTL (36h) D2=’1’) ‘0’ =Increment, (LCD refresh Right to Left, when MADCTL (36h) D2=’0’) ‘0’ ‘0’ “011” = 12-bit / pixel, “101” = 16-bit / pixel, “110” = 18-bit / pixel, others are no define ‘1’ = On, “0” = Off ‘1’ = On, “0” = Off ‘1’ = Out, “0” = In ‘1’ = Normal Display, ‘0’ = Partial Display ‘1’ = Scroll on,“0” = Scroll off ‘0’ ‘1’ = On, “0” = Off ‘0’ ‘0’ ‘1’ = On, “0” = Off ‘1’ = On, “0” = Off ‘0’ = mode1, ‘1’ = mode2 ‘1’ = On, ‘0’ = Off ‘1’ = On, ‘0’ = Off ‘1’ = On, ‘0’ = Off ‘1’ = On, ‘0’ = Off ‘0’ GC[7:0] 01h GCS[2:0] 000 02h 001 04h 010 (LCM=[01]) 08h 011 01h 000 (LCM=[01]) 02h 001 04h 010 113 TR LCtype γ=1.0 γ=2.5 γ=2.2 γ=1.8 γ=2.2 γ=1.8 γ=2.5 2008.04.18 ST7787 Note: ST0, ST5, ST9, ST11-ST15, ST19, ST23, ST24 are set to ‘0’, when RGB I/F. - Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Status Default Power On Sequence S/W Reset H/W Reset ST[31-24] 0000-0000 0xxx0xx00 0000-0000 Default Value (ST31 to ST0) ST[23-16] ST[15-8] 0110-0001 0000-0000 0xxx-0001 0000-0000 0110-0001 0000-0000 Serial I/F Mode Parallel I/F Mode RDDST (09h) RDDST (09h) ST[7-0] 0000-0000 0000-0000 0000-0000 Host Driver Dummy Clock Dummy Read Send ST[31:24] Send ST[31:24] Send ST[23:16] Send ST[23:16] Send ST[15:8] Send ST[15:8] Legend Command Flow Chart Parameter Display Action Mode Sequential transfer Send ST[7:0] Ver. 1.7 Send ST[7:0] 114 2008.04.18 ST7787 10.1.5 RDDPM (0Ah): Read Display Power Mode 0AH Inst / Para RDDPM D/CX WRX RDX 0 ↑ 1 1st Parameter 2nd Parameter 1 1 1 1 RDDPM (Read Display Power Mode) D7 D6 D5 D4 D3 0 0 0 0 1 D17-8 - ↑ ↑ - D2 0 D1 1 D0 0 (Code) (0Ah) D1 D0 - BSTON IDMON PTLON SLPOUT NORON DISON NOTE: “-” Don’t care, can be set to VDDI or DGND level This command indicates the current status of the display as described in the table below: Bit Description Description BSTON Booster Voltage Status IDMON Idle Mode On/Off PTLON Partial Mode On/Off SLPON Sleep In/Out NORON Display Normal Mode On/Off DISON Display On/Off D1 D0 Not Used Not Used Value 1’ =Booster on, 0’ =Booster off “1” = Idle Mode On, “0” = Idle Mode Off “1” = Partial Mode On, “0” = Partial Mode Off “1” = Sleep Out, “0” = Sleep In “1” = Normal Display, “0” = Partial Display “1” = Display On, “0” = Display Off “0” “0” - Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value (D7 to D0) 08h 08h 08h Serial I/F Mode Parallel I/F Mode RDDPM (0Ah) RDDPM (0Ah) Legend Command Host Driver Flow Chart Send D[7:0] Dummy Read Parameter Display Action Mode Send D[7:0] Sequential transfer Ver. 1.7 115 2008.04.18 ST7787 10.1.6 RDDMADCTL (0Bh): Read Display MADCTL 0BH Inst / Para RDDMADCTL D/CX 0 WRX ↑ RDX 1 1st Parameter 2nd Parameter 1 1 1 1 ↑ ↑ RDDMADCTL (Read Display MADCTL) D17-8 D7 D6 D5 D4 D3 0 0 0 0 1 - MY MX MV ML RGB D2 0 D1 1 D0 1 (Code) (0Bh) MH D1 D0 - NOTE: “-” Don’t care, can be set to VDDI or DGND level This command indicates the current status of the display as described in the table below: Description Bit Description MX Row Address Order MY Column Address Order MV Row/Column Order (MV) ML Vertical Refresh Order RGB RGB/BGR Order MH Horizontal order D1 D0 Not Used Not Used Value ‘1’ = Bottom to Top (When MADCTL B7=’1’) ‘0’ = Top to Bottom (When MADCTL B7=’0’) ‘1’ = Right to Left (When MADCTL B6=’1’) ‘0’ = Left to Right (When MADCTL B6=’0’) ‘1’ = Row/column exchange (MV=1) ‘0’ = Normal (MV=0) ‘1’ =LCD Refresh Bottom to Top ‘0’ =LCD Refresh Top to Bottom ‘1’ =BGR, “0”=RGB ‘1’ =LCD Refresh Right to Left ‘0’ =LCD Refresh Left to Right “0” “0” - Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value (D7 to D0) 00h No change 00h Legend Serial I/F Mode Parallel I/F Mode Command RDDMADCTL (0Bh) RDDMADCTL (0Bh) Host Driver Flow Chart Send D[7:0] Dummy Read Parameter Display Action Mode Send D[7:0] Sequential transfer Ver. 1.7 116 2008.04.18 ST7787 10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format 0CH Inst / Para RDDCOLMOD D/CX 0 WRX 1st Parameter 2nd Parameter 1 1 ↑ RDX 1 D17-8 - 1 1 ↑ ↑ - RDDCOLMOD (Read Display Pixel Format) D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 VIPF3 VIPF2 VIPF1 VIPF0 D3 IFPF2 D1 0 D0 0 (Code) (0Ch) IFPF1 IFPF0 - NOTE: “-” Don’t care, can be set to VDDI or DGND level This command indicates the current status of the display as described in the table below: IFPF[2:0] 011 101 110 111 MCU Interface Color Format 12-bit/pixel 16-bit/pixel 18-bit/pixel No used 3 5 6 7 Description Others are no define and invalid VIFPF[2:0] 0101 0110 0111 1110 RGB Interface Color Format 16-bit/pixel (1-times data transfer) 18-bit/pixel (1-times data transfer) No used 18-bit/pixel (3-times data transfer) 5 6 7 14 Others are no define and invalid - Restriction Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence S/W Reset H/W Reset Default Value IFPF[2:0] 0110 (18 bits/pixel) No Change 0110 (18 bits/pixel) VIPF[3:0] 0110 (18 bits/pixel) No Change 0110 (18 bits/pixel) Legend Serial I/F Mode Parallel I/F Mode Command RDDCOLMOD (0Ch) RDDCOLMOD (0Ch) Host Driver Flow Chart Send D[7:0] Dummy Read Parameter Display Action Mode Send D[7:0] Sequential transfer Ver. 1.7 117 2008.04.18 ST7787 10.1.8 RDDIM (0Dh): Read Display Image Mode 0DH Inst / Para RDDIM D/CX WRX RDX 0 ↑ 1 1st Parameter 2nd Parameter 1 1 1 1 D17-8 - RDDIM (0Dh): Read Display Image Mode D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 - ↑ ↑ D1 0 D0 1 (Code) (0Dh) - - - - - - - - - VSSON D6 INVON D4 D3 GCS2 GCS1 GCS0 NOTE: “-” Don’t care, can be set to VDDI or DGND level This command indicates the current status of the display as described in the table below: Bit Description VSSON D6 Value “1” = Vertical scrolling is On, “0” = Vertical scrolling is Off “0” (Not used) “1” = Inversion is On, “0” = Inversion is Off “0” (Not used) “0” (Not used) Vertical Scrolling On/Off Horizontal Scrolling On/Off INVON D4 D3 Inversion On/Off All Pixels On All Pixels Off GS GC[7:0] Reg. LCM1 LCM0 LC Type 0 0 MVA 0 1 Transflective(TR) 1 0 Transmissive(TM) 1 1 N/A 02H X X Transflective(TR) 1.8 04H X X Transflective(TR) 2.5 08H X X Transflective(TR) 1.0 01H X X Transflective(TR) 1.0 02H X X Transflective(TR) 2.5 0 0 MVA 0 1 Transflective(TR) 1 0 Transmissive(TM) 1 1 N/A X X 01H 1 Description 0 Curve 2.2 04H 08H Gamma Curve 2.2 Transflective(TR) 1.8 Note 1: While LCM[1:0]=”00” Note 2: Even GCS[2:0] value is be changeable from read status, the gamma curve of Transmissive and MVA only γ =2.2. Restriction Register Availability Default Ver. 1.7 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value(D7 to D0) 0000_0001 (01h) 0000_0001 (01h) 0000_0001 (01h) 118 2008.04.18 ST7787 Legend Serial I/F Mode Parallel I/F Mode Command RDDIM (0Dh) RDDIM (0Dh) Host Driver Flow Chart Send D[7:0] Dummy Read Parameter Display Action Mode Send D[7:0] Sequential transfer Ver. 1.7 119 2008.04.18 ST7787 10.1.9 RDDSM (0Eh): Read Display Signal Mode 0EH RDDSM (0Eh): Read Display Signal Mode Inst / Para RDDSM D/CX WRX 0 ↑ 1st Parameter nd 2 Parameter RDX 1 D17-8 - D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 (Code) (0Eh) - 1 1 ↑ - - - - - - - - - 1 1 ↑ - TEON TELOM HSON VSON PCKON DEON D1 D0 NOTE: “-” Don’t care, can be set to VDDI or DGND level This command indicates the current status of the display as described in the table below: Bit Description TEON Description Value Tearing Effect Line On/Off TELOM Tearing effect line mode HSON Horizontal Sync. (RGB I/F) On/Off VSON Vertical Sync. (RGB I/F) On/Off PCKON DEON Pixel Clock (PCLK, RGB I/F) On/Off Data Enable (DE, RGB I/F) On/Off D1 Not Used D0 Not Used - Restriction Register Availability Default “1” = On, “0” = Off “1” = mode1, “0” = mode2 “1” = On, “0” = Off “1” = On, “0” = Off “1” = On, “0” = Off “1” = On, “0” = Off “1” = On, “0” = Off “1” = On, “0” = Off Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value(D7~D0) 00h 00h 00h Legend Serial I/F Mode Parallel I/F Mode Command RDDSM (0Eh) RDDSM (0Eh) Host Driver Flow Chart Send D[7:0] Dummy Read Parameter Display Action Mode Send D[7:0] Sequential transfer Ver. 1.7 120 2008.04.18 ST7787 10.1.10 RDDSDR (0Fh): Read Display Self-Diagnostic Result 0FH Inst / Para RDDSDR D/CX 0 WRX ↑ RDX 1 1st Parameter 2nd Parameter 1 1 1 1 ↑ ↑ RDDSDR (0Fh): Read Display Self-Diagnostic Result D17-8 D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 - RELD FUND ATTD BRD D3 D2 D1 1 D0 1 (Code) (0Fh) D1 D0 - NOTE: “-” Don’t care, can be set to VDDI or DGND level This command indicates the current status of the display as described in the table below: Description Bit RELD FUND ATTD BRD D3 D2 D1 D0 Description Register Loading Detection Functionality Detection Chip Attachment Detection Display Glass Break Detection Not Used Not Used Not Used Not Used Value See section 9.19 See section 9.19 “1” “1” “0” “0” “0” “0” - Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value(D7~D0) Legend Serial I/F Mode Parallel I/F Mode Command RDDSDR (0Fh) RDDSDR (0Fh) Host Driver Flow Chart Send D[7:0] Dum my Read Parameter Display Action Mode Send D[7:0] Sequential transfer Ver. 1.7 121 2008.04.18 ST7787 10.1.11 SLPIN (10h): Sleep In 10H Inst / Para SLPIN st 1 Parameter D/CX 0 WRX ↑ RDX 1 SLPIN (Sleep In) D7 D6 D5 D4 0 0 0 1 No parameter D17-8 - D3 0 D2 0 D1 0 D0 0 (Code) (10h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command causes the LCD module to enter the minimum power consumption mode. -In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped. Sleep In 1.6V-3.0V VDDI VDD 2.6V-3.0V Gate Output Description STOP Source Output 0V VCOM Output 0V Blanking display (over 1frame display) * 0V Internal counter STOP Internal Oscillator STOP DC charge in capacitors DISCHARGE 0V or VDD VGH 0V or VDD VGL 0V AVDD 0V or VDD IC Internal reset 0V * Note: complete 1 frame display (ex: continue 2-falling edges of VS) -MCU interface and memory are still working and the memory keeps its contents -This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out Command (11h). -It will be necessary to wait 120msec before sending next command , this is to allow time for the supply Restriction voltages and clock circuits to stabilize. -It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Register Availability Default Ver. 1.7 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Sleep in mode Sleep in mode Sleep in mode 122 2008.04.18 ST7787 -It takes about 120msec to get into Sleep In mode (booster off state) after SLPIN command issued. -The results of booster off can be check by RDDST (09h) command Bit31. Legend SPLIN (10h) Flow Chart Display whole blank screen (Automatic No effect to DISP ON/OFF Command) Stop DC/DC Converter Ver. 1.7 Parameter Display Stop Internal Oscillator Action Sleep In Sequential transfer Drain charge from LCD Command 123 Mode 2008.04.18 ST7787 10.1.12 SLPOUT (11h): Sleep Out 11H Inst / Para SLPOUT 1st Parameter D/CX 0 WRX ↑ RDX 1 SLPOUT (Sleep Out) D7 D6 D5 D4 0 0 0 1 No Parameter D17-8 - D3 0 D2 0 D1 0 D0 1 (Code) (11h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command turns off sleep mode. -In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started. Sleep Out Description VDDI 1.6V-3.0V VDD 2.6V-3.0V Internal Oscillator STOP AVDD 0V or VDD Start VGL 0V VGH 0V or VDD Internal counter STOP IC Internal reset 0V Gate Output STOP Source Output 0V 0V Memory Contents VCOM Output 0V 0V Memory Contents Start STOP Blanking display (over 1fram e display) * If DISPON 29h is set * Note: complete 1 frame display (ex: continue 2-falling edges of VS) -This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10h). -It will be necessary to wait 120msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. -DRIVER loads all default values of extended and test command to the registers during this 120msec and Restriction there cannot be any abnormal visual effect on the display image if those default and register values are same when this load is done and when the DRIVER is already Sleep Out mode. -DRIVER is doing self-diagnostic functions during this 120msec. See also section 9.20. -It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent Register Availability Default Ver. 1.7 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Sleep in mode Sleep in mode Sleep in mode 124 2008.04.18 ST7787 -It takes 120msec to become Sleep Out mode (booster on mode) after SLPOUT command issued. -The results of booster on can be checked by RDDST (09h) command Bit31. SLPOUT (11h) Legend Start Internal Oscillator Flow Chart Start DC-DC Converter Charge Offset voltage for LCD Panel Display whole blank screen for 2 frames (Automatic No effect to DISP ON/OFF Command Parameter Display Display Memory contents in accordance with the current command table settings Action Mode Sequential transfer Sleep Out Ver. 1.7 125 2008.04.18 ST7787 10.1.13 PTLON (12h): Partial Display Mode On 12H Inst / Para PTLON st 1 Parameter D/CX 0 WRX ↑ RDX 1 PTLON (12h): Partial Display Mode On D17-8 D7 D6 D5 D4 D3 D2 0 0 0 1 0 0 No Parameter D1 1 D0 0 (Code) (12h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h) Description -To leave Partial mode, the Normal Display Mode On command (13H) should be written. -There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On. Restriction This command has no effect when Partial mode is active. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Normal Mode On Normal Mode On Normal Mode On Flow Chart See Partial Area (30h) Ver. 1.7 126 2008.04.18 ST7787 10.1.14 NORON (13h): Normal Display Mode On 13H Inst / Para NORON st 1 Parameter D/CX 0 WRX ↑ RDX 1 NORON (Normal Display Mode On) D17-8 D7 D6 D5 D4 D3 0 0 0 1 0 No Parameter D2 0 D1 1 D0 1 (Code) (13h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command returns the display to normal mode. -Normal display mode on means Partial mode off, Scroll mode Off. Description -Exit from NORON by the Partial mode On command (12h) -There is no abnormal visual effect during mode change from Normal mode On to Partial mode On. Restriction -This command has no effect when Normal Display mode is active. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Normal Mode On Normal Mode On Normal Mode On Flow Chart -See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command Ver. 1.7 127 2008.04.18 ST7787 9.1.15 INVOFF (20h): Display Inversion Off 20H Inst / Para INVOFF st 1 Parameter D/CX 0 WRX ↑ IVNOFF (Normal Display Mode Off) D17-8 D7 D6 D5 D4 D3 0 0 1 0 0 No Parameter RDX 1 D2 0 D1 0 D0 0 (Code) (20h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to recover from display inversion mode. -This command makes no change of contents of frame memory. -This command does not change any other status. (Example) Top-Left (0,0) Memory Display Description Restriction -This command has no effect when module is already inversion off mode. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Display Inversion off Display Inversion off Display Inversion off Legend Display Inversion On Mode Command Parameter Display Flow Chart INVOFF (20h) Action Mode Display Inversion OFF Sequential transfer Ver. 1.7 128 2008.04.18 ST7787 10.1.16 INVON (21h): Display Inversion On 21H Inst / Para INVON st 1 Parameter D/CX 0 WRX ↑ IVNOFF (Display Inversion On) D17-8 D7 D6 D5 D4 D3 0 0 1 0 0 No Parameter RDX 1 D2 0 D1 0 D0 1 (Code) (21h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to enter into display inversion mode -This command makes no change of contents of frame memory. -This command does not change any other status. -To exit from Display Inversion On, the Display Inversion Off command (20h) should be written. (Example) Description Top-Left (0,0) Memory Display Restriction -This command has no effect when module is already Inversion On mode. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Display Inversion off Display Inversion off Display Inversion off Legend Display Inversion On Mode Command Parameter Display Flow Chart INVON (21h) Action Mode Display Inversion OFF Sequential transfer Ver. 1.7 129 2008.04.18 ST7787 10.1.17 GAMSET (26h): Gamma Set 26H Inst / Para GAMSET D/CX 0 1st Parameter 1 WRX ↑ ↑ RDX 1 1 GAMSET (Gamma Set) D6 D5 D4 0 1 0 D17-8 - D7 0 - GC7 GC6 GC5 GC4 D3 0 D2 1 D1 1 D0 0 GC3 GC2 GC1 GC0 (Code) (26h) NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curves are defined in section 9.17 The curve is selected by setting the appropriate bit in the parameter as described in the Table. GS GC[7:0] Reg. LCM1 LCM0 LC Type 0 0 MVA 0 1 Transflective(TR) 01H Gamma Curve 2.2 1 0 Transmissive(TM) 1 1 N/A 02H X X Transflective(TR) 1.8 04H X X Transflective(TR) 2.5 08H X X Transflective(TR) 1.0 01H X X Transflective(TR) 1.0 02H X X Transflective(TR) 2.5 0 0 MVA 0 1 Transflective(TR) 1 0 Transmissive(TM) 1 1 N/A X X 1 Description 0 04H Curve 2.2 08H Transflective(TR) 1.8 Note: All other values are undefined. -Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma Restriction curve until valid is received. Register Availability Default Ver. 1.7 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value 01h 01h 01h 130 2008.04.18 ST7787 Legend ---------------- Com and GAMSET (26h) Parameter Display Flow Chart 1st Parameter: GC[7:0] Action Mode Sequential New Gamma Curve Loaded Ver. 1.7 131 2008.04.18 ST7787 10.1.18 DISPOFF (28h): Display Off 28H Inst / Para DISPOFF st 1 Parameter D/CX 0 WRX ↑ RDX 1 D17-8 - DISPOFF (Display Off) D7 D6 D5 D4 0 0 1 0 No Parameter D3 1 D2 0 D1 0 D0 0 (Code) (28h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and blank page inserted. -This command makes no change of contents of frame memory. -This command does not change any other status. -There will be no abnormal visible effect on the display. -Exit from this command by Display On (29h) (Example) Top-Left (0,0) Memory Display Display OFF VDDI 1.6V-3.0V VDD 2.6V-3.0V Description Gate Output STOP Source Output 0V VCOM Output 0V Blanking display (over 1 frame display) * 0V Internal counter STOP Internal Oscillator VGH VGL AVDD IC Internal reset * Note: complete 1 frame display (ex: continue 2-falling edges of VS) Restriction -This command has no effect when module is already in Display Off mode. Register Availability Default Ver. 1.7 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Display off Display off Display off 132 2008.04.18 ST7787 Legend Display Inversion On Mode Command Parameter Display Flow Chart DISPOFF (28h) Action Mode Display Inversion OFF Sequential transfer Ver. 1.7 133 2008.04.18 ST7787 10.1.19 DISPON (29h): Display On 29H Inst / Para DISPON st 1 Parameter D/CX 0 WRX ↑ RDX 1 D17-8 - DISPON (Display On) D7 D6 D5 D4 0 0 1 0 No Parameter D3 1 D2 0 D1 0 D0 1 (Code) (29h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. -This command makes no change of contents of frame memory. -This command does not change any other status. (Example) Top-Left (0,0) Memory Display Display ON 1.6V-3.0V VDDI Description VDD 2.6V-3.0V Blanking display (over 1 frame display) * Gate Output STOP Source Output 0V Memory Contents VCOM Output 0V Memory Contents Internal counter STOP Start Internal Oscillator VGH VGL AVDD IC Internal reset * Note: complete 1 frame display (ex: continue 2-falling edges of VS) Restriction -This command has no effect when module is already in Display On mode. Register Availability Default Ver. 1.7 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Display off Display off Display off 134 2008.04.18 ST7787 Legend Display OFF Mode Command Parameter Display Flow Chart DISPON (29h) Action Mode Display ON Mode Sequential transfer Ver. 1.7 135 2008.04.18 ST7787 10.1.20 CASET (2Ah): Column Address Set 2AH Inst / Para GAMSET D/CX 0 1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 1 1 1 1 WRX ↑ ↑ ↑ ↑ ↑ RDX 1 D17-8 - 1 1 1 1 - CASET(Colume Address Set)_ D7 D6 D5 D4 D3 0 0 1 0 0 D2 1 D1 1 D0 0 XS7 XE7 XS2 XE2 XS1 XE1 XS8 XS0 XE8 XE0 XS6 XE6 XS5 XE5 XS4 XE4 XS3 XE3 (Code) (2Ah) NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to define area of frame memory where MCU can access. -This command makes no change on the other driver status. -The value of XS [8:0] and XE [8:0] are referred when RAMWR command comes. -Each value represents one column line in the Frame Memory. (Example) XS[8:0] XE[8:0] Description Xaddress start: 0≦XS≦EF MV=0 Restriction Xaddress end: XS≦XE≦EF MV=0 Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes 1. 240x320 memory base 2Status Default Ver. 1.7 Power On Sequence S/W Reset H/W Reset Default Value XS[8:0] 0000h 0000h 0000h XE[8:0] 00EFh 00EFh 00EFh 136 2008.04.18 ST7787 Partial Mode CASET (2Ah) 1st & 2nd Parameter: XS[8:0] 3rd & 4th Parameter: XE[8:0] RASET (2Bh) Flow Chart 1st & 2nd Parameter: YS[8:0] 3rd & 4th Parameter: YE[8:0] Legend RAMWR (2Ch) Command Parameter Image Data D1[17:0],D2[17:0]…Dn[17:0] Display Action Mode Any Command Ver. 1.7 Sequential 137 2008.04.18 ST7787 10.1.21 RASET (2Bh): Row Address Set 2BH Inst / Para RASET (2Bh) D/CX 0 1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 1 1 1 1 WRX ↑ ↑ ↑ ↑ ↑ RASET (Row Address Set) D6 D5 D4 D3 0 1 0 1 RDX 1 D17-8 - D7 0 1 1 1 1 - YS7 YE7 YS6 YE6 YS5 YE5 YS4 YE4 YS3 YE3 D2 0 D1 1 D0 1 YS2 YE2 YS1 YE1 YS8 YS0 YE8 YE0 (Code) (2Bh) NOTE: “-” Don’t care, can be set to VDDI or DGND level This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The value of YS [8:0] and YE [8:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory. Example YS[8:0] Description YE[8:0] Xaddress start: 0≦YS≦13F MV=0 Restriction Xaddress end: YS≦YE≦13F MV=0 Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes 1. 240x320 memory base 2Status Default Ver. 1.7 Power On Sequence S/W Reset H/W Reset Default Value YS[8:0] 0000h 0000h 0000h YE[8:0] 013Fh 013Fh 013Fh 138 2008.04.18 ST7787 Partial Mode CASET (2Ah) 1st & 2nd Parameter: XS[8:0] 3rd & 4th Parameter: XE[8:0] RASET (2Bh) Flow Chart 1st & 2nd Parameter: YS[8:0] 3rd & 4th Parameter: YE[8:0] Legend RAMWR (2Ch) Command Parameter Image Data D1[17:0],D2[17:0]…Dn[17:0] Display Action Mode Any Command Ver. 1.7 Sequential 139 2008.04.18 ST7787 10.1.22 RAMWR (2Ch): Memory Write 2CH Inst / Para RAMWR 1st Parameter ∣ Nth Parameter D/CX 0 1 1 1 WRX ↑ ↑ ↑ ↑ RDX 1 1 1 1 D17-8 D17-8 RAMWR (Memory Write) D7 D6 D5 D4 0 0 1 0 D7 D6 D5 D4 D3 1 D3 D2 1 D2 D1 0 D1 D0 0 D0 (Code) (2Ch) - ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ D17-8 D7 D6 D5 D4 D3 D2 D1 D0 - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to transfer data from MCU to frame memory. -This command makes no change to the other driver status. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. Description -The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 9.12) -Then D[23:0] is stored in frame memory and the column register and the row register incremented as section 9.10.2. -Sending any other command can stop Frame Write. Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared Legend RAMWR (2Ch) Command Parameter Flow Chart Image Data D1[17:0],D2[17:0]…Dn[17:0] Display Action Mode Any Command Ver. 1.7 Sequential 140 2008.04.18 ST7787 10.1.23 RAMRD (2Eh): Memory Read 2Eh Inst / Para RAMRD 1st Parameter 2nd Parameter ∣ (N+1)th Parameter D/CX 0 WRX ↑ RDX 1 D17-8 - 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ D17-8 RAMRD (Memory Read) D7 D6 D5 D4 D3 0 0 1 0 1 D7 D6 D5 D4 D3 D2 1 D1 1 D0 0 (Code) (2Eh) D2 D1 D0 - ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ D17-8 D7 D6 D5 D4 D3 D2 D1 D0 - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to transfer data from frame memory to MCU. -This command makes no change to the other driver status. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. -The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 9.12) Description -Then D[23:0] is read back from the frame memory and the column register and the row register incremented as section 9.10.2. -Frame Read can be canceled by sending any other command. -See section 9.8 “Data color coding” for color coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data. -In all color modes, the Frame Read is always 18- bits and there is no restriction on length of parameters. Restriction -Memory read is only possible via the SPI and parallel interface Status Register Availability Default Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared RAMRD (2Eh) Legend Command Dummy Read Parameter Display Flow Chart Image Data D1[17:0],D2[17:0]…Dn[17:0] Action Mode Sequential Any Command Ver. 1.7 141 2008.04.18 ST7787 10.1.24 PTLAR (30h): Partial Area 30H Inst / Para PTLAR D/CX WRX 0 ↑ 1st Parameter 2nd Parameter 1 1 ↑ 3rd Parameter 4th Parameter 1 1 ↑ RDX D17-8 1 - ↑ ↑ 1 1 - 1 1 - PTLAR (Partial Area) D6 D5 D4 D3 0 1 1 0 D7 0 D2 0 D1 0 D0 0 (Code) (30h) -- -- -- -- -- -- -- PSL8 PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 -- -- -- -- -- -- -- PEL8 PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command defines the partial mode’s display area. -There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter. -If End Row > Start Row, when MADCTL ML=’0’ Start Row PSL [8:0] Non-displaying Area Partial Display Area PEL [8:0] Non-displaying Area End Row -If End Row > Start Row, when MADCTL ML=’1’ End Row PEL [8:0] Description Non-displaying Area Partial Display Area PSL [8:0] Non-displaying Area Start Row -If End Row < Start Row, when MADCTL ML=’0’ End Row Partial Display Area Non-displaying Area PSL [8:0] Start Row PEL [8:0] -If End Row = Start Row then the Partial Area will be one row deep. - Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Availability Yes Yes Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Status Default Ver. 1.7 Power On Sequence S/W Reset H/W Reset Default Value PSL[7:0] PE[8] 0000h 0h 0000h 0h 0000h 0h PSL[8] 0h 0h 0h 142 PEL[7:0] 0000h 0000h 0000h 2008.04.18 ST7787 1. To Enter Partial Mode 2. To Exit Partial Mode Partial Mode PTYLAR (30h) 1st & 2nd Parameter: PSEL[8:0] NORON (13h) Legend D 3rd & 4th Parameter: PEL[8:0] Flow Chart DISPOFF (28h) Optional to prevent tearing effect image display Partial Mode OFF PTLON (12h) Command Parameter RAMRW (2Ch) Partial Mode Display Action Image Data D1[17:0],D2[17:0]… Dn[17:0] Mode Sequential transfer DISON (29h) Ver. 1.7 143 2008.04.18 ST7787 10.1.25 SCRLAR (33h): Scroll Area 33H Inst / Para PTLAR 1st Parameter nd 2 Parameter 3rd Parameter 4th Parameter 5th Parameter 6th Parameter D/CX WRX RDX D17-8 0 ↑ 1 - D7 0 SCRLAR (Scrolll Area) D6 D5 D4 D3 0 1 1 0 D2 0 D1 1 D0 1 TFA8 1 ↑ 1 - --- --- --- --- --- --- --- 1 1 1 1 1 ↑ 1 1 1 1 1 - TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 --- --- --- --- --- --- --- VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 --BFA7 --BFA6 --BFA5 --BFA4 --BFA3 --BFA2 --BFA1 BFA8 BFA0 ↑ ↑ ↑ ↑ (Code) (33h) NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command defines the Vertical Scrolling Area of the display. When MADCTL ML=0 st nd －The 1 & 2 parameter TFA [8:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). rd th －The 3 & 4 parameter VSA [8:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) －The first line appears immediately after the bottom most line of the Top Fixed Area. th th －The 5 & 6 parameter BFA [8:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). －TFA, VSA and BFA refer to the Frame Memory row address. Top-Left (0,0) Top Fixed Area TFA [8:0] First line read from Scroll Fixed Area VSFA [8:0] Bottom Fixed Area BFA [8:0] Description When MADCTL ML=1 st nd －The 1 & 2 parameter TFA [8:0] describes the Top Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). rd th －The 3 & 4 parameter VSA [8:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) －The first line appears immediately after the top most line of the Top Fixed Area. th th －The 5 & 6 parameter BFA [8:0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory and Display). Top-Left (0,0) Bottom Fixed Area BFA [8:0] Scroll Fixed Area VSFA [8:0] First line read from Top Fixed Area frame memory TFA [8:0] See Section 9.10.4 for details of the Memory to Display Mapping. Restriction Register Availability Ver. 1.7 -In Vertical Scroll Mode, MADCTL parameter MV should be set to ‘0’-this only affects the Frame Memory Write. TFA[8:0]+VSA[8:0]+BFA[8:0] must equal to 320 or abnoemal display will be observed. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes 144 2008.04.18 ST7787 Status Default Power On Sequence S/W Reset H/W Reset TFA8 0h 0h 0h TFA[7:0] 00h 00h 00h Default Value VFA8 VFA[7:0] 1h 40h 1h 40h 1h 40h 1. To Enter Vertical Scroll Mode Normal Mode BFA8 0h 0h 0h BFA[7:0] 00h 00h 00h Legend Command Parameter SCRLAR (33h) Display 1st & 2nd Parameter: TFA[8:0] Action 3rd & 4th Parameter VSA[8:0] Mode 5th & 6th Parameter BFA[8:0] Sequential transfer CASET (2Ah) 1st & 2nd Parameter XS[7:0] 3rd & 4th Parameter XE[7:0] RASET (2 Redefines the Frame memory Window that the scroll data will be define 1st & 2nd Parameter YS[7:0] Flow Chart Only required for non-rolling scrolling 3rd & 4th Parameter YE[7:0] MADCTL (36h) Parameter: MY,MX,MV,ML,RGB Optional – It may be necessary to redefine the Frame Memory Write Direction. RAMRW (2Ch) Scroll Image Data VSCSAD (37h) 1st & 2nd Parameter SS A[7:0]1 Scroll Mode NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed. Ver. 1.7 145 2008.04.18 ST7787 Legend 2. Continuous Scroll Command 1st Normal Mode Parameter CASET (2Ah) Display Action &2nd Parameter XS[7:0] Mode rd 3 th & 4 Parameter XE[7:0] Sequential transfer RASET (2Bh) 1st & 2nd Parameter YS[7:0] 3rd & 4th Parameter YE[7:0] RAMRW (2Ch) Only required for non-rolling scrolling Scroll Image Data VSCSAD (37h) 1st & 2nd Parameter SSA[7:0]1 3. To Exit Vertical Scroll Mode Scroll Mode DISOFF (28h) OptionTo prevent Tearing Effect Image Display NORON (13h) / PTLON (12h) Scroll Mode OFF RAMRW (2Ch) Image Data D1[17:0],D2[17:0]… Dn[17:0] DISON (29h) NOTE: Scroll Mode can be exit by both the Normal Display Mode On (13h) and Partial Mode On (12h) commands. Ver. 1.7 146 2008.04.18 ST7787 10.1.26 TEOFF (34h): Tearing Effect Line OFF 34H Inst / Para TEOFF 1st Parameter D/CX 0 WRX RDX 1 ↑ TEOFF (Tearing Effect Line OFF) D17-8 D7 D6 D5 D4 D3 0 0 1 1 0 No Parameter D2 1 D1 0 D0 0 (Code) (34h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level Description -This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Restriction -This command has no effect when Tearing Effect output is already OFF. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value OFF OFF OFF Legend Command TE Line Output ON Parameter Display Flow Chart TE Action Mo TE Line Output OFF Sequential transfer Ver. 1.7 147 2008.04.18 ST7787 10.1.27 TEON (35h): Tearing Effect Line ON 35H Inst / Para TEON 1st Parameter D/CX 0 1 WRX RDX 1 1 ↑ ↑ D17-8 - TEON (Tearing Effect Line ON) D7 D6 D5 D4 D3 0 0 1 1 0 0 0 0 0 0 D2 1 D1 0 D0 1 (Code) (35h) 0 0 TELOM NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to turn ON the Tearing Effect output signal from the TE signal line. -This output is not affected by changing MADCTL bit ML. -The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. (“-“=Don’t Care). －When TELOM(M)=’0’: The Tearing Effect Output line consists of V-Blanking information only. tvdl Description tvdh Vertical time scale －When TELOM M=’1’: The Tearing Effect Output line consists of both V-Blanking and H-Blinking information. tvdl tvdh Vertical time scale Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Restriction -This command has no effect when Tearing Effect output is already OFF. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Tearing effect off & TELOM=0 Tearing effect off & TELOM=0 Tearing effect off & TELOM=0 Flow Chart Legend Command TE Line Output OFF Parameter Display TEON (35h) Action st 1 Parameter: (M) Mode Sequential TE Line Output ON Ver. 1.7 148 2008.04.18 ST7787 10.1.28 MADCTL (36h): Memory Data Access Control MADCTL (Memory Data Access Control) 36H Inst / Para MADCTL 1st Parameter D/CX 0 1 WRX ↑ ↑ RDX 1 1 D17-8 - D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 1 D0 0 MY MX MV ML RGB MH 0 0 (Code) (36h) NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command defines read/ write scanning direction of frame memory. -This command makes no change on the other driver status. -Bit Assignment Bit MY MX MV NAME Row Address Order Column Address Order Row/Column Exchange ML Vertical Refresh Order RGB MH DESCRIPTION These 3bits controls MCU to memory write/read direction. (See Section 9.12) LCD vertical refresh direction control ‘0’ = LCD vertical refresh Top to Bottom ‘1’ = LCD vertical refresh Bottom to Top Color selector switch control ‘0’ =RGB color filter panel, ‘1’ =BGR color filter panel LCD horizontal refresh direction control ‘0’ = LCD horizontal refresh Left to right ‘1’ = LCD horizontal refresh right to left RGB-BGR ORDER Horizontal Refresh Order ML: Vertical Refresh Order Top-Left (0,0) Memory Display Sent First Sent 2nd Sent 3rd ML=’0’ Sent Last Description Top-Left (0,0) Memory Display Sent Last ML=’1’ Sent 3rd Sent 2nd Sent First RGB: RGB-BGR Order RGB=”0” Driver IC RG R GB B SIG1 Ver. 1.7 RGB=”1” Driver IC RG GB R B SIG2 RG R GB B SIG240 SIG1 SIG2 SIG240 RGB B RGB RG RGB B RGB B RGB B RGB B LCD Panel R RG GBB RG R GB B SIG2 RG R G BB SIG240 SIG1 SIG2 SIG240 B GR BG B RGR BGR B GR B G RR B BG GR SIG1 B G RR LCD Panel 149 2008.04.18 ST7787 MH: Horizontal refresh Order Top-Left (0,0) Top-Left (0,0) Memory ML=’0’ ML=’1’ Sent First Sent 2nd Top-Left (0,0) Display Sent 3rd Sent Last Top-Left (0,0) Sent Last Sent 3rd Sent 2nd Sent First Description Memory Display Restriction D1 and D0 of the 1st parameter are set to “00” internally. Register Availability Default Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Status Power On Sequence S/W Reset H/W Reset Default Value MY=0,MX=0,MV=0,ML=0,RGB=0, MH=0 No Change MY=0,MX=0,MV=0,ML=0,RGB=0, MH=0 Flow Chart Legend Command MADCTL (36h) Parameter Display 1st Parameter: MY, MX, ML, RGB, MH Action Mode Sequential Ver. 1.7 150 2008.04.18 ST7787 10.1.29 VSCSAD (37h): Vertical Scroll Start Address of RAM 37H Inst / Para VSCSAD 1st Parameter 2nd Parameter VSCSAD (Vertical Scroll Start Address of RAM) D/CX 0 1 1 WRX ↑ ↑ ↑ RDX 1 1 1 D17-8 - D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 1 D0 1 - - - - - - - SSA8 SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 (Code) (37h) NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. -The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: -This command Start the scrolling. -Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h). When MADCTL ML= ‘0’ Example: －When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=320 and Vertical Scrolling Pointer SSA= ’3’. (Example) Top-Left (0,0) Description Scan address Memory Display 0 1 2 3 ∣ ∣ 318 319 SSA[7:0] Scroll start address G1 G2 G3 G4 | | G319 G320 When MADCTL ML = ‘1’ Example: －When Top Fixed Area= Bottom Fixed Area=00, Vertical Scrolling Area=320 and SSA= ’3’ (Example) Top-Left (0,0) Scan address Memory Display 319 318 ∣ ∣ 3 2 1 0 SSA[7:0] Scroll start address G1 G2 G3 G4 | | G319 G320 NOTE: -When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. -SSA refers to the Frame Memory scan address. -Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h)- otherwise Restriction undesirable image will be displayed on the Panel. SSA[7:0] is based on 1-line unit. -SSA[7:0] = 0000h, 0001h, 0002h, 0003h, … , 00A1h Register Availability Ver. 1.7 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes 151 2008.04.18 ST7787 Default Status Power On Sequence S/W Reset H/W Reset Default Value 0000h 0000h 0000h Flow Chart See Vertical Scrolling Definition (33h) description. Ver. 1.7 152 2008.04.18 ST7787 10.1.30 IDMOFF (38h): Idle Mode Off 38H Inst / Para IDMOFF 1st Parameter IDMOFF (Idle Mode Off) D/CX 0 WRX ↑ RDX 1 D17-8 - D7 D6 D5 0 0 1 No Parameter D4 1 D3 1 D2 0 D1 0 D0 0 (Code) (38h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to recover from Idle mode on. -There will be no abnormal visible effect on the display mode change transition. Description -In the idle off mode, 1. LCD can display 4096, 65k or 262k colors. 2. Normal frame frequency is applied. Restriction -This command has no effect when module is already in idle off mode. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Idle Mode Off Idle Mode Off Idle Mode Off Flow Chart Legend Command Idle mode on Parameter Display IDMOFF (38h) Action Mode Idle mode off Sequential transfer Ver. 1.7 153 2008.04.18 ST7787 10.1.31 IDMON (39h): Idle Mode On 39H IDMON (Idle Mode On) Inst / Para IDMOFF 1st Parameter D/CX 0 WRX ↑ RDX 1 D17-8 - D7 D6 D5 0 0 1 No Parameter D4 1 D3 1 D2 0 D1 0 D0 1 (Code) (39h) - NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to enter into Idle mode on. -There will be no abnormal visible effect on the display mode change transition. -In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command (Example) Top-Left (0,0) Mem ory Display Description Color Black Blue Red Magenta Green Cyan Yellow White R5 R4 R3 R2 R1 R0 0xxxxx 0xxxxx 1xxxxx 1xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx G5 G4 G3 G2 G1 G0 0xxxxx 0xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx 1xxxxx 1xxxxx B5 B4 B3 B4 B1 B0 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx Restriction This command has no effect when module is already in idle on mode. Register Availability Default Ver. 1.7 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Idle Mode Off Idle Mode Off Idle Mode Off 154 2008.04.18 ST7787 Legend Command Idle mode on Parameter Display Flow Chart IDMOFF (38h) Action Mode Idle mode off Sequential transfer Ver. 1.7 155 2008.04.18 ST7787 10.1.32 COLMOD (3Ah): Interface Pixel Format 3AH COLMOD (3Ah): Interface Pixel Format Inst / Para D/CX WRX ↑ COLMOD 0 ↑ 1st Parameter 1 RDX 1 1 D17-8 - D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 1 D0 0 VIPF3 VIPF2 VIPF1 VIPF0 D3 IFPF2 IFPF1 IFPF0 (Code) (3Ah) NOTE: “-” Don’t care, can be set to VDDI or DGND level This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface (IFPF) and RGB interface (VIPF). The formats are shown in the table: Others are no define and invalid IFPF[2:0] 011 101 110 3 5 6 MCU Interface Color Format 12-bit/pixel 16-bit/pixel 18-bit/pixel VIPF[3:0] 0101 0110 1110 5 6 14 RGB Interface Color Format 16-bit/pixel (1-time data transfer) 18-bit/pixel (1-time data transfer) 8-bit/pixel (3-times data transfer) Description Others are no define and invalid Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory. Note2: When RGB I/F the 12-bit/pixel don’t care Restriction There is no visible effect until the Frame Memory is written to. Status Register Availability Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Default Default Value Power On Sequence IFPF[2:0] VIPF[3:0] 0110(18-bit/Pixel) 0110(18-bit/Pixel) S/W Reset No Change No Change H/W Reset 0110(18-bit/Pixel) 0110(18-bit/Pixel) Legend 18-bit/Pixel Mode Command Parameter COLMOD (3Ah) Display Flow Chart Action 1st Parameter: P[2:0]=”111” Mode Sequential transfer 16-bit/Pixel Mode Ver. 1.7 156 2008.04.18 ST7787 10.1.33 OTP-Process (3Fh): OTP-Process 3FH Inst / Para WRX RDX D17-8 GMCTRP1 0 -↑ 1 - 0 0 1 1 st 1 1 -↑ 1 1 - 1 0 1 0 0 0 0 0 1 Parameter rd 2 Parameter -↑ D7 D6 OTP-Process D5 D4 D3 D/CX D2 D1 D0 (Code) 1 1 1 1 (3Fh) 1 0 0 0 1 INI 0 0 CAh -While EXTC is fixed to L. Description Please set INI to “1” for enable OTP rogramming -While EXTC is fixed to “L” Please set INI to “0” for disable OTP programing -If this register not using the register need be reserved. Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), VPP connect ≧7.5V. Register Availability Default Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Status Power On Sequence S/W Reset H/W Reset Default Value Not Fixed 00h 00h -----------------OTP-process (FAh) Legend Command Parameter Display Flow Chart 1st Parameter: Action Mode Sequential transfer Ver. 1.7 157 2008.04.18 ST7787 10.1.34 RDID1 (Dah): Read ID1 Value DAH RDID1 (Read ID1 Value) Inst / Para RDID1 D/CX 0 WRX 1st Parameter 1 nd 2 Parameter 1 ↑ RDX 1 D17-8 - D7 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 1 D0 0 (Code) (Dah) 1 ↑ - - - - - - - - - - 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 NOTE: “-” Don’t care, can be set to VDDI or DGND level -This read byte returns 8-bit LCD module’s manufacturer ID st -The 1 parameter is dummy data Description nd -The 2 parameter (ID17 to ID10): LCD module’s manufacturer ID. nd NOTE: See command RDDID (04h), 2 parameter. Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Power On Sequence Default Value S/W Reset FF H/W Reset FF FF Serial I/F Mode Partial I/F Mode RDID1 (DAh) RDID1 (DAh) Legend Command Host Driver Flow Chart Send 2nd parameter: ID1[7:0] Dummy Read Parameter Display Action Mode Send 2nd parameter: ID1[7:0] Ver. 1.7 158 Sequential transfer 2008.04.18 ST7787 10.1.35 RDID2 (DBh): Read ID2 Value DBH RDID2 (Read ID2 Value) Inst / Para RDID2 D/CX 0 WRX 1st Parameter 1 nd 2 Parameter 1 ↑ RDX 1 D17-8 - D7 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 1 D0 1 (Code) (DBh) 1 ↑ - - - - - - - - - - 1 ↑ - ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 NOTE: “-” Don’t care, can be set to VDDI or DGND level -This read byte returns 8-bit LCD module/driver version ID st -The 1 parameter is dummy data nd -The 2 parameter (ID26 to ID20): LCD module/driver version ID Description -Parameter Range: ID=80h to FFh rd NOTE: See command RDDID (04h), 3 parameter. Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Power On Sequence Default Value FF S/W Reset FF H/W Reset FF Flow Chart Serial I/F Mode Partial I/F Mode RDID2 (DBh) RDID2 (DBh) Legend Command Host Driver :Send 2nd parameter ID2[7:0] Dummy Read Parameter Display Action Mode Send 2nd parameter: ID2[7:0] Ver. 1.7 159 Sequential transfer 2008.04.18 ST7787 10.1.36 RDID3 (DCh): Read ID3 Value DCH RDID3 (Read ID2 Value) Inst / Para RDID3 D/CX 0 WRX 1st Parameter 1 nd 2 Parameter 1 ↑ RDX 1 D17-8 - D7 1 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 0 (Code) (DCh) 1 ↑ - - - - - - - - - - 1 ↑ - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 NOTE: “-” Don’t care, can be set to VDDI or DGND level -This read byte returns 8-bit LCD module/driver ID. st -The 1 parameter is dummy data Description -The 2nd parameter (ID37 to ID30): LCD module/driver ID. NOTE: See command RDDID (04h), 4th parameter. Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Power On Sequence Default Value FF S/W Reset FF H/W Reset FF Serial I/F Mode RDID3 (DCh) Legend Part Command RDID3 (DCh) Host Driver Flow Chart Send 2nd parameter: ID3[7:0] Dummy Read Parameter Display Action Mode Send 2nd parameter: ID3[7:0] Ver. 1.7 160 Sequential transfer 2008.04.18 ST7787 10.2.1 RGBCTR (B0h): RGB signal control RGBCTR (RGB signal control) B0H Inst / Para RGBCTR 1st Parameter D/CX 0 1 WRX ↑ ↑ RDX 1 1 D17-8 - D7 1 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0 - 0 0 0 ICM DP EP HSP VSP (Code) (B0h) NOTE: “-“ Don’t care -Set the operation status on the RGB interface. The setting becomes effective as soon as the command is received. -ICM: GRAM Write/Read frequency and data input select on the RGB interface ICM Write/ Read frequency and input data select Read cycle PCLK Internal oscillator 0 1 Write cycle PCLK SCL Symbol Name DP PCLK polarity set EP Enable polarity set HSP Hsync polarity set VSP Vsync polarity set Data input D[17:0] SDA Description Clock polarity set for RGB Interface ‘1’ = data fetched at the falling edge ‘0’ = data fetched at the rising edge ‘1’ = Low enable for RGB interface ‘0’ = High enable for RGB interface ‘1’ = High level sync clock ‘0’ = Low level sync clock ‘1’ = High level sync clock ‘0’ = Low level sync clock Restriction -If this register not using the register need be reserved. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status ICM Default Default Value DP/EP/HSP/VSP Power On Sequence S/W Reset H/W Reset ------------------ Legend RGBCTR (B0h) Command Parameter Display Action Flow Chart st 1 Parameter: ICM, DW, DP, EP, HSP, VSP Ver. 1.7 Mode Sequential transfer 161 2008.04.18 ST7787 10.2.2 FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors) B1H Inst / Para FRMCTR1 D/CX 0 WRX 1st Parameter nd 2 Parameter 3th Parameter FRMCTR1 (Frame Rate Control) D6 D5 D4 D3 D17-8 D7 D2 D1 D0 ↑ RDX 1 - 1 0 1 1 0 0 0 1 (Code) (B1h) 1 ↑ 1 - --- RTNA[6] RTNA[5] RTNA[4] RTNA[3] RTNA[2] RTNA[1] RTNA[0] - 1 ↑ 1 - --- --- --- FPA[4] FPA[3] FPA[2] FPA[1] FPA[0] - - --- --- --- BPA[4] BPA[3] BPA[2] BPA[1] BPA[0] NOTE: “-“ Don’t care -Set the frame frequency of the full colors normal mode. -The frame frequency need to meet 60Hz ±5% in this mode. RTNA[6:0] Description 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Frame Rate 90 88 86 84 82 80 78 77 75 74 72 71 70 68 67 66 65 63 62 61 60 59 59 57 57 56 55 54 53 53 52 51 51 50 49 48 48 47 47 46 45 45 44 44 RTNA[6:0] 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Frame Rate 43 43 42 42 41 41 40 40 40 39 39 38 38 37 37 37 36 36 36 35 35 35 34 34 34 33 33 33 32 32 32 32 31 31 31 31 30 30 30 30 29 29 29 29 Note: OSC output fre. Is 1.2MHz, FPA=02H and BPA=02H Ver. 1.7 162 2008.04.18 ST7787 FPA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BPA[4:0] 0 line 1 line 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines 15 lines 16 lines 17 lines 18 lines 19 lines 20 lines 21 lines 22 lines 23 lines 24 lines 25 lines 26 lines 27 lines 28 lines 29 lines 30 lines 31 lines 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 line 1 line 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines 15 lines 16 lines 17 lines 18 lines 19 lines 20 lines 21 lines 22 lines 23 lines 24 lines 25 lines 26 lines 27 lines 28 lines 29 lines 30 lines 31 lines Restriction -If this register not using the register need be reserved. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Ver. 1.7 RTNA 36h 36h 36h Power On Sequence S/W Reset H/W Reset 163 Default Value FPA 02h 02h 02h BPA 02h 02h 02h 2008.04.18 ST7787 ------------- Legend FRMCTR1 (B1h) Command Parameter Display Flow Chart 1st Parameter: 2nd Parameter: 3rd Parameter:: Action Mode Sequential transfer Ver. 1.7 164 2008.04.18 ST7787 10.2.3 FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors) B2H Inst / Para FRMCTR2 D/CX 0 WRX 1st Parameter 2nd Parameter 3th Parameter FRMCTR2 (Frame Rate Control) D7 D6 D5 D4 D3 D17-8 D2 D1 D0 (Code) ↑ RDX 1 - 1 0 1 1 0 0 1 0 (B2h) 1 ↑ 1 - --- RTNB[6] RTNB[5] RTNB[4] RTNB[3] RTNB[2] RTNB[1] RTNB[0] - 1 ↑ 1 - --- --- --- FPB[4] FPB[3] FPB[2] FPB[1] FPB[0] - 1 ↑ 1 - --- --- --- BPB[4] BPB[3] BPB[2] BPB[1] BPB[0] NOTE: “-“ Don’t care -Set the frame frequency of the Idle mode. -The frame frequency need to meet 60Hz ±5% in this mode. RTNB[6:0] Description Frame Rate 0101000 0101001 0101010 0101011 40 41 42 43 0101100 44 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 1010011 83 87 85 83 81 79 78 76 74 73 71 70 69 67 66 65 64 63 62 60 59 58 58 57 56 55 54 53 52 52 51 50 50 49 48 47 47 46 46 45 44 44 43 43 42 RTNB[6:0] 1010100 1010101 1010110 1010111 84 85 86 87 1011000 88 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 1111111 127 Frame Rate 42 41 41 40 40 40 39 39 38 38 37 37 37 36 36 36 35 35 35 34 34 34 33 33 33 32 32 32 31 31 31 31 30 30 30 30 29 29 29 29 28 28 28 28 Note: OSC output fre. Is 1.2MHz, FPA=02H and BPA=02H Ver. 1.7 165 2008.04.18 ST7787 FPB[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BPB[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 0 line 1 line 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines 15 lines 16 lines 17 lines 18 lines 19 lines 20 lines 21 lines 22 lines 23 lines 24 lines 25 lines 26 lines 27 lines 28 lines 29 lines 30 lines 31 lines Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 line 1 line 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines 15 lines 16 lines 17 lines 18 lines 19 lines 20 lines 21 lines 22 lines 23 lines 24 lines 25 lines 26 lines 27 lines 28 lines 29 lines 30 lines 31 lines Restriction -If this register not using the register need be reserved. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Ver. 1.7 Power On Sequence S/W Reset H/W Reset RTNB 38H 38H 38H 166 Default Value FPB 02H 02H 02H BPB 02H 02H 02H 2008.04.18 ST7787 ------------- Legend FRMCTR1 (B2h) Command Parameter Display Flow Chart 1st Parameter: 2nd Parameter: 3rd Parameter Action Mode Sequential transfer Ver. 1.7 167 2008.04.18 ST7787 10.2.3 FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors) B3H Inst / Para FRMCTR3 D/CX 0 WRX 1st Parameter 2nd Parameter 3rd arameter 4th Parameter 5th Parameter 6th Parameter FRMCTR3 (Frame Rate Control) D6 D5 D4 D3 D17-8 D7 D2 D1 D0 ↑ RDX 1 - 1 0 1 1 0 0 1 1 (Code) (B3h) 1 ↑ 1 - - RTNC[6] RTNC[5] RTNC[4] RTNC[3] RTNC[2] RTNC[1] RTNC[0] - 1 ↑ 1 - - - - FPC[4] FPC[3] FPC[2] FPC[1] FPC[0] 1 ↑ 1 - 1 ↑ 1 1 ↑ 1 1 ↑ 1 - - - BPC[4] BPC[3] BPC[2] BPC[1] BPC[0] --- RTND[6] RTND[5] RTND[4] RTND[3] RTND[2] RTND[1] RTND[0] - - - - FPD[4] FPD[3] FPD[2] FPD[1] FPD[0] - - - - BPD[4] BPD[3] BPD[2] BPD[1] BPD[0] NOTE: “-“ Don’t care -Set the frame frequency of the Partial mode/ full colors. -When the display is frame inversion the frame frequency need to meet 65Hz ±5% in this mode. -When the display is line inversion the frame frequency need to meet 70Hz ±5% in this mode. RTNC[6:0] Description Ver. 1.7 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 Frame Rate 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 87 85 83 81 79 77 76 74 73 71 70 68 67 66 65 63 62 61 60 59 58 57 56 55 54 54 53 52 51 51 50 49 49 48 47 47 46 45 45 44 44 43 43 42 168 RTNC[6:0] 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 Frame Rate 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 42 41 41 40 40 39 39 39 38 38 37 37 36 36 36 35 35 35 34 34 34 33 33 33 32 32 32 32 31 31 31 30 30 30 30 29 29 29 29 28 28 28 28 28 2008.04.18 - ST7787 Note: OSC output fre. Is 1.2MHz, FPA=02H and BPA=02H RTND[6:0] Frame Rate 0101000 40 0101001 41 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 42 43 44 45 46 47 48 49 50 51 52 53 54 0110111 55 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 1010000 1010001 1010010 1010011 80 81 82 83 867 85 83 81 79 77 75 74 72 71 69 68 67 66 64 63 62 61 60 59 58 57 56 55 55 54 53 52 51 51 50 49 49 48 47 47 46 45 45 44 44 43 43 42 RTND[6:0] Frame Rate 1010100 84 1010101 85 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 86 87 88 89 90 91 92 93 94 95 96 97 98 1100011 99 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 1111100 1111101 1111110 124 125 126 127 1111111 42 41 41 40 40 39 39 38 38 38 37 37 36 36 36 35 35 35 34 34 34 33 33 33 32 32 32 32 31 31 31 30 30 30 30 29 29 29 29 28 28 28 28 28 Note: OSC output fre. Is 1.2MHz, FPA=02H and BPA=02H Restriction -If this register not using the register need be reserved. Register Availability Ver. 1.7 Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes 169 2008.04.18 ST7787 Status Default Power On Sequence S/W Reset H/W Reset RTNC 36h 36h 36h FPC 02h 02h 02h Default Value BPC RTND 02h 38h 02h 38h 02h 38h FPD 02h 02h 02h BPD 02h 02h 02h ------------- Legend FRMCTR1 (B3h) Command Parameter Display Flow Chart Ver. 1.7 1st Parameter: 2nd Parameter: 3rd Parameter: . . 6th Parameter: Action Mode Sequential transfer 170 2008.04.18 ST7787 10.2.5 INVCTR (B4h): Display Inversion Control B4H Inst / Para INVCTR D/CX 0 1st Parameter 1 WRX INVCTR (Display Inversion Control) D17-8 D7 D6 D5 D4 D3 D2 1 0 1 1 0 1 - RDX 1 ↑ ↑ 1 - 0 0 0 0 0 NLA D1 0 D0 0 (Code) (B4h) NLB NLC 02h NOTE: “-“ Don’t care -Display Inversion mode control -NLA: Inversion setting in full colors normal mode (Normal mode on) NLA 0 1 Inversion setting in full Colors normal mode Line Inversion Frame Inversion -NLB: Inversion setting in Idle mode (Idle mode on) Description NLB 0 1 Inversion setting in Idle mode Line Inversion Frame Inversion -NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off) NLC 0 1 Inversion setting in full Colors partial mode Line Inversion Frame Inversion Restriction -If this register not using the register need be reserved. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default NLA 0d 0d 0d Power On Sequence S/W Reset H/W Reset NLB 1d 1d 1d Default Value NLC 0d 0d 0d B4h 02h 02h 02h ------------- Legend INVCTR (B4h) Command Parameter Flow Chart ] Display 1st Parameter: Action NLA, NLB, NLC Mode Sequential transfer Ver. 1.7 171 2008.04.18 ST7787 10.2.6 RGBBPCTR (B5h): RGB Interface Blanking Porch setting B5H Inst / Para RGBBPCTR D/CX 0 WRX ↑ RDX 1 RGBPSET (RGB Interface Blanking Porch setting) D17-8 D7 D6 D5 D4 D3 D2 D1 1 0 1 1 0 1 0 1st Parameter 1 ↑ 1 - --- --- --- --- VFP[3] VFP[2] 2nd Parameter 1 ↑ 1 - --- --- --- --- VBP[3] VBP[2] 3rd Parameter 1 ↑ 1 --- --- --- --- HFP[3] HFP[2] HFP[1] HFP[0] 4th Parameter 1 ↑ 1 --- --- --- --- HBP[3] HBP[2] HBP[1] HBP[0] D0 1 (Code) (B5h) VFP[1] VFP[0] - VBP[1] VBP[0] - NOTE: “-“ Don’t care -Set the blanking porch in the RGB interface Description -The detail settings are designed by driver maker. Restriction -If this register not using the register need be reserved. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Status Default Power On Sequence S/W Reset H/W Reset VFP[3:0] 00H 00H 00H Default Value VBP[3:0] HFP[3:0] 02H 09H 02H 09H 02H 09H ------------- HBP[3:0] 09H 09H 09H Legend Command RGBBPCTR1 (B5h) Parameter Display Flow Chart 1st Parameter: 2nd Parameter: 3rd Parameter: 4th Parameter: Action Mode Sequential transfer Ver. 1.7 172 2008.04.18 ST7787 10.2.7 DISSET5 (B6h): Display Function set 5 DISSET (Display Function set 5) B6H Inst / Para DISSET5 D/CX 0 WRX 1st Parameterr 2nd Paramete D17-8 - D7 D6 D5 D4 D3 D2 D1 D0 ↑ RDX 1 1 0 1 1 0 1 1 0 (Code) (B6h) 1 ↑ 1 --- NO1 NO0 STD1 STD0 EQ1 EQ0 02h ↑ 1 - --- 1 --- --- --- --- PTG1 PTG0 PT1 PT0 02h NOTE: “-“ Don’t care -1st parameter: Set output waveform relation. -NO[1:0]: Set the amount of non-overlap of the gate output NO[1:0] 00 01 10 11 0 1 2 3 Amount of non-overlap of the gate output Refer the Internal oscillator Refer the PCLK 2 clock cycle 8 clock cycle 4 clock cycle 16 clock cycle 8 clock cycle 32 clock cycle 10 clock cycle 40 clock cycle -SDT[1:0]: Set delay amount from gate signal falling edge of the source output. SDT[1:0] 00 01 10 11 0 1 2 3 Amount of non-overlap of the gate output Refer the Internal oscillator Refer the PCLK 1 clock cycle 4 clock cycle 2 clock cycle 8 clock cycle 3 clock cycle 12 clock cycle 4 clock cycle 16 clock cycle -EQ[1:0]: Set the Equalizing period EQ[1:0] 00 01 10 11 0 1 2 3 Amount of non-overlap of the gate output Refer the Internal oscillator Refer the PCLK 0 clock cycle 0 clock cycle 4 clock cycle 16 clock cycle 6 clock cycle 24 clock cycle 8 clock cycle 32 clock cycle Gate Non-overlap period Gn Description Gn+1 Sn VCOM Delay time for source output EQ period -2nd parameter: Set the output waveform in non-display area. -PTG[1:0]: Determine gate output in a non-display area in the partial mode PTG[1:0] 00 01 10 11 Gate output in a non-display area Normal scan Fix on VGL Fix on VGL Fix on VGL 0 1 2 3 -PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode PT[1:0] 00 01 10 11 0 1 2 3 Source output on non-display area Positive Negative V63 V0 V0 V63 AGND AGND Hi-z Hi-z VCOM output on non-display area Positive Negative VCOML VCOMH VCOML VCOMH AGND AGND AGND AGND Restriction -If this register not using the register need be reserved. Ver. 1.7 173 2008.04.18 ST7787 Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence S/W Reset H/W Reset NO[1:0] 00 00 00 STD[1:0] 00 00 00 Default Value EQ[1:0] PTG[1:0] 10 00 10 00 10 00 PT[1:0] 10 10 10 ------------------ Legend DISSET5 (B6h) Command Parameter Display Flow Chart Ver. 1.7 : st Parameter 1 NO[1:0], STD[1:0], EQ[1:0] 2nd Parameter: PTG[1:0], PT[1:0] 174 Action Mode Sequential transfer 2008.04.18 ST7787 10.2.8 VSYNCOUT (BCh): BCH Inst / Para VSYNCOUT st 1 Parameter VSYNCOUT D/CX 0 WRX ↑ RDX 1 D17-8 - D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1 1 0 0 (Code) (BCh) No Parameter NOTE: “-“ Don’t care This command comes off external VSYNC a display synchronous. Description Operation shifts to an internal synchronous mode by the VSYNCOUT command while external VSYNC is synchronizing. VSYNCOUT command is recognized frame synchronously. The shift operation becomes the same for the VSYNCOUT command issued within the range of the inside of the figure. Restriction -If this register not using the register need be reserved. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence S/W Reset H/W Reset OFF OFF OFF Legend Command Exxternal VSYNC enable Parameter Display Flow Chart VSYNCOUT(BCh) Action Mode Sequential transfer External VSYNC disable Ver. 1.7 175 2008.04.18 ST7787 10.2.9 VSYNCIN (BDh): BDH Inst / Para VSYNCOUT st 1 Parameter VSYNCIN D/CX 0 WRX ↑ RDX 1 D17-8 - D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1 1 0 1 (Code) (BDh) No Parameter NOTE: “-“ Don’t care -The frame to which the command is input finishes sending data by an internal vertical synchronizing signal. Afterward, an external vertical synchronizing signal is waiting for at the rest period. The operation after that becomes external synchronous. Operation enters the rest period when the transmission of data ends for one frame while the external is synchronizing. Description wait: Synchronous waiting period. Operation is external VSYNC perceives “L” level of the VSYNC signal and internal operate and after synchronization t, scans the display for one frame. External VSYNC signal through TE pin. Operation enters the synchronous waiting period again when the display sacanning ends. Restriction -If this register not using the register need be reserved. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence S/W Reset H/W Reset OFF OFF OFF Legend Command Exxternal VSYNC disable Parameter Display Flow Chart VSYNCOUT(BDh) Action Mode Sequential transfer External VSYNC enable Ver. 1.7 176 2008.04.18 ST7787 10.2.10 PWCTR1 (C0h): Power Control 1 C0H Inst / Para PWCTR1 D/CX 0 1st Parameter 1 WRX ↑ ↑ RDX 1 D17-8 - D7 1 1 - 0 PWCTR1 (Power Control 1) D6 D5 D4 D3 1 0 0 0 0 0 VRH4 VRH3 D2 0 D1 0 D0 0 (Code) (C0h) VRH2 VRH1 VRH0 NOTE: “-“ Don’t care -Set the GVDD and voltage Description VRH[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GVDD 5.00 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 3.75 3.70 3.65 3.60 3.55 3.50 3.45 3.40 3.35 3.25 3.00 -If this register not using the register need be reserved. Restriction -The deviation value of GVDD between with Measurement and Specification: Max <=50mV -The deviation value of VCI1 between with Measurement and Specification: Max <= 1% Status Register Availability Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Ver. 1.7 Availability Normal Mode On, Idle Mode Off, Sleep Out Power On Sequence S/W Reset H/W Reset Default Value LCM1, LCM0 = “01” TR LC Type VRH[4:0] 10000 10000 10000 177 2008.04.18 ST7787 ------------------ Legend PECTR1 (C0h) Command Parameter Display Flow Chart Action : st Parameter 1 VRH[4:0] Mode Sequential transfer Ver. 1.7 178 2008.04.18 ST7787 10.2.11 PWCTR2 (C1h): Power Control 2 C1H Inst / Para PWCTR2 D/CX 0 WRX 1st Parameter PWCTR2 (Power Control 2) D6 D5 D4 D3 1 0 0 0 ↑ RDX 1 D17-8 - D7 1 1 ↑ 1 VGH3 VGH2 VGH1 VGH0 2 Parameter 1 NOTE: “-“ Don’t care ↑ 1 - -- -- -- -- nd D2 0 D1 0 D0 1 VGL3 VGL2 VGL1 VGL0 -- GOT2 GOT1 GOT0 (Code) (C1h) -Set the AVDD, VCL, VGH and VGL supply power level VGH[2:0]/VGL[2:0] Description - VGH VGL 0000 0 X -5.0 0001 1 X -5.5 0010 2 X -6.0 0011 3 X -6.5 0100 4 X -7.0 0101 5 12 -9.0 0110 6 12.5 -9.5 0111 7 13.0 -10.0 1000 8 13.5 -10.5 1001 9 14.0 -11.0 1010 10 14.5 -11.5 1011 11 15.0 -12.0 1100 12 15.5 -12.5 1101 13 16.0 -13.0 1110 14 16.5 -13.5 1111 15 x -14.0 Unit(V) GOT [2:0]: Define VGH2 level period. GOT[2:0] UC mode OSC clk RGB pixel clk 000 0 0 001 4 16 010 6 24 011 9 36 100 11 44 101 14 56 110 16 64 111 19 76 Note: When VCI1=2.5V, VDD=2.5V,Set-up cycle 1 effective=95%, Set-up cycle 2 effective=98%, -If this register not using the register need be reserved. Restriction -The deviation value of VGH/ VGL between with Measurement and Specification: Max: VGH-VGL<=1V -VGH-VGL <= 32V Ver. 1.7 179 2008.04.18 ST7787 Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence S/W Reset H/W Reset GOT[2:0] 00h 00h 00h Default Value VGH[3:0] C0h C0h C0h VGL[3:0] 80h 80h 80h ------------------ Legend PWCTR2 (C1h) Command Parameter Display Flow Chart Action : st Parameter 1 .2nd Parameter Mode Sequential transfer Ver. 1.7 180 2008.04.18 ST7787 10.2.12 PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors) C2H Inst / Para PWCTR3 D/CX WRX RDX D17-8 0 ↑ 1 - D7 1 PWCTR3 (Power Control 3) D6 D5 D4 D3 1 0 0 0 D2 0 D1 1 D0 0 1st Parameter 1 ↑ 1 - 0 0 0 0 0 APA2 APA1 APA0 2nd Parameter 1 ↑ 1 - STEP1A _SEL3 STEP1A _SEL0 LDO5 _SEL0 STEP1AP _SEL0 0 3rd Parameter STEP1A _SEL1 LDO5 _SEL1 STEP1AP _SEL1 - - STEP2A _SEL2 STEP4A _SEL2 STEP2PA _SEL2 STEP4PA _SEL2 STEP2A _SEL1 STEP4A _SEL1 STEP2PA _SEL1 STEP4PA _SEL1 STEP2A _SEL0 STEP4A _SEL0 STEP2PA _SEL0 STEP4PA _SEL0 1 ↑ 1 - 1 th 1 ↑ 1 - - STEP1A _SEL2 LDO5 _SEL2 STEP1AP _SEL2 th 1 ↑ 1 - - - 4 Parameter 5 Parameter ----- (Code) (C2h) NOTE: “-“ Don’t care -Set the amount of current in Operational amplifier in normal mode/full colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. APA[2:0] 000 001 010 011 100 101 110 111 Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved 0 1 2 3 4 5 6 7 -Set the Booster circuit Step-up cycle in Normal mode/ full colors. Step1A_SEL[3:0] Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 LDO5 [2:0] 000 C1S(V) 0 4.5 0000 0 001 1 4.6 0001 1 010 2 4.7 0010 2 011 3 4.8 0011 3 100 4 4.9 0100 4 101 5 5.0 0101 5 110 6 5.1 0110 6 111 7 X 0111 7 Unit(V) 1000 8 1001 9 1010 10 Description 1011 11 1100 12 1101 13 1110 14 1111 15 Unit:KHz Note:While Step1A_SEL3 setting to ‘0”, the charge pump circuit is selected to “Single mode”. On the contray to “Dual mode”. Step2A_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 2 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step4A_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Unit:KHz Ver. 1.7 181 2008.04.18 ST7787 1. Set the Booster circuit Step-up cycle during porch area in Normal mode/ full colors. Step1PA_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step2PA_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 2 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Unit:KHz Step4PA_SEL[2:0] Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Unit:KHz Note: BCLK is Clock frequency for Booster circuit Restriction -If some parameter of the register not use the register need to be reserved. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence S/W Reset H/W Reset Default Value APA[2:0] Step1A _SEL[3:0] Step2A _SEL[2:0] Ste4A _SEL[2:0] LDO5 _SEL[2:0] Step1PA _SEL[3:0] Step2PA _SEL[2:0] Ste4PA _SEL[2:0] 01h 01h 01h 0Bh 0Bh 0Bh 03h 03h 03h 03h 03h 03h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Legend ------------------ Command PWCTR3 (C2h) Parameter Display Flow Chart Ver. 1.7 1st Parameter: APA[2:0] 2nd Parameter: Step1A[3:0] & Step2A[2:0] 3rd Parameter LDO5[2:0] &Step2A[2:0] 4th Parameter Step1PA[2:0] & Step2PA[2:0] 5th Parameter Step4PA[2:0] Action Mode Sequential transfer 182 2008.04.18 ST7787 10.2.13 PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors) C3H Inst / Para PWCTR4 D/CX WRX RDX D17-8 0 ↑ 1 - 1st Parameter 2nd Parameter 1 1 ↑ ↑ 1 1 3rd Parameter 1 ↑ 1 4 Parameter 1 ↑ 1 5th Parameter 1 ↑ 1 th - D7 1 PWCTR4 (Power Control 4) D6 D5 D4 D3 1 0 0 0 0 0 0 0 STEP1B _SEL3 STEP1B _SEL2 STEP1B _SEL1 STEP1B _SEL0 STEP1PB STEP1PB _SEL2 _SEL1 0 0 STEP1PB _SEL0 D2 0 D1 1 D0 1 APB2 APB1 APB0 STEP2B _SEL2 STEP4B _SEL2 STEP2PB _SEL2 STEP4PB _SEL2 STEP2B _SEL1 STEP4B _SEL1 STEP2PB _SEL1 STEP4PB _SEL1 STEP2B _SEL0 STEP4B _SEL0 STEP2PB _SEL0 STEP4PB _SEL0 (Code) (C3h) NOTE: “-“ Don’t care -Set the amount of current in Operational amplifier in Idle mode/8 colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. APB[2:0] 000 001 010 011 100 101 110 111 Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved 0 1 2 3 4 5 6 7 -Set the Booster circuit Step-up cycle in Idle mode/8 colors. Step1B_SEL[3:0] Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 Description 1011 11 1100 12 1101 13 1110 14 1111 15 Unit:KHz Note:While Step1B_SEL3 setting to ‘0”, the charge pump circuit is selected to “Single mode”. On the contray to “Dual mode”. Step2B_SEL[2:0] 000 001 010 011 100 101 110 111 Ver. 1.7 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 2 OSC/1024 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 183 Step4B_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 2008.04.18 ST7787 1. Set the Booster circuit Step-up cycle during porch area in Idle mode. Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step1PB_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step2PB_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 2 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Unit:KHz Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step4PB_SEL[2:0] 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Unit:KHz Note: BCLK is Clock frequency for Booster circuit Restriction -If some parameter of the register not use the register need to be reserved. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence S/W Reset H/W Reset APB[2:0] Step1B _SEL[3:0] Step2B _SEL[2:0] Ste4B _SEL[2:0] Step1PB _SEL[3:0] Step2PB _SEL[2:0] Ste4PB _SEL[2:0] 01h 01h 01h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h ------------------ Legend PWCTR4 (C3h) Command Parameter Display Flow Chart Ver. 1.7 Action 1st Parameter: APB[2:0] 2nd Parameter: Step1B[3:0] & Step2B[2:0] 3rd Parameter Step2B[2:0] 4th Parameter Step1PAB2:0] & Step2PB[2:0] 5th Parameter Step4PB[2:0] Mode Sequential transfer 184 2008.04.18 ST7787 10.2.14 PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors) C4H Inst / Para PWCTR5 D/CX 0 1st Parameter 2nd Parameter 1 1 rd WRX th D17-8 - ↑ 1 1 - ↑ 1 - ↑ ↑ 1 3 Parameter RDX 1 PWCTR5 (Power Control 5) D7 D6 D5 D4 D3 1 1 0 0 0 0 0 0 0 STEP1C STEP1C STEP1C STEP1C _SEL3 _SEL2 _SEL1 _SEL0 - 4 Parameter 1 ↑ 1 - - 5th Parameter 1 ↑ 1 - - -- - - STEP1PC STEP1PC STEP1PC _SEL2 _SEL1 _SEL0 - - - 0 0 - D2 1 D1 0 D0 0 APC2 APC1 APC0 STEP2C _SEL2 STEP4C _SEL2 STEP2PC _SEL2 STEP4PC _SEL2 STEP2C _SEL1 STEP4C _SEL1 STEP2PC _SEL1 STEP4PC _SEL1 STEP2C _SEL0 STEP4C _SEL0 STEP2PC _SEL0 STEP4PC _SEL0 (Code) (C4h) 00h NOTE: “-“ Don’t care -Set the amount of current in Operational amplifier in Partial mode/ full-colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. APC[2:0] 000 001 010 011 100 101 110 111 Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved 0 1 2 3 4 5 6 7 -Set the Booster circuit Step-up cycle in Partial mode/ full-colors. Note: BCLK is Clock frequency for Booster circuit Step1C_SEL[3:0] Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 Description 1011 11 1100 12 1101 13 1110 14 1111 15 Unit:KHz Note:While Step1B_SEL3 setting to ‘0”, the charge pump circuit is selected to “Single mode”. On the contray to “Dual mode”. Step2C_SEL[2:0] 000 001 010 011 100 101 110 111 Ver. 1.7 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 2 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 185 Step4C_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 2008.04.18 ST7787 1. Set the Booster circuit Step-up cycle during porch area in Partial mode/ full-colors. Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step1PC_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step2PC_SEL[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 2 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Unit:KHz Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step4PC_SEL[2:0] 000 001 010 011 100 101 110 111 Unit:KHz 0 1 2 3 4 5 6 7 Note: BCLK is Clock frequency for Booster circuit Restriction -If some parameter of the register not use the register need to be reserved. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence S/W Reset H/W Reset APC[2:0] Step1C _SEL[3:0] Step2C _SEL[2:0] Ste4C _SEL[2:0] Step1PC _SEL[3:0] Step2PC _SEL[2:0] Ste4PC _SEL[2:0] 01h 01h 01h 0Bh 0Bh 0Bh 03h 03h 03h 03h 03h 03h 00h 00h 00h 00h 00h 00h 00h 00h 00h ------------------ Legend PWCTR4 (C4h) Command Parameter Display Flow Chart Ver. 1.7 Action 1st Parameter: APB[2:0] 2nd Parameter: Step1B[3:0] & Step2B[2:0] 3rd Parameter Step2B[2:0] 4th Parameter Step1PAB2:0] & Step2PB[2:0] 5th Parameter Step4PB[2:0] Mode Sequential transfer 186 2008.04.18 ST7787 10.2.15 VMCTR1 (C5h): VCOM Control 1 C5H Inst / Para VMCTR1 D/CX WRX RDX D17-8 D7 0 ↑ 1 1 1st Parameter 1 ↑ 1 - D6 1 D0 1 VMH_R5 VMH_R4 VMH_R3 VMH_R2 VMH_R1 VMH_R0 VMH _IDMON5 VMH _IDMON4 VMH _IDMON3 VMH _IDMON2 VMH _IDMON1 VMH _IDMON0 ---- ---- ---- ---- ---- ---- 1 ↑ 1 - 0 3 Parameter 1 ↑ 1 - nVM0 --- rd D1 0 VMH_R6 Parameter 2 D2 1 0 VMH _IDMON6 nd VMCTR1 (VCOM Control 1) D5 D4 D3 0 0 0 (Code) (C5h) NOTE: “-“ Don’t care -Set VCOMH Voltage in normal mode/full colors. Description VMH[6:0] 0000000 0 0000001 1 0000010 2 0000011 3 0000100 4 0000101 5 0000110 6 0000111 7 0001000 8 0001001 9 0001010 10 0001011 11 0001100 12 0001101 13 0001110 14 0001111 15 0010000 16 0010001 17 0010010 18 0010011 19 0010100 20 0010101 21 0010110 22 0010111 23 0011000 24 0011001 25 0011010 26 VCOMH 2.500 2.525 2.550 2.575 2.600 2.625 2.650 2.675 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050 3.075 3.100 3.125 3.150 VMH[6:0] 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 VCOMH 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 3.175 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 3.500 3.525 3.550 3.575 3.600 3.625 3.650 3.675 3.700 3.725 3.750 3.775 3.800 3.825 VMH[6:0] 0110110 54 0110111 55 0111000 56 0111001 57 0111010 58 0111011 59 0111100 60 0111101 61 0111110 62 0111111 63 1000000 64 1000001 65 1000010 66 1000011 67 1000100 68 1000101 69 1000110 70 1000111 71 1001000 72 1001001 73 1001010 74 1001011 75 1001100 76 1001101 77 1001110 78 1001111 79 1010000 80 VCOMH 3.850 3.875 3.900 3.925 3.950 3.975 4.000 4.025 4.050 4.075 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 4.325 4.350 4.375 4.400 4.425 4.450 4.475 4.500 VMH[6:0] 1010001 81 1010010 82 1010011 83 1010100 84 1010101 85 1010110 86 1010111 87 1011000 88 1011001 89 1011010 90 1011011 91 1011100 92 1011101 93 1011110 94 1011111 95 1100000 96 1100001 97 1100010 98 1100011 99 1100100 100 1100101 101 | 1111111 127 VCOMH 4.525 4.550 4.575 4.600 4.625 4.650 4.675 4.700 4.725 4.750 4.775 4.800 4.825 4.850 4.875 4.900 4.925 4.950 4.975 5.000 Not Permitted -When the VCOM circuit use VOCMH + VCOMAC -The VCOML is generated from VCOMH-VCOMAC -VcomH voltage also can be adjusted by VMH_IDOMON[6:0] register in Idle mode/8 colors. VMH _IDOMON[6:0] 0000000 0 0000001 1 0000010 2 0000011 3 0000100 4 0000101 5 0000110 6 0000111 7 0001000 8 0001001 9 0001010 10 0001011 11 0001100 12 0001101 13 0001110 14 0001111 15 0010000 16 0010001 17 0010010 18 0010011 19 0010100 20 0010101 21 0010110 22 Ver. 1.7 VCOMH 2.500 2.525 2.550 2.575 2.600 2.625 2.650 2.675 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050 VMH _IDOMON[6:0] 0011011 27 0011100 28 0011101 29 0011110 30 0011111 31 0100000 32 0100001 33 0100010 34 0100011 35 0100100 36 0100101 37 0100110 38 0100111 39 0101000 40 0101001 41 0101010 42 0101011 43 0101100 44 0101101 45 0101110 46 0101111 47 0110000 48 0110001 49 VCOMH 3.175 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 3.500 3.525 3.550 3.575 3.600 3.625 3.650 3.675 3.700 3.725 187 VMH _IDOMON[6:0] 0110110 54 0110111 55 0111000 56 0111001 57 0111010 58 0111011 59 0111100 60 0111101 61 0111110 62 0111111 63 1000000 64 1000001 65 1000010 66 1000011 67 1000100 68 1000101 69 1000110 70 1000111 71 1001000 72 1001001 73 1001010 74 1001011 75 1001100 76 VCOMH 3.850 3.875 3.900 3.925 3.950 3.975 4.000 4.025 4.050 4.075 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 4.325 4.350 4.375 4.400 VMH _IDOMON[6:0] 1010001 81 1010010 82 1010011 83 1010100 84 1010101 85 1010110 86 1010111 87 1011000 88 1011001 89 1011010 90 1011011 91 1011100 92 1011101 93 1011110 94 1011111 95 1100000 96 1100001 97 1100010 98 1100011 99 1100100 100 1100101 101 | 1111111 127 VCOMH 4.525 4.550 4.575 4.600 4.625 4.650 4.675 4.700 4.725 4.750 4.775 4.800 4.825 4.850 4.875 4.900 4.925 4.950 4.975 5.000 Not Permitted 2008.04.18 ST7787 0010111 0011000 0011001 0011010 23 24 25 26 3.075 3.100 3.125 3.150 0110010 0110011 0110100 0110101 50 51 52 53 3.750 3.775 3.800 3.825 1001101 1001110 1001111 1010000 77 78 79 80 4.425 4.450 4.475 4.500 -Set VCOMH Voltage in normal mode/full colors. -When nVM0=1, VcomH voltage can be adjusted by VMH_R[6:0] register. -When nVM0=0, VcomH rogram will be setted by OTP register value. -If this register not using the register need be reserved. Restriction -The deviation value of VCOMH/VCOML between with Measurement and Specification: Max<=30mV -The deviation value of VCOMAC between with Measurement and Specification: Max <=50mV Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence S/W Reset H/W Reset nVM0=0, VMH_R[6:0] 28h 28h 28h Default Value nVM0=0, VMH_COLOR8M[6:0] 28h 28h 28h Legend PWCTR4 (C5h) Command Parameter Display Flow Chart Ver. 1.7 1st Parameter: VMH_R[6:0] 2nd Parameter: VMH_COLOR8M[6:0] 3rd Parameter nVM0 Action Mode Sequential transfer 188 2008.04.18 ST7787 10.2.16 VMCTR2 (C6h): VCOM Control 2 C6H Inst / Para D/CX WRX RDX D17-8 D7 VMCTR2 (VCOM Control 2) D6 D5 D4 D3 VMCTR2 0 ↑ 1 - 1 1 1st Parameter 1 ↑ 1 - 0 0 2nd Parameter 1 ↑ 1 - 0 0 0 0 0 D2 D1 D0 (Code) 1 1 0 (C6h) VMA5 VMA4 VMA3 VMA2 VMA1 VMA0 VMA VMA VMA VMA VMA VMA _IDMON5 _IDMON4 _IDMON3 _IDMON2 _IDMON1 _IDMON0 NOTE: “-“ Don’t care -Set VCOMAC Voltage in normal mode/full colors. VMA[5:0] 000000 0 000001 1 000010 2 000011 3 000100 4 000101 5 000110 6 000111 7 001000 8 001001 9 001010 10 001011 11 001100 12 001101 13 001110 14 001111 15 VCOMAC 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400 4.450 4.500 4.550 4.600 4.650 4.700 4.750 VMA[5:0] 010000 16 010001 17 010010 18 010011 19 010100 20 010101 21 010110 22 010111 23 011000 24 011001 25 011010 26 011011 27 011100 28 011101 29 011110 30 011111 31 VCOMAC 4.800 4.850 4.900 4.950 5.000 5.050 5.100 5.150 5.200 5.250 5.300 5.350 5.400 5.450 5.500 5.550 VMA[5:0] 100000 32 100001 33 100010 34 100011 35 100100 36 100101 37 100110 38 100111 39 101000 40 101001 41 | 111111 63 VCOMAC 5.600 5.650 5.700 5.750 5.800 5.850 5.900 5.950 6.000 Not Permitted Description -Set VCOMAC Voltage in Idle mode/8 colors. VMA _IDMON[5:0] 000000 0 000001 1 000010 2 000011 3 000100 4 000101 5 000110 6 000111 7 001000 8 001001 9 001010 10 001011 11 001100 12 001101 13 001110 14 001111 15 Restriction Register Availability Ver. 1.7 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400 4.450 4.500 4.550 4.600 4.650 4.700 4.750 VMA _IDMON[5:0] 010000 16 010001 17 010010 18 010011 19 010100 20 010101 21 010110 22 010111 23 011000 24 011001 25 011010 26 011011 27 011100 28 011101 29 011110 30 011111 31 VCOMAC 4.800 4.850 4.900 4.950 5.000 5.050 5.100 5.150 5.200 5.250 5.300 5.350 5.400 5.450 5.500 5.550 VMA _IDMON[5:0] 100000 32 100001 33 100010 34 100011 35 100100 36 100101 37 100110 38 100111 39 101000 40 101001 41 | 111111 63 VCOMAC 5.600 5.650 5.700 5.750 5.800 5.850 5.900 5.950 6.000 Not Permitted -If this register not use the register need be reserved. -The deviation value of VCOMAC between with Measurement and Specification: Max <=50mV Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default VCOMAC Power On Sequence S/W Reset H/W Reset Default Value LCM1, LCM0 = “01” TR LC Type LCM1, LCM0 = “01” TR LC Type VMA[6:0] VMA_IDMON[5:0] 06h 00h 06h 00h 06h 00h 189 2008.04.18 ST7787 ------------------ Legend VMCTR4 (C6h) Command Parameter Display Flow Chart Action 1st Parameter: VMA[5:0] 2nd Parameter: VMA_IDMON[5:0] Ver. 1.7 Mode Sequential transfer 190 2008.04.18 ST7787 10.2.17 WRID1 (D0h): OTP ID1 set LCM version code D0H OTP ID1 set LCM version code Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 (Code) OTP-read 0 ↑ 1 - 1 1 0 1 0 0 0 0 (D0h) st 1 ↑ 1 - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 1 Parameter -OTP ID1 set the LCM version code Description -If this register not using the register need be reserved. Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), VPP connect 7.5V. Register Availability Default Status Availability Normal Mode On, Idle Mode Ooff, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode Off, Idle Mode On, Sleep Out Yes Sleep In No Status Default Value Power On Sequence S/W Reset H/W Reset N/A N/A N/A Legend Command Parameter Display Flow Chart Action Mode Sequential transfer Ver. 1.7 191 2008.04.18 ST7787 10.2.18 WRID2 (D1h): OTP ID2 set LCM version code OTP ID2 set LCM version code D1H Inst / Para D/CX WRX RDX OTP-read 0 ↑ 1 - 1 1 0 1 0 0 1st Parameter 1 ↑ 1 - 1 ID26 ID25 ID24 ID23 ID22 D17-8 D7 D6 D5 D4 D3 D2 D1 D0 (Code) 0 1 (D1h) ID21 ID20 -OTP ID2 set the LCM version code Description -If this register not using the register need be reserved. Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), Vpp connect 7.5V. Register Availability Default Status Availability Normal Mode On, Idle Mode Ooff, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode Off, Idle Mode On, Sleep Out Yes Sleep In No Status Default Value Power On Sequence S/W Reset H/W Reset N/A N/A N/A Legend Command Parameter Display Flow Chart Action Mode Sequential transfer Ver. 1.7 192 2008.04.18 ST7787 10.2.19 WRID3 (D2h): OTP ID3 set Project code OTP ID3 set LCM version code D2H Inst / Para D/CX WRX RDX OTP-read 0 ↑ 1 - 1 1 0 1 0 0 1st Parameter 1 ↑ 1 - ID37 ID36 ID35 ID34 ID33 ID32 D17-8 D7 D6 D5 D4 D3 D2 D1 D0 (Code) 1 0 (D2h) ID31 ID30 -OTP ID3 set the project code Description -If this register not using the register need be reserved. Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), VPP connect 7.5V. Register Availability Default Status Availability Normal Mode On, Idle Mode Ooff, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode Off, Idle Mode On, Sleep Out Yes Sleep In No Status Default Value Power On Sequence S/W Reset H/W Reset N/A N/A N/A Legend Command Parameter Display Flow Chart Action Mode Sequential transfer Ver. 1.7 193 2008.04.18 ST7787 10.2.20 OTP-Load (Deh): OTP read command DEH Inst / Para D/CX WRX RDX OTP-read 0 ↑ 1 - 1 1 0 1 1 1 1 0 (Deh) 1st Parameter 1 ↑ 1 - 0 1 1 1 0 1 0 1 (75H) D17-8 D7 D6 OTP-Load D5 D4 D3 D2 D1 D0 (Code) -Read OTP value Description After OTP rogramming, IC will download the OTP value. If you change the VcomH register, you can execute Deh command to re-download OTP. Restriction -If this register not using the register need be reserved. Register Availability Default Status Availability Normal Mode On, Idle Mode Ooff, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode Off, Idle Mode On, Sleep Out Yes Sleep In No Status Default Value Power On Sequence S/W Reset H/W Reset 75h 75h 75h Legend Command Parameter Display Flow Chart Action Mode Sequential transfer Ver. 1.7 194 2008.04.18 ST7787 10.2.21 OTP-Prog (DFh): OTP Programimng command DFH Inst / Para OTP-read D/CX 0 WRX 1st Parameter 2nd Parameter 3rd Parameter 4rd Parameter 5rd Parameter 1 1 1 1 1 OTP-Prog D5 D4 D17-8 - D7 D6 D3 D2 D1 D0 ↑ RDX 1 1 1 0 1 1 1 1 0 ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 - 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1 1 0 0 1 0 (Code) (DFh) (CAH) (00H) (AAH) (A5H) (5AH) - OTP download Description -Set the VcomH voltage in normal mode/full colors and Idle mode/8 colors. -Set the VcomAC voltage in normal mode/full colors and Idle mode/8 colors. -If this register not using the register need be reserved. Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), VPP connect 7.5V. Register Availability Default Status Availability Normal Mode On, Idle Mode Ooff, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode Off, Idle Mode On, Sleep Out Yes Sleep In No Status Default Value Power On Sequence S/W Reset H/W Reset No change No change No change Legend Command Parameter Display Flow Chart Action Mode Sequential transfer Ver. 1.7 195 2008.04.18 ST7787 10.2.22 GMCTRP1 (E0h): Gamma (‘+’polarity) Correction Characteristics Setting E0H Inst / Para GMCTRP0 (Gamma ‘+’polarity Correction Characteristics Setting) D7 D6 D5 D4 D3 D2 D1 D0 D/CX WRX RDX D17-8 GMCTRP1 0 -↑ 1 - 1 1 1 st 1 1 1 1 1 1 1 1 1 1 1 1 1 -↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 - MVA_EN - - - 1 Parameter nd 2 Parameter rd 3 Parameter th 4 Parameter th 5 Parameter th 6 Parameter th 7 Parameter th 8 Parameter th 9 Parameter th 10 Parameter th 11 Parameter th 12 Parameter th 13 Parameter -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ Register Group Negative Polarity High level adjustment RFP0[3:0] PKP0[3:0] PKP1[4:0] PKP2[4:0] PKP3[4:0] PKP4[4:0] Description Mid level adjustment PKP5[4:0] PKP6[4:0] PKP7[4:0] PKP8[3:0] RFP1[3:0] OSP1[2:0] Low level adjustment OSP0[4:0] 0 0 0 0 (Code) 0 (E0h) RFP0[3] RFP0[2] RFP0[1] RFP0[0] PKP0[3] PKP0[2] PKP0[1] PKP0[0] PKP1[4] PKP1[3] PKP1[2] PKP1[1] PKP1[0] PKP2[4] PKP2[3] PKP2[2] PKP2[1] PKP2[0] PKP3[4] PKP3[3] PKP3[2] PKP3[1] PKP3[0] PKP4[4] PKP4[3] PKP4]2] PKP4]1] PKP4]0] PKP5[4] PKP5[3] PKP5]2] PKP5]1] PKP5]0] PKP6[4] PKP6[3] PKP6[2] PKP6[1] PKP6[0] PKP7[4] PKP7[3] PKP7[2] PKP7[1] PKP7[0] PKP8[3] PKP8[2] PKP8[1] PKP8[0] RFP1[3] RFP1[2] RFP1[1] RFP1[0] OSP1[2]OSP1[1]OSP1[0] OSP0[4] OSP0[3]OSP0[2]OSP0[1]OSP0[0] Set-up Contents Variable resistor VRHP The voltage of grayscale number 3 is selected by the 16 to 1 selector The voltage of grayscale number 6 is selected by the 32 to 1 selector The voltage of grayscale number 11 is selected by the 32 to 1 selector The voltage of grayscale number 20 is selected by the 32 to 1 selector The voltage of grayscale number 31 is selected by the 32 to 1 selector The voltage of grayscale number 43 is selected by the 32 to 1 selector The voltage of grayscale number 52 is selected by the 32 to 1 selector The voltage of grayscale number 57 is selected by the 32 to 1 selector The voltage of grayscale number 60 is selected by the 16 to 1 selector The voltage of grayscale number 1 is selected by the 16 to 1 selector The voltage of grayscale number 62 is selected by the 7 to 1 selector Variable resistor VRLP -When MVA_EN=1, The Gamma correction select to MVA type -When MVA_EN=0, The Gamma correction don’t select to MVA type Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Ver. 1.7 Availability Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes 196 2008.04.18 ST7787 Default Status Power On Sequence S/W Reset H/W Reset Default Value Not Fixed Not Fixed Not Fixed -----------------GMCTRP1 (E0h) Legend Command Parameter Display Flow Chart 1st Parameter: | 13th Parameter Action Mode Sequential transfer Ver. 1.7 197 2008.04.18 ST7787 10.2.23 GMCTRN1 (E1h): Gamma (‘-’polarity) Correction Characteristics Setting E1H GMCTRP0 (Gamma ‘+’polarity Correction Characteristics Setting) RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 Inst / Para D/CX WRX GMCTRP1 0 -↑ 1 - 1 1 1 st 1 1 1 1 1 1 1 1 1 1 1 1 1 -↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 Parameter nd 2 Parameter rd 3 Parameter th 4 Parameter th 5 Parameter th 6 Parameter th 7 Parameter th 8 Parameter th 9 Parameter th 10 Parameter th 11 Parameter th 12 Parameter th 13 Parameter -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ -↑ Register Group Negative Polarity High level adjustment RFN0[3:0] 0 PKN1[4:0] PKP2[4:0] PKN3[4:0] PKN4[4:0] Mid level adjustment PKN5[4:0] PKN6[4:0] PKN7[4:0] PKN8[3:0] RFN1[3:0] OSN1[2:0] Low level adjustment Restriction OSN0[4:0] Default Ver. 1.7 0 0 (E1h) Set-up Contents Variable resistor VRHN The voltage of grayscale number 3 is selected by the 16to 1 selector The voltage of grayscale number 6 is selected by the 32 to 1 selector The voltage of grayscale number 11 is selected by the 32 to 1 selector The voltage of grayscale number 20 is selected by the 32 to 1 selector The voltage of grayscale number 31 is selected by the 32 to 1 selector The voltage of grayscale number 43 is selected by the 32 to 1 selector The voltage of grayscale number 52 is selected by the 32 to 1 selector The voltage of grayscale number 57 is selected by the 64 to 1 selector The voltage of grayscale number 60 is selected by the 16 to 1 selector The voltage of grayscale number 1 is selected by the 16 to 1 selector The voltage of grayscale number 62 is selected by the 7 to 1 selector Variable resistor VRLN Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability 0 RFN0[3] RFN0[2] RFN0[1] RFN0[0] PKN0[3] PKN0[2] PKN0[1] PKN0[0] PKN1[4] PKN1[3] PKN1[2] PKN1[1] PKN1[0] PKN2[4] PKN2[3] PKN2[2] PKN2[1] PKN2[0] PKN3[4] PKN3[3] PKN3[2] PKN3[1] PKN3[0] PKN4[4] PKN4[3] PKN4]2] PKN4]1] PKN4]0] PKN5[4] PKN5[3] PKN5]2] PKN5]1] PKN5]0] PKN6[4] PKN6[3] PKN6[2] PKN6[1] PKN6[0] PKN7[4] PKN7[3] PKN7[2] PKN7[1] PKN7[0] PKN8[3] PKN8[2] PKN8[1] PKN8[0] RFN1[3] RFN1[2] RFN1[1] RFN1[0] OSN1[2]OSN1[1]OSN1[0] OSN0[4] OSN0[3] OSN0[2]OSN0[1]OSN0[0] PKN0[3:0] Description 0 (Code) Availability Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence S/W Reset H/W Reset Default Value Not Fixed Not Fixed Not Fixed 198 2008.04.18 ST7787 Legend GMCTRP1 (E1h) Command Parameter Display Flow Chart 1st Parameter: | 13th Parameter Action Mode Sequential transfer Ver. 1.7 199 2008.04.18 ST7787 10.2.24 Vcom multi_mode (FBh): DEH Inst / Para D/CX WRX RDX D17-8 Vcom_multi_mode 1st Parameter 0 1 ↑ ↑ 1 1 D7 D6 1 1 1 - 0 OTP-Load D5 D4 D3 D2 D1 D0 (Code) 1 1 1 0 1 1 (FBh) Vcom _multi_mode 1 1 1 1 1 -Vcom multi_mode Description For power saving, please set the Vcom_multi_mode=1. Restriction Register Availability Default -If this register not using the register need be reserved. Status Availability Normal Mode On, Idle Mode Ooff, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode Off, Idle Mode On, Sleep Out Yes Sleep In No Status Default Value Power On Sequence S/W Reset H/W Reset 7Fh 7Fh 7Fh Legend Command Parameter Display Flow Chart Action Mode Sequential transfer Ver. 1.7 200 2008.04.18 ST7787 11. Display Module Default Position The default position of the display is always as follow, when MADCTL’s (36h) parameter is 00h. Display driver The 1st pixel on the display. This is also the 1st access location Ver. 1.7 RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB 201 RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB 2008.04.18 ST7787 12. Power structure 12.1. Driver IC Operating voltages Specification VGH(12V~16.5V) AVDD(4.9V~6.6V) GVDD(3.0V~5.0V) VDD=(2.45V-3.0V) Charge pump VCOMH(2.5V~5.0V) Internal Reference Voltage AGND=0V VCOML(-2.5V~0V) VCL(-3.3V~-2.2V) VGL(-5V~-14V) Remark 1. AVDD supply to all power source (exclude VGH, VGL) 2. Source output range: 0.1V ~ AVDD-0.1V 3. Linear Range: 0.2V ~ AVDD-0.2V (For all output voltage, but exclude VGH, VGL) 4. Above operating voltages is min range. Ver. 1.7 202 2008.04.18 ST7787 12.2 Power Booster Circuit 12.2.1 VCI1 generate from VDD regulator Source Output Circuit Block VDD CVDD S1 | S720 Vref Reference Voltage generator AVDD Gray reference Circuit Block (Gamma) VCI1 Vref AVDD VC [2:0} GVDD Vref VRH [4:0} AGND VCI1 CVCI1 CVci1 AGND AVDD C11 Boost 1 (x2)VCI1 set-yp 1 BT[2:0] DC[2:0] Or DCT[2:0] C12 VCOMH Vref VMH[6:0} + VMOF[6:0] AVDD CAVDD CVMH AGND VCOM C21 VGH CVGH Boost 2,3,4 (x4, x5, x6)VCI1 (x-2, x-4, x-5)VCI1 (x-1)VCI1 VDD VCOML VMH[6:0} + VMOF[6:0] AGND C23 CVML VGL Set-Up 2,3,4 VCL CVGL VGH C22 VCL VGL BT[2:0] DC[2:0] or DCT[2:0] Vref Gate output Cirrect Block G1 | G320 VDDI CVCL CVDDI Fig. 12.2.1 Power Booster Structure (1) Ver. 1.7 203 2008.04.18 ST7787 12.2.2 EXTERNAL COMPONENTS CONNECTION Pad Name VDDI VDD VCC AGND DGND C23P, C23N C22P, C22N C21P, C22N C12P, C12N C11P, C11N AVDD VCI1 VGH VGL VCL VREF GVDD VCOMH VCOML VC1S VGL Ver. 1.7 Rated (Min) Voltage Connection VDDI (Logic Power) VDD (Analog Power) Connect to Capacitor (Max 3V): VCC -------||-------- GND Analog ground (Connect to GND) Digital ground (Connect to GND) Connect to Capacitor: C23P -------||--------C23N Connect to Capacitor: C22P -------||--------C22N Connect to Capacitor: C21P -------||--- -----C21N Connect to Capacitor: C12P -------||--------C12N Connect to Capacitor: C11P -------||--------C11N Connect to Capacitor: AVDD -------||-------- GND Connect to Capacitor: AVDD -------||-------- GND Connect to Capacitor: VGH -------||-------- GND Connect to Capacitor: VGL -------||-------- GND Connect to Capacitor: VCL -------||-------- GND Connect to Capacitor: VREF -------||-------- GND Connect to Capacitor: GVDD -------||-------- GND Connect to Capacitor: VCOMH-------||--------- GND Connect to Capacitor: VCOML -------||-------- GND Connect to Capacitor: VC1S -------||-------- GND Connect to Schottky diode: VGL -------.|-------- GND 204 Typical capacitance value 10.0V 10.0V 10.0V 1.0 uF 1.0 uF 1.0 uF 25.0V 25.0V 10.0V 10.0V 10.0V 10.0V 10.0V 25.0V 25.0V 10.0V 10.0V 10.0V 10.0V 10.0V 10V 30V 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0uF Schottky diode 2008.04.18 ST7787 13. Gamma structure 13.1 STRUCTURE OF GRAYSCALE AMPLIFIER The structure of grayscale amplifier is shown as below. 13 voltage levels (VIN0-VIN12) between GVDD and VGS are determined by the high/ mid/ low level adjustment registers. Each mid-adjustment level is split into 64 levels again by the internal ladder resistor network. As a result, grayscale amplifier generates 64 voltage levels ranging from V0 to V63 and outputs one of 64 levels. Positive frame Negative frame GVDD GVDD 30R 30R RF0P[3:0] 0~2 R 2.5 R 2.5 0~2 Step : 1.5R V63 V0 RF1P[3:0] Step : 1.5R OS0N[3:0] 0~3 0R Step : 2R 8R 0~2 OS1N[2:0] V1 Step : 4R V62 PKP0[3:0] V3 PKN8[3:0] V60 PKP1[4:0] V6 PKN7[4:0] V57 PKP2[4:0] V11 PKN6[4:0] V52 PKP3[4:0] V20 PKN5[4:0] PKP4[4:0] V31 PKN4[4:0] PKP5[4:0] V43 PKN3[4:0] V20 PKP6[4:0] V52 PKN2[4:0] V11 PKP7[4:0] V57 PKN1[4:0] V6 V60 PKN0[3:0] V3 PKP8[3:0] V43 184R V31 V1 V62 OS1P[2:0] 8R 0~2 Step : 4R RF1N[3:0] 0R 0~3 V0 V63 OS0P[3:0] R 2.5 0~2 Step : 1.5R RF0N[3:0] R 2.5 0~2 Step : 1.5R 30R 30R Ver. 1.7 Step : 2R 205 2008.04.18 ST7787 13.2 Gamma Voltage Formula (Positive/ Negative Polarity) Grayscale 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Ver. 1.7 Voltage Formula(Positive) VINP0 VINP1 V1-(V1-V3)*(16/30) VIN2 V3-(V3-V6)*(21/60) V3-(V3-V6)*(41/60) VINP3 V6-(V6-V11)*(13/60) V6-(V6-V11)*(26/60) V6-(V6-V11)*(38/60) V6-(V6-V11)*(49/60) VINP4 V11-(V11-V20)*(8/60) V11-(V11-V20)*(16/60) V11-(V11-V20)*(24/60) V11-(V11-V20)*(31/60) V11-(V11-V20)*(38/60) V11-(V11-V20)*(44/60) V11-(V11-V20)*(50/60) V11-(V11-V20)*(55/60) VINP5 V20-(V20-V31)*(6/60) V20-(V20-V31)* (12/60) V20-(V20-V31)* (18/60) V20-(V20-V31)* (24/60) V20-(V20-V31)* (30/60) V20-(V20-V31)* (35/60) V20-(V20-V31)* (40/60) V20-(V20-V31)* (45/60) V20-(V20-V31)* (50/60) V20-(V20-V31)* (55/60) VINP6 V31-(V31-V43)*(5/60) V31-(V31-V43)*(10/60) V31-(V31-V43)*(15/60) V31-(V31-V43)*(20/60) V31-(V31-V43)*(25/60) V31-(V31-V43)*(30/60) V31-(V31-V43)*(35/60) V31-(V31-V43)*(40/60) V31-(V31-V43)*(45/60) V31-(V31-V43)*(55/60) V31-(V31-V43)*(60/60) VINP7 V43-(V43-V52)*(2/18) V43-(V43-V52)*(4/18) V43-(V43-V52)*(6/18) V43-(V43-V52)*(8/18) V43-(V43-V52)*(10/18) V43-(V43-V52)*(12/18) V43-(V43-V52)*(14/18) V43-(V43-V52)*(16/18) VINP8 V52-(V52-V57)*(7/40) V52-(V52-V57)*(15/40) 206 Voltage Formula(Negative) VINN 0 VINN 1 V1-(V1-V3)*(17/30) VINN 2 V3-(V3-V6)*(12/30) V3-(V3-V6)*(22/30) VINN 3 V6-(V6-V11)*(9/40) V6-(V6-V11)*(17/40) V6-(V6-V11)*(25/40) V6-(V6-V11)*(33/40) VINN 4 V11-(V11-V20)*(4/36) V11-(V11-V20)*(8/36) V11-(V11-V20)*(12/36) V11-(V11-V20)*(16/36) V11-(V11-V20)*(20/36) V11-(V11-V20)*(24/36) V11-(V11-V20)*(28/36) V11-(V11-V20)*(32/36) VINN 5 V20-(V20-V32)*(5/60) V20-(V20-V32)* (10/60) V20-(V20-V32)* (15/60) V20-(V20-V32)* (20/60) V20-(V20-V32)* (25/60) V20-(V20-V32)* (30/60) V20-(V20-V32)* (35/60) V20-(V20-V32)* (40/60) V20-(V20-V32)* (45/60) V20-(V20-V32)* (50/60) V20-(V20-V32)* (55/60) VINN6 V32-(V32-V43)*(5/60) V32-(V32-V43)*(10/60) V32-(V32-V43)*(15/60) V32-(V32-V43)*(20/60) V32-(V32-V43)*(25/60) V32-(V32-V43)*(30/60) V32-(V32-V43)*(36/60) V32-(V32-V43)*(42/60) V31-(V31-V43)*(48/60) V31-(V31-V43)*(54/60) VINN 7 V43-(V43-V52)*(5/60) V43-(V43-V52)*(10/60) V43-(V43-V52)*(16/60) V43-(V43-V52)*(22/60) V43-(V43-V52)*(29/60) V43-(V43-V52)*(36/60) V43-(V43-V52)*(44/60) V43-(V43-V52)*(52/60) VINN 8 V52-(V52-V57)*(11/60) V52-(V52-V57)*(22/60) 2008.04.18 ST7787 55 56 57 58 59 60 61 62 63 Ver. 1.7 V52-(V52-V57)*(23/40) V52-(V52-V57)*(31/40) VINP9 V57-(V57-V60)*(8/30) V57-(V57-V60)*(18/30) VINP10 V60-(V60-V62)*(13/30) VINP11 VINP12 207 V52-(V52-V57)*(34/60) V52-(V52-V57)*(47/60) VINN 9 V57-(V57-V60)*(19/60) V57-(V57-V60)*(39/60) VINN 10 V60-(V60-V62)*(14/30) VINN 11 VINN12 2008.04.18 ST7787 14. Example Connection with Panel direction and Different Resolution 14.1 Application of connection with panel direction Case 1: (This is default case) - 1 Pixel is at Left Top of the panel - RGB filter order = RGB st - Direction default setting (H/W) G 320 G 319 ST7787 (Bump Down) S1 S 720 G1 SMX = ’0’ SMY = ‘0’ G2 SRGB = ‘0’ S1 = Filter R 00h 01h 02h ------------EDh EEh EFh S2 = Filter G G1 S3 = Filter B G2 G3 | | | | | | | | | | | G317 - Display direction control (S/W) G4 | | | | | | | | | | | G318 1 st Pixel - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV IC (Bump down) LCD Front side G319 CF Glass TFT Glass G320 Case 2: - 1 Pixel is at Left Top of the panel - RGB filter order = BGR st - Direction default setting (H/W) G 320 G 319 G1 ST7787 (Bump Down) S1 S 720 SMX = ’0’ SMY = ‘0’ G2 SRGB = ‘1 S1 = Filter B 00h 01h 02h ------------EDh EEh EFh S2 = Filter G G1 S3 = Filter R G2 G3 | | | | | | | | | | | G317 - Display direction control (S/W) 1 st Pixel G4 | | | | | | | | | | | G318 - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV IC (Bump down) LCD Front side CF Glass TFT Glass G319 G320 Ver. 1.7 208 2008.04.18 ST7787 Case 3: - 1 Pixel is at Righ Bottom of the panel - RGB filter order = RGB st - Direction default setting (H/W) G 320 G 319 G1 ST7787 (Bump Down) S1 S 720 SMX = ’1’ SMY = ‘1’ G2 SRGB = ‘0’ S1 = Filter R 00h 01h 02h ------------EDh EEh EFh S2 = Filter G G1 S3 = Filter B G2 G3 | | | | | | | | | | | G317 - Display direction control (S/W) G4 | | | | | | | | | | | G318 1 st Pixel - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV IC (Bump down) LCD Front side CF Glass TFT Glass G319 G320 Case 4: - 1 Pixel is at Righ Bottom of the panel - RGB filter order = BGR st G 320 G 319 G1 ST7787 (Bump Down) S1 S 720 - Direction default setting (H/W) SMX = ’1’ G2 SMY = ‘1’ SRGB = ‘1’ 00h 01h 02h ------------EDh EEh EFh S1 = Filter B G1 G2 G3 | | | | | | | | | | | G317 1 st Pixel S2 = Filter G S3 = Filter R G4 | | | | | | | | | | | G318 - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV IC (Bump down) LCD Front side CF Glass TFT Glass G319 G320 Ver. 1.7 209 2008.04.18 ST7787 14.2 Application of connection with Different resolution RAM size=240 x 320 x 18-bits (Used) Display size = 240 RGB x 320 1). Example for SMX=SMY=’0’ G 320 G 319 G R A M s i z e (240x 320x 18-b i t s ) (0,0) 00h 02h --- --- --- --- --- EEh EFh 00h 01h 02h | | | | | | | | | | | | | 13Eh 13Fh ST7787 (Bump Down) S 720 S1 G1 D1 D2 -- -- -- -- -- G2 D239 D240 G1 G2 G3 | | | | | | | | | | | G317 (0,0) (239,319) G4 | | | | | | | | | | | G318 1 st Pixel G319 G320 (239,319) - Display direction control (S/W) - Direction default setting (H/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV SMX = ’0’ SMY = ‘0’ SRGB = ‘0’ 2). Example for SMX=SMY=’1’ G 320 G 319 G R A M s i z e (240x 320x 18-b i t s ) G1 00h 02h --- --- --- --- --- EEh EFh 00h 01h 02h | | | | | | | | | | | | | 13Eh 13Fh Ver. 1.7 ST7787 (Bump Down) S1 S 720 D1 D2 -- -- -- -- -- G2 D239 D240 G1 G2 G3 | | | | | | | | | | | G317 (0,0) (239,319) (239,319) 1 st P ixel G4 | | | | | | | | | | | G318 G319 G320 - Display direction control (S/W) (0,0) - Direction default setting (H/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV SMX = ’1’ SMY = ‘1’ SRGB = ‘0’ 210 2008.04.18 ST7787 14.3 MicroProcessor Interface applications 14.3.1 8080-Seriers MCU + SPI Interface (RCM = ‘00’, P68=’0’, IM2=’1’) 14.3.1.1 8080-Series MCU Interface for 8-bits data bus (IM1, IM0=”00”) Host ST7787 RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 “0” “0” “0” Note: RCM = ‘0x’ IM2=’0’, SPI I/F IM2=’1’, MCU I/F “00” IM2 D/CX WRX RDX D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.1.1 8080-Series MCU Interface for 8-bits data bus 14.3.1.2 8080-Series MCU Interface for 16-bits data bus (IM1, IM0=”01”) Host ST7787 RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 D15 to D8 “0” “0” Note: RCM = ‘0x’ IM2=’0’, SPI I/F IM2=’1’, MCU I/F “01” IM2 D/CX WRX RDX D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.1.2 8080-Series MCU Interface for 16-bits data bus Ver. 1.7 211 2008.04.18 ST7787 14.3.1.3 8080-Series MCU Interface for 9-bits data bus (IM1, IM0=”10”) Host RESX TE ST7787 RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D8 to D1 D0 “0” “0” “0” Note: RCM = ‘0x’ IM2=’0’, SPI I/F IM2=’1’, MCU I/F “10” IM2 D/CX WRX RDX D8 to D1 D0 D15 to D9 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.1.3 8080-Series MCU Interface for 9-bits data bus 14.3.1.4 8080-Series MCU Interface for 18-bits data bus (IM1, IM0=”11”) Host ST7787 RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 D17 to D8 “0” Note: RCM = ‘0x’ IM2=’0’, SPI I/F IM2=’1’, MCU I/F “11” IM2 D/CX WRX RDX D7 to D1 D0 D17 to D8 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.1.4 8080-Series MCU Interface for 18-bits data bus Ver. 1.7 212 2008.04.18 ST7787 14.3.2 6800-Seriers MCU + SPI Interface (RCM = ‘00’, P68=’1’, IM2=’1’) 14.3.2.1 6800-Series MCU Interface for 8-bits data bus (IM1, IM0=”00”) Host ST7787 RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 “0” “0” “1” Note: RCM = ‘0x’ IM2=’0’, SPI I/F IM2=’1’, MCU I/F “00” IM2 D/CX R/WX E D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.2.1 6800-Series MCU Interface for 8-bits data bus 14.3.2.2 6800-Series MCU Interface for 16-bits data bus (IM1, IM0=”01”) Host ST7787 RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 D15 to D8 “0” “1” Note: RCM = ‘0x’ IM2=’0’, SPI I/F IM2=’1’, MCU I/F “01” IM2 D/CX R/WX E D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.2.2 6800-Series MCU Interface for 16-bits data bus Ver. 1.7 213 2008.04.18 ST7787 14.3.2.3 6800-Series MCU Interface for 9-bits data bus (IM1, IM0=”10”) Host ST7787 RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D8 to D1 D0 “0” “0” “1” Note: RCM = ‘0x’ IM2=’0’, SPI I/F IM2=’1’, MCU I/F “10” IM2 D/CX R/WX E D8 to D1 D0 D15 to D9 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.2.3 6800-Series MCU Interface for 9-bits data bus 14.3.2.4 6800-Series MCU Interface for 18-bits data bus (IM1, IM0=”11”) Host ST7787 RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX ) RDX(E) D7 to D1 D0 D17 to D8 “1” Note: RCM = ‘0x’ IM2=’0’, SPI I/F IM2=’1’, MCU I/F “11” IM2 D/CX R/WX E D7 to D1 D0 D17 to D8 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.2.4 6800-Series MCU Interface for 18-bits data bus Ver. 1.7 214 2008.04.18 ST7787 14.3.3 RGB Interface (RCM = ‘1’) 14.3.3.1 RGBInterface for 6-bits Data Width Fig. 14.3.3.1 RGB Interface for 6-bits data width 14.3.3.2 RGBInterface for 16-bits Data Width Fig. 14.3.3.2 RGB Interface for 16-bits data width Ver. 1.7 215 2008.04.18 ST7787 14.3.3.3 RGBInterface for 18-bits Data Width Fig. 14.3.3.3 RGB Interface for 18-bits data width Ver. 1.7 216 2008.04.18 ST7787 11. Revise History ST7787 Serial Specification Revision History Version Date 0.5B 2007/02/06 1.0 2007/3/2 Modify Power on and off sequence 1.0 2007/3/2 Add FBH command 1.1 2007/06/14 1.2 2007/9/6 1.3 2007/9/11 1.4 2007/10/2 1.5 2007/11/26 1.6 2008/3/6 1.7 2009/4/18 Ver. 1.7 Description Page Add timing value Modify the operation temperature range Modify the command 3Ah Modify gamma structure Removed the description of 4-line Modify 3SPI Interface description Modify “RAMHD” typo to “RAMRD” Modify VIPF[3:0] typo Modify the description of power on/off sequence(9.15) Remove table 9.17.3.1 reset input timing(9.17.3) Modify the figure of reset timing (9.17.3) Modify the waiting time of SWReset to 120ms(10.1.2) Modify the waiting time of SLPout to 120ms(10.1.12) Modify the description of command E0h & E1h Modify power consumption IDDI (Unit) Modify operation temperature range Modify RGB Interface application circuit Modify Power On Sequence on RGB Mode 2 from VDDIVDD to VDDVDDI(9.9.6.4) Modify Power OFF Sequence on RGB Mode 2 from VDDIVDD to VDDVDDI(9.9.6.5) Modify WRX level on RGB mode from VDDI or DGND to VDDI only Modify SCL signal on SPI mode during proch area from clock to Hi level 217 P2 P157 P206 P22 P34 P142 P157 P91 P96 P96 P111 P124 P196, P198 P29 P27~P30, P32~33 P215~216 P73 P74 P22,P215,P216 P40,P44 2008.04.18