ST ST8011 120 Output LCD Segment driver IC Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change n DESCRIPTION The ST8011 is a 120-output segment driver IC suitable for driving small/medium scale dot matrix LCD panels, and is used in PDA or electronic dictionary . The ST8011 is good as a segment driver, and it can create a low power consuming, high-resolution LCD. n FEATURES Ÿ Number of LCD drive outputs: 120 Ÿ Supply voltage for LCD drive: Max +16V Ÿ Supply voltage for the logic system: +2.5 to +5.5 V Ÿ Low power consumption Ÿ Package: 136-pin COB. (Segment mode) Ÿ Shift clock frequency - 20 MHz (MAX.): VDD = +5.0 ± 0.5 V - 15 MHz (MAX.): VDD = +3.0 to + 4.5 V - 12 MHz (MAX.): VDD = +2.5 to + 3.0 V Ÿ Adopts a data bus system Ÿ 4-bit parallel / serial input modes are selectable with a mode (P/S) pin Ÿ Automatic transfer function of an enable signal Ÿ Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 120 bits of input data Ÿ Line latch circuits are reset when XDISPOFF active V1.3 1/ 20 2004/09/08 ST8011 n ST8011 Serial Specification Revision History ST8011 Serial Specification Revision History Version 0.0B V1.3 Date Description 2002/10/14 Preliminary version 1.0 2003/07/28 Final Version 1.1 2003/11/12 Modify the pin pitch 1.2 2004/04/05 Add application timing block diagram 1.3 2004/09/08 Define timing(tLSW ) of Segment Mode. P17~P19 2/20 2004/09/08 ST8011 n Pad Arrangement Chip size: 4860(µm) × 2220(µm) Pad size: 80(µm) × 80(µm) Pin Pitch: 100~110 µm SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG25 SEG24 SEG26 SEG27 SEG29 SEG28 SEG31 SEG30 SEG32 SEG33 SEG34 SEG11 43 SEG10 42 SEG9 SEG41 75 SEG42 74 44 45 SEG12 SEG40 73 SEG13 SEG39 72 SEG14 46 71 SEG15 47 70 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 68 67 69 SEG38 SEG35 SEG36 SEG37 41 SEG44 77 40 SEG7 SEG45 78 39 SEG6 38 SEG5 37 SEG4 80 SEG47 79 SEG46 76 SEG8 SEG43 36 82 35 SEG2 SEG50 83 34 SEG1 33 SEG0 81 SEG3 SEG49 SEG48 V3 18 V2 17 V0 16 SEG119 15 SEG118 14 SEG117 13 SEG116 12 SEG115 11 SEG114 10 SEG113 9 SEG112 8 SEG111 7 SEG110 6 SEG109 5 SEG108 4 SEG107 3 SEG106 136 SEG101 SEG102 SEG103 SEG105 1 135 SEG100 SEG99 133 132 SEG97 SEG98 134 131 SEG94 129 SEG93 130 127 SEG92 SEG95 126 SEG91 SEG96 125 128 124 SEG88 123 121 SEG87 SEG89 120 SEG85 SEG86 SEG90 119 122 118 2 SEG82 DI3 19 SEG81 DI2 20 SEG79 SEG80 DI1 21 SEG78 DI0 22 SEG77 EIO1 23 SEG76 EIO2 24 SEG75 XCK 25 SEG74 FR VDD 26 SEG73 SEG84 SEG71 SEG72 117 SEG69 SEG70 SEG83 SEG68 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 SEG67 98 SEG66 97 SEG64 SEG65 96 SEG63 94 95 SEG62 93 SEG61 92 SEG60 LP 27 91 SEG59 XDISPOFF 28 90 SEG58 L/R 89 SEG57 ST8011 88 SEG56 PS 30 29 86 87 SEG54 SEG55 VSS 31 85 SEG53 32 84 SEG52 L/R SEG51 SEG104 PIN1 Substrate Connect to Vss. V1.3 3/20 2004/09/08 ST8011 Pad Location Coordinates Pad.No V1.3 Function X Y Pad.No Function X Y 1 SEG104 2385.00 1065.00 69 SEG36 -2385.00 -1065.00 2 SEG105 2265.00 1065.00 70 SEG37 -2265.00 -1065.00 3 SEG106 2155.00 1065.00 71 SEG38 -2155.00 -1065.00 4 SEG107 2050.00 1065.00 72 SEG39 -2050.00 -1065.00 5 SEG108 1950.00 1065.00 73 SEG40 -1950.00 -1065.00 6 SEG109 1850.00 1065.00 74 SEG41 -1850.00 -1065.00 7 SEG110 1750.00 1065.00 75 SEG42 -1750.00 -1065.00 8 SEG111 1650.00 1065.00 76 SEG43 -1650.00 -1065.00 9 SEG112 1550.00 1065.00 77 SEG44 -1550.00 -1065.00 10 SEG113 1450.00 1065.00 78 SEG45 -1450.00 -1065.00 11 SEG114 1350.00 1065.00 79 SEG46 -1350.00 -1065.00 12 SEG115 1250.00 1065.00 80 SEG47 -1250.00 -1065.00 13 SEG116 1150.00 1065.00 81 SEG48 -1150.00 -1065.00 14 SEG117 1050.00 1065.00 82 SEG49 -1050.00 -1065.00 15 SEG118 950.00 1065.00 83 SEG50 -950.00 -1065.00 16 SEG119 850.00 1065.00 84 SEG51 -850.00 -1065.00 17 V0 750.00 1065.00 85 SEG52 -750.00 -1065.00 18 V2 650.00 1065.00 86 SEG53 -650.00 -1065.00 19 V3 550.00 1065.00 87 SEG54 -550.00 -1065.00 20 DI3 450.00 1065.00 88 SEG55 -450.00 -1065.00 21 DI2 350.00 1065.00 89 SEG56 -350.00 -1065.00 22 DI1 250.00 1065.00 90 SEG57 -250.00 -1065.00 23 DI0 150.00 1065.00 91 SEG58 -150.00 -1065.00 24 EIO1 50.00 1065.00 92 SEG59 -50.00 -1065.00 25 EIO2 -50.00 1065.00 93 SEG60 50.00 -1065.00 26 XCK -150.00 1065.00 94 SEG61 150.00 -1065.00 27 FR -250.00 1065.00 95 SEG62 250.00 -1065.00 28 LP -350.00 1065.00 96 SEG63 350.00 -1065.00 29 VDD -450.00 1065.00 97 SEG64 450.00 -1065.00 30 XDISPOFF -550.00 1065.00 98 SEG65 550.00 -1065.00 31 PS -650.00 1065.00 99 SEG66 650.00 -1065.00 32 VSS -750.00 1065.00 100 SEG67 750.00 -1065.00 33 SEG0 -850.00 1065.00 101 SEG68 850.00 -1065.00 34 SEG1 -950.00 1065.00 102 SEG69 950.00 -1065.00 35 SEG2 -1050.00 1065.00 103 SEG70 1050.00 -1065.00 36 SEG3 -1150.00 1065.00 104 SEG71 1150.00 -1065.00 37 SEG4 -1250.00 1065.00 105 SEG72 1250.00 -1065.00 4/20 2004/09/08 ST8011 Pad.No V1.3 Function X Y Pad.No Function X Y 38 SEG5 -1350.00 1065.00 106 SEG73 1350.00 -1065.00 39 SEG6 -1450.00 1065.00 107 SEG74 1450.00 -1065.00 40 SEG7 -1550.00 1065.00 108 SEG75 1550.00 -1065.00 41 SEG8 -1650.00 1065.00 109 SEG76 1650.00 -1065.00 42 SEG9 -1750.00 1065.00 110 SEG77 1750.00 -1065.00 43 SEG10 -1850.00 1065.00 111 SEG78 1850.00 -1065.00 44 SEG11 -1950.00 1065.00 112 SEG79 1950.00 -1065.00 45 SEG12 -2050.00 1065.00 113 SEG80 2050.00 -1065.00 46 SEG13 -2155.00 1065.00 114 SEG81 2155.00 -1065.00 47 SEG14 -2265.00 1065.00 115 SEG82 2265.00 -1065.00 48 SEG15 -2385.00 1065.00 116 SEG83 2385.00 -1065.00 49 SEG16 -2385.00 955.00 117 SEG84 2385.00 -955.00 50 SEG17 -2385.00 850.00 118 SEG85 2385.00 -850.00 51 SEG18 -2385.00 750.00 119 SEG86 2385.00 -750.00 52 SEG19 -2385.00 650.00 120 SEG87 2385.00 -650.00 53 SEG20 -2385.00 550.00 121 SEG88 2385.00 -550.00 54 SEG21 -2385.00 450.00 122 SEG89 2385.00 -450.00 55 SEG22 -2385.00 350.00 123 SEG90 2385.00 -350.00 56 SEG23 -2385.00 250.00 124 SEG91 2385.00 -250.00 57 SEG24 -2385.00 150.00 125 SEG92 2385.00 -150.00 58 SEG25 -2385.00 50.00 126 SEG93 2385.00 -50.00 59 SEG26 -2385.00 -50.00 127 SEG94 2385.00 50.00 60 SEG27 -2385.00 -150.00 128 SEG95 2385.00 150.00 61 SEG28 -2385.00 -250.00 129 SEG96 2385.00 250.00 62 SEG29 -2385.00 -350.00 130 SEG97 2385.00 350.00 63 SEG30 -2385.00 -450.00 131 SEG98 2385.00 450.00 64 SEG31 -2385.00 -550.00 132 SEG99 2385.00 550.00 65 SEG32 -2385.00 -650.00 133 SEG100 2385.00 650.00 66 SEG33 -2385.00 -750.00 134 SEG101 2385.00 750.00 67 SEG34 -2385.00 -850.00 135 SEG102 2385.00 850.00 68 SEG35 -2385.00 -955.00 136 SEG103 2385.00 955.00 5/20 2004/09/08 ST8011 PIN DESCRIPTION SYMBOL DESCRIPTION I/O No of Num SEG0-SEG119 O LCD drive output 120 V0,V2,V3 P Power supply for LCD drive 3 XDISPOFF I Control input for output of non-select level 1 VDD P Power supply for logic system (+2.5 to +5.5 V) 1 EIO2, EIO1 I/O Input/output for chip selection at segment mode and FLM input output function at com/seg mix mode or common mode 2 DI0-DI3 I Display data input at segment mode 4 XCK I Clock input for taking display data at segment mode 1 L/R I Display data shift direction selection I Latch pulse input for display data at segment mode/ LP FR Shift clock input for shift register at common mode I AC-converting signal input for LCD drive waveform 1 1 This is the parallel data input/serial data input switch terminal. P/S I P/S=”H”: Parallel data input. 1 P/S=”L”: Serial data input. VSS n V1.3 P Ground (0 V) 1 BLOCK DIAGRAM 6/20 2004/09/08 ST8011 n INPUT/OUTPUT CIRCUITS V DD I T o In te rn a l C irc u it A p p lic a b le P in s X D IS P O F F , D I 3 ~ D I 0 , L P , F R , P /S ,L /R V s s (0 V ) Input Circuit V DD To Internal Circuit I/O Control Signal Vss (0V) Vss (0V) V DD Output Signal Application Pins EIO 1 , EIO 2 Control Signal Vss (0V) Input/Output Circuit V1.3 7/20 2004/09/08 ST8011 n FUNCTIONAL DESCRIPTION Pin Functions u SYMBOL FUNCTION VDD Logic system power supply pin, connected to +2.5 to +5.5 V. VSS Ground pin, connected to 0 V. This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or V0 V2 V3 through changing the impedance using an op. amp. Voltage levels are determined based on VSS, and must maintain the relative magnitudes shown below. Ÿ V0 ≧ V2 ≧ V3≧ Vss Input pins for display data Ÿ In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0. DI3-DI0 Ÿ In serial input mode, input data into the 1 pin DI0. Connect DI3-DI1 to VSS or VDD Ÿ Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. XCK LP Clock input pin for taking display data * Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data Ÿ Data is latched at the falling edge of the clock pulse. Control input pin for output of non-select level Ÿ The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Ÿ When set to VSS level "L", the LCD drive output pins (SEG0-SEG119) are set to level Vss. XDISPOFF Ÿ When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /DISPOFF. When the XDISPOFF function is canceled, the driver outputs non-select level (V2 or V3), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if XDISPOFF removal time does not correspond to what is shown in AC characteristics, it cannot output the reading data correctly. Ÿ Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform Ÿ The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. FR Ÿ Normally it inputs a frame inversion signal. Ÿ The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Ÿ Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. P/S V1.3 Interface Mode selection pin Ÿ When P/S is “H” then parallel data input mode. 8/20 2004/09/08 ST8011 When P/S is “L” the serial data input mode, Input pin for selecting the reading direction of display data. Default value is LOW Ÿ When set to VSS level "L", data is read sequentially from SEG119 to SEG0. L/R Ÿ When set to VDD level "H", data is read sequentially from SEG0 to SEG119. Ÿ Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Input/output pins for chip selection. AT segment mode: Ÿ When L/R input is at VSS level "L", ElO1 is set for output, and EIO2 is set for input(connect to Vss). Ÿ When L/R input is at VDD level "H", ElO1 is set for input(connect to Vss), and EIO2 is set for ElO1, EIO2 output. Ÿ During output, set to "H" while LP • XCK is "H" and after 120 bits of data have been read, set to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is non-selected after 120 bits of data have been read. LCD drive output pins SEG0–SEG119 Ÿ Corresponding directly to each bit of the data latch, one level (V0, V2, V3, and Vss) is selected and output. Ÿ Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Functional Operations u LCD DRIVE OUTPUT VOLTAGE LEVEL FR LATCH DATA /DISPOFF L L H V3 L H H Vss H L H V2 H H H V0 X X L Vss (SEG0-SEG119) TRUTH TABLE NOTES: Ÿ L : VSS (0 V), H : VDD (+2.5 to +5.5 V), Ÿ "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage that is assigned by specification for each power pin. V1.3 9/20 2004/09/08 ST8011 RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS (A) 4-bit Parallel Input Mode u L/R L EIO1 EIO2 DATA INPUT 30 CLOCK 29 CLOCK 28 CLOCK … Output Input H Input NUMBER OF CLOCKS Output 3 CLOCK 2 CLOCK 1 CLOCK DI0 SEG0 SEG4 SEG8 … SEG108 SEG112 SEG116 Dl1 SEG1 SEG5 SEG9 … SEG109 SEG113 SEG117 DI2 SEG2 SEG6 SEG10 … SEG110 SEG114 SEG118 DI3 SEG3 SEG7 SEG11 … SEG111 SEG115 SEG119 DI0 SEG119 SEG115 SEG111 … SEG11 SEG7 SEG3 Dl1 SEG118 SEG114 SEG110 … SEG10 SEG6 SEG2 DI2 SEG117 SEG113 SEG109 … SEG9 SEG5 SEG1 DI3 SEG116 SEG112 SEG108 … SEG8 SEG4 SEG0 3 CLOCK 2 CLOCK 1 CLOCK (B) Serial Input Mode L/R EIO1 EIO2 L Output Input H Input Output DATA NUMBER OF CLOCKS INPUT 120 CLOCK 119 CLOCK 118 CLOCK … DI0 SEG0 SEG1 SEG2 … SEG117 SEG118 SEG119 Dl1 X X X X X X X DI2 X X X X X X X DI3 X X X X X X X DI0 SEG119 SEG118 SEG117 … SEG2 SEG1 SEG0 Dl1 X X X X X X X DI2 X X X X X X X DI3 X X X X X X X NOTES: Ÿ L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care "Don't care" should be fixed to "H" or "L", avoiding floating. V1.3 10/20 2004/09/08 ST8011 u (A) Connection examples of plural segment drivers When L/R = “ L” Top data Last data Data flow SEG119 SEG0 EIO2 EIO1 SEG119 SEG0 SEG119 EIO2 EIO1 L/R SEG0 EIO2 EIO1 L/R L/R DI3-DI0 FR FR LP FR LP XCK LP XCK DI3-DI0 XCK DI3-DI0 FR LP XCK XCK LP FR DI3-DI0 4 VSS (B) When L/R = “ H” VDD XCK LP FR DI3-DI0 4 EIO1 EIO2 SEG0 SEG0 SEG119 Last data Top data V1.3 L/R EIO2 SEG119 Data flow DI3-DI0 EIO1 FR L/R EIO2 LP SEG0 XCK EIO1 DI3-DI0 DI3-DI0 FR LP XCK L/R Vss 11/20 2004/09/08 ST8011 u Timing chart of 4-device cascade connection of segment drivers FR LP XCK TOP DATA DI3 - DI0 n* 1 2 LAST DATA n* device A 1 2 n* 1 2 device B n* device C 1 2 n* 1 2 device D EI (device A) EO (device A) EO (device B) EO (device C) *n = 30 in 4-bit parallel input mode *n = 120 in serial input mode V1.3 12/20 2004/09/08 ST8011 u PRECAUTIONS Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so a high current that may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating may permanently damage it. The details are as follows, Ÿ When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on XDISPOFF function. After that, cancel the XDISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level Vss on XDISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here VDD VDD VSS VDD XDISPOFF VSS VDD V0 VSS V1.3 13/20 2004/09/08 ST8011 Application Timing Block: Example 160X80 Frame and Lp falling edge (or rising edge) must >10ns Between Lp falling edge and XCK rising edge must >50ns Parallel vs. Serial Interface Diagram S1 S2 S3 S4 S5 S6 S7 S8 S15 S15 S15 S16 1 2 3 4 5 6 7 8 157 158 159 160 LP D3 D2 D1 D0 D0 V1.3 1 5 9 13 145 149 153 157 1 5 9 2 6 10 14 146 150 154 158 2 6 10 3 7 11 15 147 151 155 159 3 7 11 4 8 12 16 148 152 156 160 4 8 12 1 2 3 4 5 6 7 14/20 8 157 158 159 160 2004/09/08 ST8011 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL APPLICABLE PINS RATING UNIT VDD VDD -0.3~+7.0 V V2 V2 VDD-10~ VDD+0.3 V3 V3 -0.3~V5S+10 V -0.3 to VDD+0.3 V -45 to +125 °C Supply voltage (1) Input voltage Storage temperature VI D14-DI0, XCK, LP, L/R, FR, EIO1, EIO2, XDISPOFF TSTG NOTE 1,2 NOTES: 1. TA = +25 °C 2. The maximum applicable voltage on any pin with respect to VSS (0 V). n RECOMMENDED OPERATING Conditions PARAMETER SYMBOL APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE Supply voltage (1) VDD VDD +2.5 +5.5 V Supply voltage (2) V0 V0 +6.0 +16.0 V Operating temperature TOPR -20 +85 °C 1, 2 NOTES: 1. The applicable voltage on any pin with respect to VSS (0 V). 2. Ensure that voltages are set such that V2 ≧ V3 ≧ VSS. V1.3 15/20 2004/09/08 ST8011 n ELECTRICAL CHARACTERISTICS u DC Characteristics (VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 to +85°C) PARAMETER Input "Low" voltage SYMBOL CONDITIONS VIL VIH Output "Low" voltage VOL IOL = +0.4 mA Output "High" voltage VOH IOH = -0.4 mA ILIL VI = VSS ILIH VI = VDD |∆ VON| V0 = 30 MIN. TYP. MAX. UNIT NOTE DI3-DI0, XCK, LP, L/R 0.2VD FR, EIO1, EIO2, D XDISPOFF Input "High" voltage Input leakage current APPLICABLE PINS EIO1, EIO2 0.8VDD V +0.4 VDD-0.4 V V DI3-DI0, XCK, LP, LIR, FR, EIO1, EIO2, XDISPOFF μA +10 μA 2.0 kΩ RON Standby current ISTB VSS 50 μA 1 ISS VSS 2.0 mA 2 I0 V0 0.9 mA 4 Supply current (1) (Non-selection) Supply current (2) V 1.5 -10 Output resistance =0.5V SEG0-SEG119 V NOTES: 1. VDD = +3.0 V, V0 = +12.0 V 2. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8 MHz, no-load, El = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8 MHz, no-load, El = VSS. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8MHz, fLP = 19.2 kHz, fFR = 80 Hz, no-load. The input data is turned over by data taking clock (4-bit parallel input mode). V1.3 16/20 2004/09/08 ST8011 u AC Characteristics (VSS = 0 V, VDD = +2.5 to +3.0 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 °C) PARAMETER SYMBOL CONDITIONS MIN Shift clock period tWCK tR,tF ≤ 11ns 125 Shift clock "H" pulse width tWCKH 51 Shift clock "L" pulse width tWCKL 51 Data setup time tDS 30 Data hold time tDH 40 Latch pulse "H" pulse width tWLPH 51 Shift clock rise to latch pulse rise time tLD 0 Shift clock fall to latch pulse fall time tSL 51 Latch pulse rise to shift clock rise time tLS 51 Latch pulse fall to shift clock fall time tLH 51 Latch pulse fall to shift clock rise time tLSW 50 Enable setup time tS 36 Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD 100 DISPOFF "L" pulse width tWDL 1.2 Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, t PD2 CL = 15 pF Output delay time (3) t PD3 CL = 15 pF NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. TYP. MAX. 50 50 78 1.2 1.2 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs NOTE 1 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs NOTE 1 2 2 (VSS = 0 V, VDD = +5.0± 0.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 to +85 °C) PARAMETER SYMBOL CONDITIONS Shift clock period tWCK tR,tF ≤ 10ns Shift clock "H" pulse width tWCKH Shift clock "L” pulse width tWCKL Data setup time tDS Data hold time tDH Latch pulse "H" pulse width tWLPH Shift clock rise to latch pulse rise time tLD Shift clock fall to latch pulse fall time tSL Latch pulse rise to shift clock rise time tLS Latch pulse fall to shift clock fall time tLH Latch pulse fall to shift clock rise time tLSW Enable setup time tS Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD DISPOFF "L" pulse width tWDL Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, t PD2 CL = 15 pF Output delay time (3) t PD3 CL = 15 pF NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. V1.3 17/20 MIN. 66 23 23 15 23 30 0 50 30 30 50 15 TYP. MAX. 50 50 100 1.2 41 1.2 1.2 2 2 2004/09/08 ST8011 (VSS = 0 V, VDD = +3.0 to +4.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 °C) PARAMETER SYMBOL Shift clock period tWCK Shift clock "H" pulse width tWCKH Shift clock "L” pulse width tWCKL Data setup time tDS Data hold time tDH Latch pulse "H" pulse width tWLPH Shift clock rise to latch pulse rise time tLD Shift clock fall to latch pulse fall time tSL Latch pulse rise to shift clock rise time tLS Latch pulse fall to shift clock fall time tLH Latch pulse fall to shift clock rise time tLSW Enable setup time tS Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD DISPOFF "L" pulse width tWDL Output delay time (1) tD Output delay time (2) tPD1, t PD2 Output delay time (3) t PD3 NOTES: CONDITIONS tR,tF ≤ 10ns MIN. 82 28 28 20 23 30 0 51 30 30 50 15 TYP. MAX. 50 50 100 1.2 CL = 15 pF CL = 15 pF CL = 15 pF 57 1.2 1.2 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs NOTE 1 2 2 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. V1.3 18/20 2004/09/08 ST8011 u Timing Chart of Segment Mode tWLPH LP tLD tSL tLH tLS tWCKH tWCKL XCK tR tF tWCK DI4 - DI0 tDS LAST DATA tDH TOP DATA tWDL tSD XDISPOFF FR tPD1 LP tPD2 XDISPOFF tPD3 SEG0 - SEG119 Fig. 8 Timing Characteristics (3) V1.3 19/20 2004/09/08 ST8011 The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. V1.3 20/20 2004/09/08